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authorRajendra Nayak <rnayak@ti.com>2009-12-09 04:46:28 +0300
committerpaul <paul@twilight.(none)>2009-12-12 03:00:45 +0300
commit972c542746904b5f418284946728a61b783275ef (patch)
tree3f8b449c10e6a25df3bd216c6e039f4240d52446 /arch/arm/mach-omap2/clock44xx.h
parentdd7084138f7293f97584050d43a92cb03836974e (diff)
downloadlinux-972c542746904b5f418284946728a61b783275ef.tar.xz
ARM: OMAP4: PM: OMAP4 clock tree and clkdev registration
This patch defines all the clock nodes in OMAP4430 platform. All the clock node structs and the clkdev table is autogenerated using a python script (gen_clock_tree.py) developed by Paul Walmsley, Benoit Cousson and Rajendra Nayak. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Benoit Cousson <b-cousson@ti.com>
Diffstat (limited to 'arch/arm/mach-omap2/clock44xx.h')
-rw-r--r--arch/arm/mach-omap2/clock44xx.h23
1 files changed, 23 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/clock44xx.h b/arch/arm/mach-omap2/clock44xx.h
new file mode 100644
index 000000000000..c1bc4b6eb6b3
--- /dev/null
+++ b/arch/arm/mach-omap2/clock44xx.h
@@ -0,0 +1,23 @@
+/*
+ * OMAP4 clock function prototypes and macros
+ *
+ * Copyright (C) 2009 Texas Instruments, Inc.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_44XX_H
+#define __ARCH_ARM_MACH_OMAP2_CLOCK_44XX_H
+
+unsigned long omap3_dpll_recalc(struct clk *clk);
+unsigned long omap3_clkoutx2_recalc(struct clk *clk);
+int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
+
+/* DPLL modes */
+#define DPLL_LOW_POWER_STOP 0x1
+#define DPLL_LOW_POWER_BYPASS 0x5
+#define DPLL_LOCKED 0x7
+#define OMAP4430_MAX_DPLL_MULT 2048
+#define OMAP4430_MAX_DPLL_DIV 128
+
+extern const struct clkops clkops_noncore_dpll_ops;
+
+#endif