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authorPaul Walmsley <paul@pwsan.com>2009-05-13 03:26:32 +0400
committerpaul <paul@twilight.(none)>2009-05-13 03:27:10 +0400
commit4519c2bf433b97d091635eb51e4ba8ffa1c84d62 (patch)
tree0b36fc5e39c6a29005783c74f727c953c75e2198 /arch/arm/mach-omap2/clock.c
parentb2abb271a5705bc80478e79d95fc9f3babc2605c (diff)
downloadlinux-4519c2bf433b97d091635eb51e4ba8ffa1c84d62.tar.xz
OMAP3 clock: only unlock SDRC DLL if SDRC clk < 83MHz
According to the 34xx TRM Rev. K section 11.2.4.4.11.1 "Purpose of the DLL/CDL Module," the SDRC delay-locked-loop can be locked at any SDRC clock frequency from 83MHz to 166MHz. CDP code unconditionally unlocked the DLL whenever shifting to a lower SDRC speed, but this seems unnecessary and error-prone, as the DLL is no longer able to compensate for process, voltage, and temperature variations. Instead, only unlock the DLL when the SDRC clock rate would be less than 83MHz. Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'arch/arm/mach-omap2/clock.c')
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