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| author | Tero Kristo <t-kristo@ti.com> | 2015-11-30 17:43:25 +0300 |
|---|---|---|
| committer | Stephen Boyd <sboyd@codeaurora.org> | 2015-11-30 22:34:17 +0300 |
| commit | 07ff73a932b725b2a4675bd0cc1a86b4933e433e (patch) | |
| tree | da9e26ac88590535060e130e8ce51c4369a7c2a8 /arch/arm/mach-omap2/clock.c | |
| parent | cf81a1cf711d71daafe8f1b8eca96b54c3f5c8ed (diff) | |
| download | linux-07ff73a932b725b2a4675bd0cc1a86b4933e433e.tar.xz | |
clk: ti: omap5+: dpll: implement errata i810
Errata i810 states that DPLL controller can get stuck while transitioning
to a power saving state, while its M/N ratio is being re-programmed.
As a workaround, before re-programming the M/N ratio, SW has to ensure
the DPLL cannot start an idle state transition. SW can disable DPLL
idling by setting the DPLL AUTO_DPLL_MODE=0 or keeping a clock request
active by setting a dependent clock domain in SW_WKUP.
This errata impacts OMAP5 and DRA7 chips, so enable the errata for these.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'arch/arm/mach-omap2/clock.c')
| -rw-r--r-- | arch/arm/mach-omap2/clock.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index acb60ed17273..d058125876d8 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -225,5 +225,9 @@ void __init ti_clk_init_features(void) if (omap_rev() == OMAP3430_REV_ES1_0) features.flags |= TI_CLK_DPLL4_DENY_REPROGRAM; + /* Errata I810 for omap5 / dra7 */ + if (soc_is_omap54xx() || soc_is_dra7xx()) + features.flags |= TI_CLK_ERRATA_I810; + ti_clk_setup_features(&features); } |