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authorPaul Walmsley <paul@pwsan.com>2012-10-30 06:56:17 +0400
committerPaul Walmsley <paul@pwsan.com>2012-11-08 23:33:08 +0400
commitb6ffa05091978c68e94d2802200f2aaa06a598d9 (patch)
tree4e2b9cc71015ba1103efe7ded485294a3aab19e7 /arch/arm/mach-omap2/clkt2xxx_apll.c
parent187e3e06e8d7050a77c3208f54edff1e1bfae31d (diff)
downloadlinux-b6ffa05091978c68e94d2802200f2aaa06a598d9.tar.xz
ARM: OMAP2xxx: APLL/CM: convert to use omap2_cm_wait_module_ready()
Convert the OMAP2xxx APLL code to use omap2_cm_wait_module_ready(), and move the low-level CM register manipulation functions to mach-omap2/cm2xxx.c. The objectives here are to remove the dependency on the deprecated omap2_cm_wait_idlest() function in mach-omap2/prcm.c, so that code can be removed later; and move low-level register accesses to the CM IP block to the CM code, which will soon be moved into drivers/. Signed-off-by: Paul Walmsley <paul@pwsan.com> Tested-by: Vaibhav Hiremath <hvaibhav@ti.com>
Diffstat (limited to 'arch/arm/mach-omap2/clkt2xxx_apll.c')
-rw-r--r--arch/arm/mach-omap2/clkt2xxx_apll.c56
1 files changed, 14 insertions, 42 deletions
diff --git a/arch/arm/mach-omap2/clkt2xxx_apll.c b/arch/arm/mach-omap2/clkt2xxx_apll.c
index e3f0c1e262a7..75561a6b04d3 100644
--- a/arch/arm/mach-omap2/clkt2xxx_apll.c
+++ b/arch/arm/mach-omap2/clkt2xxx_apll.c
@@ -37,44 +37,16 @@
#define APLLS_CLKIN_13MHZ 2
#define APLLS_CLKIN_12MHZ 3
-void __iomem *cm_idlest_pll;
-
/* Private functions */
-/* Enable an APLL if off */
-static int omap2_clk_apll_enable(struct clk *clk, u32 status_mask)
-{
- u32 cval, apll_mask;
-
- apll_mask = EN_APLL_LOCKED << clk->enable_bit;
-
- cval = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN);
-
- if ((cval & apll_mask) == apll_mask)
- return 0; /* apll already enabled */
-
- cval &= ~apll_mask;
- cval |= apll_mask;
- omap2_cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
-
- omap2_cm_wait_idlest(cm_idlest_pll, status_mask,
- OMAP24XX_CM_IDLEST_VAL, __clk_get_name(clk));
-
- /*
- * REVISIT: Should we return an error code if omap2_wait_clock_ready()
- * fails?
- */
- return 0;
-}
-
-static int omap2_clk_apll96_enable(struct clk *clk)
+static int _apll96_enable(struct clk *clk)
{
- return omap2_clk_apll_enable(clk, OMAP24XX_ST_96M_APLL_MASK);
+ return omap2xxx_cm_apll96_enable();
}
-static int omap2_clk_apll54_enable(struct clk *clk)
+static int _apll54_enable(struct clk *clk)
{
- return omap2_clk_apll_enable(clk, OMAP24XX_ST_54M_APLL_MASK);
+ return omap2xxx_cm_apll54_enable();
}
static void _apll96_allow_idle(struct clk *clk)
@@ -97,28 +69,28 @@ static void _apll54_deny_idle(struct clk *clk)
omap2xxx_cm_set_apll54_disable_autoidle();
}
-/* Stop APLL */
-static void omap2_clk_apll_disable(struct clk *clk)
+static void _apll96_disable(struct clk *clk)
{
- u32 cval;
+ omap2xxx_cm_apll96_disable();
+}
- cval = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN);
- cval &= ~(EN_APLL_LOCKED << clk->enable_bit);
- omap2_cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
+static void _apll54_disable(struct clk *clk)
+{
+ omap2xxx_cm_apll54_disable();
}
/* Public data */
const struct clkops clkops_apll96 = {
- .enable = omap2_clk_apll96_enable,
- .disable = omap2_clk_apll_disable,
+ .enable = _apll96_enable,
+ .disable = _apll96_disable,
.allow_idle = _apll96_allow_idle,
.deny_idle = _apll96_deny_idle,
};
const struct clkops clkops_apll54 = {
- .enable = omap2_clk_apll54_enable,
- .disable = omap2_clk_apll_disable,
+ .enable = _apll54_enable,
+ .disable = _apll54_disable,
.allow_idle = _apll54_allow_idle,
.deny_idle = _apll54_deny_idle,
};