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| author | James Morris <jmorris@namei.org> | 2008-08-28 04:47:34 +0400 |
|---|---|---|
| committer | James Morris <jmorris@namei.org> | 2008-08-28 04:47:34 +0400 |
| commit | 86d688984deefa3ae5a802880c11f2b408b5d6cf (patch) | |
| tree | 7ea5e8189b0a774626d3ed7c3c87df2495a4c4a0 /arch/arm/mach-ns9xxx/include/mach/regs-bbu.h | |
| parent | 93c06cbbf9fea5d5be1778febb7fa9ab1a74e5f5 (diff) | |
| parent | 4c246edd2550304df5b766cc841584b2bb058843 (diff) | |
| download | linux-86d688984deefa3ae5a802880c11f2b408b5d6cf.tar.xz | |
Merge branch 'master' into next
Diffstat (limited to 'arch/arm/mach-ns9xxx/include/mach/regs-bbu.h')
| -rw-r--r-- | arch/arm/mach-ns9xxx/include/mach/regs-bbu.h | 45 |
1 files changed, 45 insertions, 0 deletions
diff --git a/arch/arm/mach-ns9xxx/include/mach/regs-bbu.h b/arch/arm/mach-ns9xxx/include/mach/regs-bbu.h new file mode 100644 index 000000000000..af227c058fb9 --- /dev/null +++ b/arch/arm/mach-ns9xxx/include/mach/regs-bbu.h @@ -0,0 +1,45 @@ +/* + * arch/arm/mach-ns9xxx/include/mach/regs-bbu.h + * + * Copyright (C) 2006 by Digi International Inc. + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + */ +#ifndef __ASM_ARCH_REGSBBU_H +#define __ASM_ARCH_REGSBBU_H + +#include <mach/hardware.h> + +/* BBus Utility */ + +/* GPIO Configuration Registers block 1 */ +/* NOTE: the HRM starts counting at 1 for the GPIO registers, here the start is + * at 0 for each block. That is, BBU_GCONFb1(0) is GPIO Configuration Register + * #1, BBU_GCONFb2(0) is GPIO Configuration Register #8. */ +#define BBU_GCONFb1(x) __REG2(0x90600010, (x)) +#define BBU_GCONFb2(x) __REG2(0x90600100, (x)) + +#define BBU_GCONFx_DIR(m) __REGBIT(3 + (((m) & 7) << 2)) +#define BBU_GCONFx_DIR_INPUT(m) __REGVAL(BBU_GCONFx_DIR(m), 0) +#define BBU_GCONFx_DIR_OUTPUT(m) __REGVAL(BBU_GCONFx_DIR(m), 1) +#define BBU_GCONFx_INV(m) __REGBIT(2 + (((m) & 7) << 2)) +#define BBU_GCONFx_INV_NO(m) __REGVAL(BBU_GCONFx_INV(m), 0) +#define BBU_GCONFx_INV_YES(m) __REGVAL(BBU_GCONFx_INV(m), 1) +#define BBU_GCONFx_FUNC(m) __REGBITS(1 + (((m) & 7) << 2), ((m) & 7) << 2) +#define BBU_GCONFx_FUNC_0(m) __REGVAL(BBU_GCONFx_FUNC(m), 0) +#define BBU_GCONFx_FUNC_1(m) __REGVAL(BBU_GCONFx_FUNC(m), 1) +#define BBU_GCONFx_FUNC_2(m) __REGVAL(BBU_GCONFx_FUNC(m), 2) +#define BBU_GCONFx_FUNC_3(m) __REGVAL(BBU_GCONFx_FUNC(m), 3) + +#define BBU_GCTRL1 __REG(0x90600030) +#define BBU_GCTRL2 __REG(0x90600034) +#define BBU_GCTRL3 __REG(0x90600120) + +#define BBU_GSTAT1 __REG(0x90600040) +#define BBU_GSTAT2 __REG(0x90600044) +#define BBU_GSTAT3 __REG(0x90600130) + +#endif /* ifndef __ASM_ARCH_REGSBBU_H */ |