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| author | Alexandre Pereira da Silva <aletes.xgr@gmail.com> | 2012-07-20 16:01:51 +0400 |
|---|---|---|
| committer | Roland Stigge <stigge@antcom.de> | 2012-07-20 16:01:51 +0400 |
| commit | 1f37a3a32b86c443396293b1f9d3e23b0a0344e5 (patch) | |
| tree | 23260ac16c35ca382d10b56da877e91538052f2c /arch/arm/mach-lpc32xx | |
| parent | e39942f527fb02b73236d872d22c1b6b8335266c (diff) | |
| download | linux-1f37a3a32b86c443396293b1f9d3e23b0a0344e5.tar.xz | |
ARM: LPC32xx: Add PWM clock
Signed-off-by: Alexandre Pereira da Silva <aletes.xgr@gmail.com>
Signed-off-by: Roland Stigge <stigge@antcom.de>
Diffstat (limited to 'arch/arm/mach-lpc32xx')
| -rw-r--r-- | arch/arm/mach-lpc32xx/clock.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/arch/arm/mach-lpc32xx/clock.c b/arch/arm/mach-lpc32xx/clock.c index 8a4e7cb74ae1..f48c2e961b84 100644 --- a/arch/arm/mach-lpc32xx/clock.c +++ b/arch/arm/mach-lpc32xx/clock.c @@ -607,6 +607,19 @@ static struct clk clk_dma = { .get_rate = local_return_parent_rate, }; +static struct clk clk_pwm = { + .parent = &clk_pclk, + .enable = local_onoff_enable, + .enable_reg = LPC32XX_CLKPWR_PWM_CLK_CTRL, + .enable_mask = LPC32XX_CLKPWR_PWMCLK_PWM1CLK_EN | + LPC32XX_CLKPWR_PWMCLK_PWM1SEL_PCLK | + LPC32XX_CLKPWR_PWMCLK_PWM1_DIV(1) | + LPC32XX_CLKPWR_PWMCLK_PWM2CLK_EN | + LPC32XX_CLKPWR_PWMCLK_PWM2SEL_PCLK | + LPC32XX_CLKPWR_PWMCLK_PWM2_DIV(1), + .get_rate = local_return_parent_rate, +}; + static struct clk clk_uart3 = { .parent = &clk_pclk, .enable = local_onoff_enable, @@ -1188,6 +1201,7 @@ static struct clk_lookup lookups[] = { CLKDEV_INIT(NULL, "vfp9_ck", &clk_vfp9), CLKDEV_INIT("pl08xdmac", NULL, &clk_dma), CLKDEV_INIT("4003c000.watchdog", NULL, &clk_wdt), + CLKDEV_INIT("4005c000.pwm", NULL, &clk_pwm), CLKDEV_INIT(NULL, "uart3_ck", &clk_uart3), CLKDEV_INIT(NULL, "uart4_ck", &clk_uart4), CLKDEV_INIT(NULL, "uart5_ck", &clk_uart5), |