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author | Len Brown <len.brown@intel.com> | 2008-10-23 07:57:26 +0400 |
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committer | Len Brown <len.brown@intel.com> | 2008-10-23 08:11:07 +0400 |
commit | 057316cc6a5b521b332a1d7ccc871cd60c904c74 (patch) | |
tree | 4333e608da237c73ff69b10878025cca96dcb4c8 /arch/arm/mach-lh7a40x/Kconfig | |
parent | 3e2dab9a1c2deb03c311eb3f83466009147ed4d3 (diff) | |
parent | 2515ddc6db8eb49a79f0fe5e67ff09ac7c81eab4 (diff) | |
download | linux-057316cc6a5b521b332a1d7ccc871cd60c904c74.tar.xz |
Merge branch 'linus' into test
Conflicts:
MAINTAINERS
arch/x86/kernel/acpi/boot.c
arch/x86/kernel/acpi/sleep.c
drivers/acpi/Kconfig
drivers/pnp/Makefile
drivers/pnp/quirks.c
Signed-off-by: Len Brown <len.brown@intel.com>
Diffstat (limited to 'arch/arm/mach-lh7a40x/Kconfig')
-rw-r--r-- | arch/arm/mach-lh7a40x/Kconfig | 13 |
1 files changed, 6 insertions, 7 deletions
diff --git a/arch/arm/mach-lh7a40x/Kconfig b/arch/arm/mach-lh7a40x/Kconfig index 6f4c6a1798c1..9be7466e346c 100644 --- a/arch/arm/mach-lh7a40x/Kconfig +++ b/arch/arm/mach-lh7a40x/Kconfig @@ -40,23 +40,22 @@ config LPD7A40X_CPLD_SSP bool config LH7A40X_CONTIGMEM - bool "Disable NUMA Support" - depends on ARCH_LH7A40X + bool "Disable NUMA/SparseMEM Support" help Say Y here if your bootloader sets the SROMLL bit(s) in the SDRAM controller, organizing memory as a contiguous - array. This option will disable CONFIG_DISCONTIGMEM and - force the kernel to manage all memory in one node. + array. This option will disable sparse memory support + and force the kernel to manage all memory in one node. - Setting this option incorrectly may prevent the kernel from - booting. It is OK to leave it N. + Setting this option incorrectly may prevent the kernel + from booting. It is OK to leave it N. For more information, consult <file:Documentation/arm/Sharp-LH/SDRAM>. config LH7A40X_ONE_BANK_PER_NODE bool "Optimize NUMA Node Tables for Size" - depends on ARCH_LH7A40X && !LH7A40X_CONTIGMEM + depends on !LH7A40X_CONTIGMEM help Say Y here to produce compact memory node tables. By default pairs of adjacent physical RAM banks are managed |