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authorLinus Walleij <linus.walleij@linaro.org>2021-07-14 15:01:22 +0300
committerLinus Walleij <linus.walleij@linaro.org>2021-08-13 15:51:54 +0300
commitee2f116b646cb19e967d0159c212cd9f1474c7bd (patch)
treedcb976c1857fa7e242632a3e700a3754c9751e0a /arch/arm/mach-ixp4xx/nas100d-pci.c
parent06ce83a4dd42425100b5bbcd98425e7d732d3c7c (diff)
downloadlinux-ee2f116b646cb19e967d0159c212cd9f1474c7bd.tar.xz
ARM: ixp4xx: Delete NAS100D boardfiles
The NAS100D is now completely migrated to use device tree exclusively so delete the boardfiles. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'arch/arm/mach-ixp4xx/nas100d-pci.c')
-rw-r--r--arch/arm/mach-ixp4xx/nas100d-pci.c73
1 files changed, 0 insertions, 73 deletions
diff --git a/arch/arm/mach-ixp4xx/nas100d-pci.c b/arch/arm/mach-ixp4xx/nas100d-pci.c
deleted file mode 100644
index 1176f9cb4865..000000000000
--- a/arch/arm/mach-ixp4xx/nas100d-pci.c
+++ /dev/null
@@ -1,73 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * arch/arm/mach-ixp4xx/nas100d-pci.c
- *
- * NAS 100d board-level PCI initialization
- *
- * based on ixdp425-pci.c:
- * Copyright (C) 2002 Intel Corporation.
- * Copyright (C) 2003-2004 MontaVista Software, Inc.
- *
- * Maintainer: http://www.nslu2-linux.org/
- */
-
-#include <linux/pci.h>
-#include <linux/init.h>
-#include <linux/irq.h>
-#include <asm/mach/pci.h>
-#include <asm/mach-types.h>
-
-#include "irqs.h"
-
-#define MAX_DEV 3
-#define IRQ_LINES 3
-
-/* PCI controller GPIO to IRQ pin mappings */
-#define INTA 11
-#define INTB 10
-#define INTC 9
-#define INTD 8
-#define INTE 7
-
-void __init nas100d_pci_preinit(void)
-{
- irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
- irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
- irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
- irq_set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW);
- irq_set_irq_type(IXP4XX_GPIO_IRQ(INTE), IRQ_TYPE_LEVEL_LOW);
- ixp4xx_pci_preinit();
-}
-
-static int __init nas100d_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-{
- static int pci_irq_table[MAX_DEV][IRQ_LINES] = {
- { IXP4XX_GPIO_IRQ(INTA), -1, -1 },
- { IXP4XX_GPIO_IRQ(INTB), -1, -1 },
- { IXP4XX_GPIO_IRQ(INTC), IXP4XX_GPIO_IRQ(INTD),
- IXP4XX_GPIO_IRQ(INTE) },
- };
-
- if (slot >= 1 && slot <= MAX_DEV && pin >= 1 && pin <= IRQ_LINES)
- return pci_irq_table[slot - 1][pin - 1];
-
- return -1;
-}
-
-struct hw_pci __initdata nas100d_pci = {
- .nr_controllers = 1,
- .ops = &ixp4xx_ops,
- .preinit = nas100d_pci_preinit,
- .setup = ixp4xx_setup,
- .map_irq = nas100d_map_irq,
-};
-
-int __init nas100d_pci_init(void)
-{
- if (machine_is_nas100d())
- pci_common_init(&nas100d_pci);
-
- return 0;
-}
-
-subsys_initcall(nas100d_pci_init);