diff options
| author | Arnd Bergmann <arnd@arndb.de> | 2013-01-04 17:38:03 +0400 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2013-03-15 00:14:03 +0400 |
| commit | 662146b155c09d4b1fd01b5a1fb4e8464cce6685 (patch) | |
| tree | b361c8a3970ecbca99aee5f78ff53c86b2a8aedd /arch/arm/mach-gemini/gpio.c | |
| parent | f6161aa153581da4a3867a2d1a7caf4be19b6ec9 (diff) | |
| download | linux-662146b155c09d4b1fd01b5a1fb4e8464cce6685.tar.xz | |
ARM: gemini: get platform to build again
There is no defconfig file for gemini, which has lead to a lot
of bitrot. This makes the broken board files, the gpio implementation
and the reset logic work again, and fixes the build warnings
that got introduced with the changes to the readl/writel prototypes.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/mach-gemini/gpio.c')
| -rw-r--r-- | arch/arm/mach-gemini/gpio.c | 19 |
1 files changed, 10 insertions, 9 deletions
diff --git a/arch/arm/mach-gemini/gpio.c b/arch/arm/mach-gemini/gpio.c index fdc7ef1391d3..70bfa571b24b 100644 --- a/arch/arm/mach-gemini/gpio.c +++ b/arch/arm/mach-gemini/gpio.c @@ -21,6 +21,7 @@ #include <mach/hardware.h> #include <mach/irqs.h> +#include <mach/gpio.h> #define GPIO_BASE(x) IO_ADDRESS(GEMINI_GPIO_BASE(x)) @@ -44,7 +45,7 @@ #define GPIO_PORT_NUM 3 -static void _set_gpio_irqenable(unsigned int base, unsigned int index, +static void _set_gpio_irqenable(void __iomem *base, unsigned int index, int enable) { unsigned int reg; @@ -57,7 +58,7 @@ static void _set_gpio_irqenable(unsigned int base, unsigned int index, static void gpio_ack_irq(struct irq_data *d) { unsigned int gpio = irq_to_gpio(d->irq); - unsigned int base = GPIO_BASE(gpio / 32); + void __iomem *base = GPIO_BASE(gpio / 32); __raw_writel(1 << (gpio % 32), base + GPIO_INT_CLR); } @@ -65,7 +66,7 @@ static void gpio_ack_irq(struct irq_data *d) static void gpio_mask_irq(struct irq_data *d) { unsigned int gpio = irq_to_gpio(d->irq); - unsigned int base = GPIO_BASE(gpio / 32); + void __iomem *base = GPIO_BASE(gpio / 32); _set_gpio_irqenable(base, gpio % 32, 0); } @@ -73,7 +74,7 @@ static void gpio_mask_irq(struct irq_data *d) static void gpio_unmask_irq(struct irq_data *d) { unsigned int gpio = irq_to_gpio(d->irq); - unsigned int base = GPIO_BASE(gpio / 32); + void __iomem *base = GPIO_BASE(gpio / 32); _set_gpio_irqenable(base, gpio % 32, 1); } @@ -82,7 +83,7 @@ static int gpio_set_irq_type(struct irq_data *d, unsigned int type) { unsigned int gpio = irq_to_gpio(d->irq); unsigned int gpio_mask = 1 << (gpio % 32); - unsigned int base = GPIO_BASE(gpio / 32); + void __iomem *base = GPIO_BASE(gpio / 32); unsigned int reg_both, reg_level, reg_type; reg_type = __raw_readl(base + GPIO_INT_TYPE); @@ -120,7 +121,7 @@ static int gpio_set_irq_type(struct irq_data *d, unsigned int type) __raw_writel(reg_level, base + GPIO_INT_LEVEL); __raw_writel(reg_both, base + GPIO_INT_BOTH_EDGE); - gpio_ack_irq(d->irq); + gpio_ack_irq(d); return 0; } @@ -153,7 +154,7 @@ static struct irq_chip gpio_irq_chip = { static void _set_gpio_direction(struct gpio_chip *chip, unsigned offset, int dir) { - unsigned int base = GPIO_BASE(offset / 32); + void __iomem *base = GPIO_BASE(offset / 32); unsigned int reg; reg = __raw_readl(base + GPIO_DIR); @@ -166,7 +167,7 @@ static void _set_gpio_direction(struct gpio_chip *chip, unsigned offset, static void gemini_gpio_set(struct gpio_chip *chip, unsigned offset, int value) { - unsigned int base = GPIO_BASE(offset / 32); + void __iomem *base = GPIO_BASE(offset / 32); if (value) __raw_writel(1 << (offset % 32), base + GPIO_DATA_SET); @@ -176,7 +177,7 @@ static void gemini_gpio_set(struct gpio_chip *chip, unsigned offset, int value) static int gemini_gpio_get(struct gpio_chip *chip, unsigned offset) { - unsigned int base = GPIO_BASE(offset / 32); + void __iomem *base = GPIO_BASE(offset / 32); return (__raw_readl(base + GPIO_DATA_IN) >> (offset % 32)) & 1; } |