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| author | Linus Torvalds <torvalds@linux-foundation.org> | 2011-11-02 07:25:36 +0400 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2011-11-02 07:25:36 +0400 |
| commit | f906fb1d70e016726fccfb0d978c5d425503db9d (patch) | |
| tree | b2bac5fbe7d2eb81dd7fe6cc88e27dddd0189c84 /arch/arm/mach-exynos4/platsmp.c | |
| parent | 510597e26e2a072e2d46ea5bc57feaf385e37f70 (diff) | |
| parent | a7fadac10ffbfd16cc7ccf951eab1ecf85e1abdf (diff) | |
| download | linux-f906fb1d70e016726fccfb0d978c5d425503db9d.tar.xz | |
Merge branch 'next/board' of git://git.linaro.org/people/arnd/arm-soc
* 'next/board' of git://git.linaro.org/people/arnd/arm-soc: (34 commits)
ep93xx: add support Vision EP9307 SoM
ARM: mxs: Add initial support for DENX MX28
ARM: EXYNOS4: Add support SMDK4412 Board
ARM: EXYNOS4: Add MCT support for EXYNOS4412
ARM: EXYNOS4: Add functions for gic interrupt handling
ARM: EXYNOS4: Add support clock for EXYNOS4412
ARM: EXYNOS4: Add support new EXYNOS4412 SoC
ARM: EXYNOS4: Add support MCT PPI for EXYNOS4212
ARM: EXYNOS4: Add support PPI in external GIC
ARM: EXYNOS4: convert boot_params to atag_offset
ixp4xx: support omicron ixp425 based boards
ARM: EXYNOS4: Add support SMDK4212 Board
ARM: EXYNOS4: Add support PM for EXYNOS4212
ARM: EXYNOS4: Add support clock for EXYNOS4212
ARM: EXYNOS4: Add support new EXYNOS4212 SoC
at91: USB-A9G20 C01 & C11 board support
at91: merge board USB-A9260 and USB-A9263 together
at91: add support for RSIs EWS board
ARM: SAMSUNG: Fix mask value for S5P64X0 CPU IDs
ARM: SAMSUNG: Fix mask for S3C64xx CPU IDs
...
Diffstat (limited to 'arch/arm/mach-exynos4/platsmp.c')
| -rw-r--r-- | arch/arm/mach-exynos4/platsmp.c | 13 |
1 files changed, 9 insertions, 4 deletions
diff --git a/arch/arm/mach-exynos4/platsmp.c b/arch/arm/mach-exynos4/platsmp.c index 0c90896ad9a0..782dcf11d234 100644 --- a/arch/arm/mach-exynos4/platsmp.c +++ b/arch/arm/mach-exynos4/platsmp.c @@ -30,9 +30,13 @@ #include <mach/regs-clock.h> #include <mach/regs-pmu.h> +#include <plat/cpu.h> + +extern unsigned int gic_bank_offset; extern void exynos4_secondary_startup(void); -#define CPU1_BOOT_REG S5P_VA_SYSRAM +#define CPU1_BOOT_REG (samsung_rev() == EXYNOS4210_REV_1_1 ? \ + S5P_INFORM5 : S5P_VA_SYSRAM) /* * control for which core is the next to come out of the secondary @@ -64,9 +68,9 @@ static DEFINE_SPINLOCK(boot_lock); static void __cpuinit exynos4_gic_secondary_init(void) { void __iomem *dist_base = S5P_VA_GIC_DIST + - (EXYNOS4_GIC_BANK_OFFSET * smp_processor_id()); + (gic_bank_offset * smp_processor_id()); void __iomem *cpu_base = S5P_VA_GIC_CPU + - (EXYNOS4_GIC_BANK_OFFSET * smp_processor_id()); + (gic_bank_offset * smp_processor_id()); int i; /* @@ -216,5 +220,6 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus) * until it receives a soft interrupt, and then the * secondary CPU branches to this address. */ - __raw_writel(BSYM(virt_to_phys(exynos4_secondary_startup)), S5P_VA_SYSRAM); + __raw_writel(BSYM(virt_to_phys(exynos4_secondary_startup)), + CPU1_BOOT_REG); } |