diff options
| author | Sylwester Nawrocki <s.nawrocki@samsung.com> | 2011-03-10 15:53:40 +0300 |
|---|---|---|
| committer | Kukjin Kim <kgene.kim@samsung.com> | 2011-03-11 09:49:01 +0300 |
| commit | 1d45ac49daa15fd0a64c58744ac9ea6451e607e6 (patch) | |
| tree | 8db8bb0dd987dfd3c4a166893040de29ba9482e9 /arch/arm/mach-exynos4/include | |
| parent | e24d208de6bc779c6bd97523cde2665a33f2be4d (diff) | |
| download | linux-1d45ac49daa15fd0a64c58744ac9ea6451e607e6.tar.xz | |
ARM: S5P: Add support for common MIPI CSIS/DSIM D-PHY control
Add common code for MIPI-CSIS and MIPI-DSIM drivers to support
their corresponding D-PHY's enable and reset control.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/mach-exynos4/include')
| -rw-r--r-- | arch/arm/mach-exynos4/include/mach/regs-clock.h | 4 | ||||
| -rw-r--r-- | arch/arm/mach-exynos4/include/mach/regs-pmu.h | 5 |
2 files changed, 8 insertions, 1 deletions
diff --git a/arch/arm/mach-exynos4/include/mach/regs-clock.h b/arch/arm/mach-exynos4/include/mach/regs-clock.h index ba8f91c04e19..38dee94fc7ae 100644 --- a/arch/arm/mach-exynos4/include/mach/regs-clock.h +++ b/arch/arm/mach-exynos4/include/mach/regs-clock.h @@ -160,7 +160,9 @@ #define S5P_CLKDIV_BUS_GPLR_SHIFT (4) #define S5P_CLKDIV_BUS_GPLR_MASK (0x7 << S5P_CLKDIV_BUS_GPLR_SHIFT) -/* Compatibility defines */ +/* Compatibility defines and inclusion */ + +#include <mach/regs-pmu.h> #define S5P_EPLL_CON S5P_EPLL_CON0 diff --git a/arch/arm/mach-exynos4/include/mach/regs-pmu.h b/arch/arm/mach-exynos4/include/mach/regs-pmu.h index 2ddd6175dfa0..985416d1085f 100644 --- a/arch/arm/mach-exynos4/include/mach/regs-pmu.h +++ b/arch/arm/mach-exynos4/include/mach/regs-pmu.h @@ -17,6 +17,11 @@ #define S5P_PMUREG(x) (S5P_VA_PMU + (x)) +#define S5P_MIPI_DPHY_CONTROL(n) S5P_PMUREG(0x0710 + (n) * 4) +#define S5P_MIPI_DPHY_ENABLE (1 << 0) +#define S5P_MIPI_DPHY_SRESETN (1 << 1) +#define S5P_MIPI_DPHY_MRESETN (1 << 2) + #define S5P_PMU_CAM_CONF S5P_PMUREG(0x3C00) #define S5P_PMU_TV_CONF S5P_PMUREG(0x3C20) #define S5P_PMU_MFC_CONF S5P_PMUREG(0x3C40) |