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| author | Kukjin Kim <kgene.kim@samsung.com> | 2013-12-18 23:19:59 +0400 |
|---|---|---|
| committer | Kukjin Kim <kgene.kim@samsung.com> | 2013-12-19 00:21:17 +0400 |
| commit | 9c9239afe31f67d137ba6c45b244b509c2090567 (patch) | |
| tree | e832d8ff75bf0f74f0a073f84c37158943b05463 /arch/arm/mach-exynos/pm.c | |
| parent | 7d8f159188410557630a7270efe3e14a1a305c2e (diff) | |
| download | linux-9c9239afe31f67d137ba6c45b244b509c2090567.tar.xz | |
ARM: EXYNOS: local definitions for pm.c into mach-exynos dir
Some of definitions in the regs-clock.h are used only for pm.c,
so this moves them into the file.
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/mach-exynos/pm.c')
| -rw-r--r-- | arch/arm/mach-exynos/pm.c | 26 |
1 files changed, 25 insertions, 1 deletions
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c index 11c37c4f04fb..e00025bbbe89 100644 --- a/arch/arm/mach-exynos/pm.c +++ b/arch/arm/mach-exynos/pm.c @@ -29,12 +29,36 @@ #include <plat/pll.h> #include <plat/regs-srom.h> -#include <mach/regs-clock.h> +#include <mach/map.h> #include <mach/pm-core.h> #include "common.h" #include "regs-pmu.h" +#define EXYNOS4_EPLL_LOCK (S5P_VA_CMU + 0x0C010) +#define EXYNOS4_VPLL_LOCK (S5P_VA_CMU + 0x0C020) + +#define EXYNOS4_EPLL_CON0 (S5P_VA_CMU + 0x0C110) +#define EXYNOS4_EPLL_CON1 (S5P_VA_CMU + 0x0C114) +#define EXYNOS4_VPLL_CON0 (S5P_VA_CMU + 0x0C120) +#define EXYNOS4_VPLL_CON1 (S5P_VA_CMU + 0x0C124) + +#define EXYNOS4_CLKSRC_MASK_TOP (S5P_VA_CMU + 0x0C310) +#define EXYNOS4_CLKSRC_MASK_CAM (S5P_VA_CMU + 0x0C320) +#define EXYNOS4_CLKSRC_MASK_TV (S5P_VA_CMU + 0x0C324) +#define EXYNOS4_CLKSRC_MASK_LCD0 (S5P_VA_CMU + 0x0C334) +#define EXYNOS4_CLKSRC_MASK_MAUDIO (S5P_VA_CMU + 0x0C33C) +#define EXYNOS4_CLKSRC_MASK_FSYS (S5P_VA_CMU + 0x0C340) +#define EXYNOS4_CLKSRC_MASK_PERIL0 (S5P_VA_CMU + 0x0C350) +#define EXYNOS4_CLKSRC_MASK_PERIL1 (S5P_VA_CMU + 0x0C354) + +#define EXYNOS4_CLKSRC_MASK_DMC (S5P_VA_CMU + 0x10300) + +#define EXYNOS4_EPLLCON0_LOCKED_SHIFT (29) +#define EXYNOS4_VPLLCON0_LOCKED_SHIFT (29) + +#define EXYNOS4210_CLKSRC_MASK_LCD1 (S5P_VA_CMU + 0x0C338) + static const struct sleep_save exynos4_set_clksrc[] = { { .reg = EXYNOS4_CLKSRC_MASK_TOP , .val = 0x00000001, }, { .reg = EXYNOS4_CLKSRC_MASK_CAM , .val = 0x11111111, }, |