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authorArnd Bergmann <arnd@arndb.de>2012-01-09 21:06:36 +0400
committerArnd Bergmann <arnd@arndb.de>2012-01-09 21:06:36 +0400
commit421b759b86eb8a914cbbd11f6d09a74f411762c6 (patch)
tree505ca7f23987d8eaaa519a7e8506b854e2c0d030 /arch/arm/mach-exynos/pm.c
parente067096c8d57d191f29d734cd5692695c95cc36e (diff)
parenta07613a54d700a974f3a4a657da78ef5d097315d (diff)
downloadlinux-421b759b86eb8a914cbbd11f6d09a74f411762c6.tar.xz
Merge branch 'samsung/cleanup' into next/boards
Conflicts: arch/arm/mach-imx/mach-imx6q.c arch/arm/mach-omap2/board-ti8168evm.c arch/arm/mach-s3c64xx/Kconfig arch/arm/mach-tegra/Makefile arch/arm/mach-tegra/board-dt-tegra20.c arch/arm/mach-tegra/common.c Lots of relatively simple conflicts between the board changes and stuff from the arm tree. This pulls in the resolution from the samsung/cleanup tree, so we don't get conflicting merges. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/mach-exynos/pm.c')
-rw-r--r--arch/arm/mach-exynos/pm.c24
1 files changed, 2 insertions, 22 deletions
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index 509a435afd4b..4093fea849c3 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -23,6 +23,7 @@
#include <asm/cacheflush.h>
#include <asm/hardware/cache-l2x0.h>
+#include <asm/smp_scu.h>
#include <plat/cpu.h>
#include <plat/pm.h>
@@ -213,27 +214,6 @@ static int exynos4_pm_add(struct sys_device *sysdev)
return 0;
}
-/* This function copy from linux/arch/arm/kernel/smp_scu.c */
-
-void exynos4_scu_enable(void __iomem *scu_base)
-{
- u32 scu_ctrl;
-
- scu_ctrl = __raw_readl(scu_base);
- /* already enabled? */
- if (scu_ctrl & 1)
- return;
-
- scu_ctrl |= 1;
- __raw_writel(scu_ctrl, scu_base);
-
- /*
- * Ensure that the data accessed by CPU0 before the SCU was
- * initialised is visible to the other CPUs.
- */
- flush_cache_all();
-}
-
static unsigned long pll_base_rate;
static void exynos4_restore_pll(void)
@@ -402,7 +382,7 @@ static void exynos4_pm_resume(void)
exynos4_restore_pll();
- exynos4_scu_enable(S5P_VA_SCU);
+ scu_enable(S5P_VA_SCU);
#ifdef CONFIG_CACHE_L2X0
s3c_pm_do_restore_core(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save));