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authorLinus Torvalds <torvalds@linux-foundation.org>2013-07-03 00:43:38 +0400
committerLinus Torvalds <torvalds@linux-foundation.org>2013-07-03 00:43:38 +0400
commit3883cbb6c1bda013a3ce2dbdab7dc97c52e4a232 (patch)
tree5b69f83b049d24ac81123ac954ca8c9128e48443 /arch/arm/mach-exynos/include/mach/regs-usb-phy.h
parentd2033f2c1d1de2239ded15e478ddb4028f192a15 (diff)
parent1eb92b24e243085d242cf5ffd64829bba70972e1 (diff)
downloadlinux-3883cbb6c1bda013a3ce2dbdab7dc97c52e4a232.tar.xz
Merge tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC specific changes from Arnd Bergmann: "These changes are all to SoC-specific code, a total of 33 branches on 17 platforms were pulled into this. Like last time, Renesas sh-mobile is now the platform with the most changes, followed by OMAP and EXYNOS. Two new platforms, TI Keystone and Rockchips RK3xxx are added in this branch, both containing almost no platform specific code at all, since they are using generic subsystem interfaces for clocks, pinctrl, interrupts etc. The device drivers are getting merged through the respective subsystem maintainer trees. One more SoC (u300) is now multiplatform capable and several others (shmobile, exynos, msm, integrator, kirkwood, clps711x) are moving towards that goal with this series but need more work. Also noteworthy is the work on PCI here, which is traditionally part of the SoC specific code. With the changes done by Thomas Petazzoni, we can now more easily have PCI host controller drivers as loadable modules and keep them separate from the platform code in drivers/pci/host. This has already led to the discovery that three platforms (exynos, spear and imx) are actually using an identical PCIe host controller and will be able to share a driver once support for spear and imx is added." * tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (480 commits) ARM: integrator: let pciv3 use mem/premem from device tree ARM: integrator: set local side PCI addresses right ARM: dts: Add pcie controller node for exynos5440-ssdk5440 ARM: dts: Add pcie controller node for Samsung EXYNOS5440 SoC ARM: EXYNOS: Enable PCIe support for Exynos5440 pci: Add PCIe driver for Samsung Exynos ARM: OMAP5: voltagedomain data: remove temporary OMAP4 voltage data ARM: keystone: Move CPU bringup code to dedicated asm file ARM: multiplatform: always pick one CPU type ARM: imx: select syscon for IMX6SL ARM: keystone: select ARM_ERRATA_798181 only for SMP ARM: imx: Synertronixx scb9328 needs to select SOC_IMX1 ARM: OMAP2+: AM43x: resolve SMP related build error dmaengine: edma: enable build for AM33XX ARM: edma: Add EDMA crossbar event mux support ARM: edma: Add DT and runtime PM support to the private EDMA API dmaengine: edma: Add TI EDMA device tree binding arm: add basic support for Rockchip RK3066a boards arm: add debug uarts for rockchip rk29xx and rk3xxx series arm: Add basic clocks for Rockchip rk3066a SoCs ...
Diffstat (limited to 'arch/arm/mach-exynos/include/mach/regs-usb-phy.h')
-rw-r--r--arch/arm/mach-exynos/include/mach/regs-usb-phy.h74
1 files changed, 0 insertions, 74 deletions
diff --git a/arch/arm/mach-exynos/include/mach/regs-usb-phy.h b/arch/arm/mach-exynos/include/mach/regs-usb-phy.h
deleted file mode 100644
index 07277735252e..000000000000
--- a/arch/arm/mach-exynos/include/mach/regs-usb-phy.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * Copyright (C) 2011 Samsung Electronics Co.Ltd
- * Author: Joonyoung Shim <jy0922.shim@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-
-#ifndef __PLAT_S5P_REGS_USB_PHY_H
-#define __PLAT_S5P_REGS_USB_PHY_H
-
-#define EXYNOS4_HSOTG_PHYREG(x) ((x) + S3C_VA_USB_HSPHY)
-
-#define EXYNOS4_PHYPWR EXYNOS4_HSOTG_PHYREG(0x00)
-#define PHY1_HSIC_NORMAL_MASK (0xf << 9)
-#define PHY1_HSIC1_SLEEP (1 << 12)
-#define PHY1_HSIC1_FORCE_SUSPEND (1 << 11)
-#define PHY1_HSIC0_SLEEP (1 << 10)
-#define PHY1_HSIC0_FORCE_SUSPEND (1 << 9)
-
-#define PHY1_STD_NORMAL_MASK (0x7 << 6)
-#define PHY1_STD_SLEEP (1 << 8)
-#define PHY1_STD_ANALOG_POWERDOWN (1 << 7)
-#define PHY1_STD_FORCE_SUSPEND (1 << 6)
-
-#define PHY0_NORMAL_MASK (0x39 << 0)
-#define PHY0_SLEEP (1 << 5)
-#define PHY0_OTG_DISABLE (1 << 4)
-#define PHY0_ANALOG_POWERDOWN (1 << 3)
-#define PHY0_FORCE_SUSPEND (1 << 0)
-
-#define EXYNOS4_PHYCLK EXYNOS4_HSOTG_PHYREG(0x04)
-#define PHY1_COMMON_ON_N (1 << 7)
-#define PHY0_COMMON_ON_N (1 << 4)
-#define PHY0_ID_PULLUP (1 << 2)
-
-#define EXYNOS4_CLKSEL_SHIFT (0)
-
-#define EXYNOS4210_CLKSEL_MASK (0x3 << 0)
-#define EXYNOS4210_CLKSEL_48M (0x0 << 0)
-#define EXYNOS4210_CLKSEL_12M (0x2 << 0)
-#define EXYNOS4210_CLKSEL_24M (0x3 << 0)
-
-#define EXYNOS4X12_CLKSEL_MASK (0x7 << 0)
-#define EXYNOS4X12_CLKSEL_9600K (0x0 << 0)
-#define EXYNOS4X12_CLKSEL_10M (0x1 << 0)
-#define EXYNOS4X12_CLKSEL_12M (0x2 << 0)
-#define EXYNOS4X12_CLKSEL_19200K (0x3 << 0)
-#define EXYNOS4X12_CLKSEL_20M (0x4 << 0)
-#define EXYNOS4X12_CLKSEL_24M (0x5 << 0)
-
-#define EXYNOS4_RSTCON EXYNOS4_HSOTG_PHYREG(0x08)
-#define HOST_LINK_PORT_SWRST_MASK (0xf << 6)
-#define HOST_LINK_PORT2_SWRST (1 << 9)
-#define HOST_LINK_PORT1_SWRST (1 << 8)
-#define HOST_LINK_PORT0_SWRST (1 << 7)
-#define HOST_LINK_ALL_SWRST (1 << 6)
-
-#define PHY1_SWRST_MASK (0x7 << 3)
-#define PHY1_HSIC_SWRST (1 << 5)
-#define PHY1_STD_SWRST (1 << 4)
-#define PHY1_ALL_SWRST (1 << 3)
-
-#define PHY0_SWRST_MASK (0x7 << 0)
-#define PHY0_PHYLINK_SWRST (1 << 2)
-#define PHY0_HLINK_SWRST (1 << 1)
-#define PHY0_SWRST (1 << 0)
-
-#define EXYNOS4_PHY1CON EXYNOS4_HSOTG_PHYREG(0x34)
-#define FPENABLEN (1 << 0)
-
-#endif /* __PLAT_S5P_REGS_USB_PHY_H */