diff options
| author | Cyril Chemparathy <cyril@ti.com> | 2010-05-08 01:06:35 +0400 |
|---|---|---|
| committer | Kevin Hilman <khilman@deeprootsystems.com> | 2010-05-13 21:05:26 +0400 |
| commit | 1bcd38ad2de4c1cd30387c588dfb28d637d4111d (patch) | |
| tree | c8702d5bf18d3956a8a661d8aef62b79dff34cb8 /arch/arm/mach-davinci/time.c | |
| parent | 3347db8392486a1b52aab980cc445cf505c36d45 (diff) | |
| download | linux-1bcd38ad2de4c1cd30387c588dfb28d637d4111d.tar.xz | |
Davinci: timer - use ioremap()
This patch eliminates IO_ADDRESS() usage for Davinci timer definitions. The
timer code has correspondingly been modified to ioremap() MMRs instead.
Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Diffstat (limited to 'arch/arm/mach-davinci/time.c')
| -rw-r--r-- | arch/arm/mach-davinci/time.c | 22 |
1 files changed, 14 insertions, 8 deletions
diff --git a/arch/arm/mach-davinci/time.c b/arch/arm/mach-davinci/time.c index e5c598a387be..0f21c36e65dd 100644 --- a/arch/arm/mach-davinci/time.c +++ b/arch/arm/mach-davinci/time.c @@ -197,32 +197,36 @@ static void __init timer_init(void) { struct davinci_soc_info *soc_info = &davinci_soc_info; struct davinci_timer_instance *dtip = soc_info->timer_info->timers; + void __iomem *base[2]; int i; /* Global init of each 64-bit timer as a whole */ for(i=0; i<2; i++) { u32 tgcr; - void __iomem *base = dtip[i].base; + + base[i] = ioremap(dtip[i].base, SZ_4K); + if (WARN_ON(!base[i])) + continue; /* Disabled, Internal clock source */ - __raw_writel(0, base + TCR); + __raw_writel(0, base[i] + TCR); /* reset both timers, no pre-scaler for timer34 */ tgcr = 0; - __raw_writel(tgcr, base + TGCR); + __raw_writel(tgcr, base[i] + TGCR); /* Set both timers to unchained 32-bit */ tgcr = TGCR_TIMMODE_32BIT_UNCHAINED << TGCR_TIMMODE_SHIFT; - __raw_writel(tgcr, base + TGCR); + __raw_writel(tgcr, base[i] + TGCR); /* Unreset timers */ tgcr |= (TGCR_UNRESET << TGCR_TIM12RS_SHIFT) | (TGCR_UNRESET << TGCR_TIM34RS_SHIFT); - __raw_writel(tgcr, base + TGCR); + __raw_writel(tgcr, base[i] + TGCR); /* Init both counters to zero */ - __raw_writel(0, base + TIM12); - __raw_writel(0, base + TIM34); + __raw_writel(0, base[i] + TIM12); + __raw_writel(0, base[i] + TIM34); } /* Init of each timer as a 32-bit timer */ @@ -231,7 +235,9 @@ static void __init timer_init(void) int timer = ID_TO_TIMER(t->id); u32 irq; - t->base = dtip[timer].base; + t->base = base[timer]; + if (!t->base) + continue; if (IS_TIMER_BOT(t->id)) { t->enamode_shift = 6; |