diff options
| author | Alexander Shiyan <shc_work@mail.ru> | 2014-02-15 12:05:31 +0400 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2014-02-28 20:44:30 +0400 |
| commit | 32c6c01b0e58c38c4f4256091633f6b342987e28 (patch) | |
| tree | 5c4e2e1c10673c3a88ce1a25d8ff3910da7602ed /arch/arm/mach-clps711x/include | |
| parent | ead47a75cf5b92145294a4cc9671a31b34116589 (diff) | |
| download | linux-32c6c01b0e58c38c4f4256091633f6b342987e28.tar.xz | |
ARM: clps711x: Remove EP72XX_ROM_BOOT option
CLPS711X CPUs have 128 bytes of on-chip Boot ROM with an
instruction sequence that configure UART1 to receive up to
2 Kbytes of serial data which is then placed in the on-chip
SRAM. Once the download is complete, the program counter
jumps to SRAM to begin executed the downloaded data.
The purpose of this mode is to allow the downloaded code to
facilitate programming of FLASH or other ROM device. Selection
of the internal Boot ROM is accomplished at power-on-reset time.
No reason to keep this special (develop only) mode in the kernel.
This patch removes EP72XX_ROM_BOOT kernel symbol.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/mach-clps711x/include')
| -rw-r--r-- | arch/arm/mach-clps711x/include/mach/hardware.h | 17 |
1 files changed, 0 insertions, 17 deletions
diff --git a/arch/arm/mach-clps711x/include/mach/hardware.h b/arch/arm/mach-clps711x/include/mach/hardware.h index c5a8ea6839ef..5d6afda1c0e8 100644 --- a/arch/arm/mach-clps711x/include/mach/hardware.h +++ b/arch/arm/mach-clps711x/include/mach/hardware.h @@ -38,13 +38,6 @@ #define clps_writel(val,off) writel(val, CLPS711X_VIRT_BASE + (off)) #endif -/* - * The physical addresses that the external chip select signals map to is - * dependent on the setting of the nMEDCHG signal on EP7211 and EP7212 - * processors. CONFIG_EP72XX_BOOT_ROM is only available if these - * processors are in use. - */ -#ifndef CONFIG_EP72XX_ROM_BOOT #define CS0_PHYS_BASE (0x00000000) #define CS1_PHYS_BASE (0x10000000) #define CS2_PHYS_BASE (0x20000000) @@ -53,16 +46,6 @@ #define CS5_PHYS_BASE (0x50000000) #define CS6_PHYS_BASE (0x60000000) #define CS7_PHYS_BASE (0x70000000) -#else -#define CS0_PHYS_BASE (0x70000000) -#define CS1_PHYS_BASE (0x60000000) -#define CS2_PHYS_BASE (0x50000000) -#define CS3_PHYS_BASE (0x40000000) -#define CS4_PHYS_BASE (0x30000000) -#define CS5_PHYS_BASE (0x20000000) -#define CS6_PHYS_BASE (0x10000000) -#define CS7_PHYS_BASE (0x00000000) -#endif #define CLPS711X_SRAM_BASE CS6_PHYS_BASE #define CLPS711X_SRAM_SIZE (48 * 1024) |