diff options
author | Leo Chen <leochen@broadcom.com> | 2009-08-07 22:58:26 +0400 |
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committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2009-08-15 19:01:38 +0400 |
commit | 278a6752e869b0f4a03ce5ac0588b31b50712903 (patch) | |
tree | 622a4e4eae66aceb836cf3cb04056ef21b636da2 /arch/arm/mach-bcmring/clock.h | |
parent | 4663712cc745324a216112a72c744bb2b8f6658b (diff) | |
download | linux-278a6752e869b0f4a03ce5ac0588b31b50712903.tar.xz |
ARM: 5644/1: add bcmring core.c, clock.c, clock.h
add core.c, clock.c, and clock.h in mach-bcmring
implement timer init, clocksource init, amba device init
implement clock set/get enable/disable API
add dummy clkdev.h
Signed-off-by: Leo Chen <leochen@broadcom.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-bcmring/clock.h')
-rw-r--r-- | arch/arm/mach-bcmring/clock.h | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/arch/arm/mach-bcmring/clock.h b/arch/arm/mach-bcmring/clock.h new file mode 100644 index 000000000000..5e0b98138973 --- /dev/null +++ b/arch/arm/mach-bcmring/clock.h @@ -0,0 +1,33 @@ +/***************************************************************************** +* Copyright 2001 - 2009 Broadcom Corporation. All rights reserved. +* +* Unless you and Broadcom execute a separate written software license +* agreement governing use of this software, this software is licensed to you +* under the terms of the GNU General Public License version 2, available at +* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). +* +* Notwithstanding the above, under no circumstances may you combine this +* software in any way with any other Broadcom software provided under a +* license other than the GPL, without Broadcom's express prior written +* consent. +*****************************************************************************/ +#include <mach/csp/chipcHw_def.h> + +#define CLK_TYPE_PRIMARY 1 /* primary clock must NOT have a parent */ +#define CLK_TYPE_PLL1 2 /* PPL1 */ +#define CLK_TYPE_PLL2 4 /* PPL2 */ +#define CLK_TYPE_PROGRAMMABLE 8 /* programmable clock rate */ +#define CLK_TYPE_BYPASSABLE 16 /* parent can be changed */ + +#define CLK_MODE_XTAL 1 /* clock source is from crystal */ + +struct clk { + const char *name; /* clock name */ + unsigned int type; /* clock type */ + unsigned int mode; /* current mode */ + volatile int use_bypass; /* indicate if it's in bypass mode */ + chipcHw_CLOCK_e csp_id; /* clock ID for CSP CHIPC */ + unsigned long rate_hz; /* clock rate in Hz */ + unsigned int use_cnt; /* usage count */ + struct clk *parent; /* parent clock */ +}; |