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| author | Brian Norris <computersforpeace@gmail.com> | 2014-09-06 03:31:04 +0400 |
|---|---|---|
| committer | Florian Fainelli <f.fainelli@gmail.com> | 2014-10-20 23:44:40 +0400 |
| commit | 62639c2f5332a0f25b11806ddcfe1d95d3d635fb (patch) | |
| tree | 20373f40cdfaab704facd0767c17df1746b026bf /arch/arm/mach-bcm/headsmp-brcmstb.S | |
| parent | 81b43a6e2d072126df5eb016524819f6921262f3 (diff) | |
| download | linux-62639c2f5332a0f25b11806ddcfe1d95d3d635fb.tar.xz | |
ARM: brcmstb: reintroduce SMP support
Support for SMP bringup of the B15 CPUs on Broadcom STB chips was added
in commit 4fbe66d9903425156c193ae44c81c0f7557755c4 but was reverted in
commit fc3e825fa91636a5d1b992e769b2d8279877bfad to address some late
review comments. This reintroduces SMP support.
Signed-off-by: Marc Carino <marc.ceeeee@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Diffstat (limited to 'arch/arm/mach-bcm/headsmp-brcmstb.S')
| -rw-r--r-- | arch/arm/mach-bcm/headsmp-brcmstb.S | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/arch/arm/mach-bcm/headsmp-brcmstb.S b/arch/arm/mach-bcm/headsmp-brcmstb.S new file mode 100644 index 000000000000..199c1ea58248 --- /dev/null +++ b/arch/arm/mach-bcm/headsmp-brcmstb.S @@ -0,0 +1,33 @@ +/* + * SMP boot code for secondary CPUs + * Based on arch/arm/mach-tegra/headsmp.S + * + * Copyright (C) 2010 NVIDIA, Inc. + * Copyright (C) 2013-2014 Broadcom Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <asm/assembler.h> +#include <linux/linkage.h> +#include <linux/init.h> + + .section ".text.head", "ax" + +ENTRY(brcmstb_secondary_startup) + /* + * Ensure CPU is in a sane state by disabling all IRQs and switching + * into SVC mode. + */ + setmode PSR_I_BIT | PSR_F_BIT | SVC_MODE, r0 + + bl v7_invalidate_l1 + b secondary_startup +ENDPROC(brcmstb_secondary_startup) |