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author | J. Bruce Fields <bfields@citi.umich.edu> | 2009-06-16 05:08:07 +0400 |
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committer | J. Bruce Fields <bfields@citi.umich.edu> | 2009-06-16 05:08:07 +0400 |
commit | 7eef4091a653c243a87e5375c54504cc03bec4d8 (patch) | |
tree | f65b77f830b2c8f7d014512badfef5df0d591ee9 /arch/arm/include/asm/cache.h | |
parent | 0a93a47f042c459f0f46942c3a920e3c81878031 (diff) | |
parent | 07a2039b8eb0af4ff464efd3dfd95de5c02648c6 (diff) | |
download | linux-7eef4091a653c243a87e5375c54504cc03bec4d8.tar.xz |
Merge commit 'v2.6.30' into for-2.6.31
Diffstat (limited to 'arch/arm/include/asm/cache.h')
-rw-r--r-- | arch/arm/include/asm/cache.h | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h index cb7a9e97fd7e..feaa75f0013e 100644 --- a/arch/arm/include/asm/cache.h +++ b/arch/arm/include/asm/cache.h @@ -7,4 +7,20 @@ #define L1_CACHE_SHIFT 5 #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) +/* + * Memory returned by kmalloc() may be used for DMA, so we must make + * sure that all such allocations are cache aligned. Otherwise, + * unrelated code may cause parts of the buffer to be read into the + * cache before the transfer is done, causing old data to be seen by + * the CPU. + */ +#define ARCH_KMALLOC_MINALIGN L1_CACHE_BYTES + +/* + * With EABI on ARMv5 and above we must have 64-bit aligned slab pointers. + */ +#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) +#define ARCH_SLAB_MINALIGN 8 +#endif + #endif |