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authorKishon Vijay Abraham I <kishon@ti.com>2017-12-19 12:31:32 +0300
committerTony Lindgren <tony@atomide.com>2017-12-21 18:12:41 +0300
commit423aa8ba0541d8924a047755b01a1bb45fa09b03 (patch)
treeffda3ab0df5911b18255fdd2c3bda93c2ead1bab /arch/arm/configs
parent4fbd8d194f06c8a3fd2af1ce560ddb31f7ec8323 (diff)
downloadlinux-423aa8ba0541d8924a047755b01a1bb45fa09b03.tar.xz
ARM: omap2plus_defconfig: Enable CONFIG_PCI_DRA7XX (Host & Device modes)
Enable CONFIG_PCI_DRA7XX in order to be able to configure PCIe controller present in dra7 SoCs in both host mode and device mode. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/configs')
-rw-r--r--arch/arm/configs/omap2plus_defconfig8
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig
index 7b97200c1d64..a01871d5aa73 100644
--- a/arch/arm/configs/omap2plus_defconfig
+++ b/arch/arm/configs/omap2plus_defconfig
@@ -48,6 +48,13 @@ CONFIG_SOC_AM43XX=y
CONFIG_SOC_DRA7XX=y
CONFIG_ARM_THUMBEE=y
CONFIG_ARM_ERRATA_411920=y
+CONFIG_PCI=y
+CONFIG_PCI_MSI=y
+CONFIG_PCI_DRA7XX=y
+CONFIG_PCI_DRA7XX_EP=y
+CONFIG_PCI_ENDPOINT=y
+CONFIG_PCI_ENDPOINT_CONFIGFS=y
+CONFIG_PCI_EPF_TEST=m
CONFIG_SMP=y
CONFIG_NR_CPUS=2
CONFIG_CMA=y
@@ -137,6 +144,7 @@ CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=16384
CONFIG_SENSORS_TSL2550=m
CONFIG_SRAM=y
+CONFIG_PCI_ENDPOINT_TEST=m
CONFIG_EEPROM_AT24=m
CONFIG_BLK_DEV_SD=y
CONFIG_SCSI_SCAN_ASYNC=y