diff options
| author | Linus Torvalds <torvalds@linux-foundation.org> | 2014-06-08 22:31:16 +0400 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2014-06-08 22:31:16 +0400 |
| commit | 3f17ea6dea8ba5668873afa54628a91aaa3fb1c0 (patch) | |
| tree | afbeb2accd4c2199ddd705ae943995b143a0af02 /arch/arm/boot | |
| parent | 1860e379875dfe7271c649058aeddffe5afd9d0d (diff) | |
| parent | 1a5700bc2d10cd379a795fd2bb377a190af5acd4 (diff) | |
| download | linux-3f17ea6dea8ba5668873afa54628a91aaa3fb1c0.tar.xz | |
Merge branch 'next' (accumulated 3.16 merge window patches) into master
Now that 3.15 is released, this merges the 'next' branch into 'master',
bringing us to the normal situation where my 'master' branch is the
merge window.
* accumulated work in next: (6809 commits)
ufs: sb mutex merge + mutex_destroy
powerpc: update comments for generic idle conversion
cris: update comments for generic idle conversion
idle: remove cpu_idle() forward declarations
nbd: zero from and len fields in NBD_CMD_DISCONNECT.
mm: convert some level-less printks to pr_*
MAINTAINERS: adi-buildroot-devel is moderated
MAINTAINERS: add linux-api for review of API/ABI changes
mm/kmemleak-test.c: use pr_fmt for logging
fs/dlm/debug_fs.c: replace seq_printf by seq_puts
fs/dlm/lockspace.c: convert simple_str to kstr
fs/dlm/config.c: convert simple_str to kstr
mm: mark remap_file_pages() syscall as deprecated
mm: memcontrol: remove unnecessary memcg argument from soft limit functions
mm: memcontrol: clean up memcg zoneinfo lookup
mm/memblock.c: call kmemleak directly from memblock_(alloc|free)
mm/mempool.c: update the kmemleak stack trace for mempool allocations
lib/radix-tree.c: update the kmemleak stack trace for radix tree allocations
mm: introduce kmemleak_update_trace()
mm/kmemleak.c: use %u to print ->checksum
...
Diffstat (limited to 'arch/arm/boot')
372 files changed, 26759 insertions, 2396 deletions
diff --git a/arch/arm/boot/compressed/atags_to_fdt.c b/arch/arm/boot/compressed/atags_to_fdt.c index d1153c8a765a..9448aa0c6686 100644 --- a/arch/arm/boot/compressed/atags_to_fdt.c +++ b/arch/arm/boot/compressed/atags_to_fdt.c @@ -7,6 +7,8 @@ #define do_extend_cmdline 0 #endif +#define NR_BANKS 16 + static int node_offset(void *fdt, const char *node_path) { int offset = fdt_path_offset(fdt, node_path); diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index 066b03480b63..3a8b32df6b31 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -60,11 +60,6 @@ add \rb, \rb, #0x00010000 @ Ser1 #endif .endm -#elif defined(CONFIG_ARCH_S3C24XX) - .macro loadsp, rb, tmp - mov \rb, #0x50000000 - add \rb, \rb, #0x4000 * CONFIG_S3C_LOWLEVEL_UART_PORT - .endm #else .macro loadsp, rb, tmp addruart \rb, \tmp diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 377b7c364033..5986ff63b901 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -50,13 +50,15 @@ dtb-$(CONFIG_ARCH_AT91) += sama5d35ek.dtb dtb-$(CONFIG_ARCH_AT91) += sama5d36ek.dtb dtb-$(CONFIG_ARCH_ATLAS6) += atlas6-evb.dtb +dtb-$(CONFIG_ARCH_AXXIA) += axm5516-amarillo.dtb dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb dtb-$(CONFIG_ARCH_BCM_5301X) += bcm4708-netgear-r6250.dtb dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm28155-ap.dtb \ bcm21664-garnet.dtb dtb-$(CONFIG_ARCH_BERLIN) += \ berlin2-sony-nsz-gs7.dtb \ - berlin2cd-google-chromecast.dtb + berlin2cd-google-chromecast.dtb \ + berlin2q-marvell-dmp.dtb dtb-$(CONFIG_ARCH_DAVINCI) += da850-enbw-cmc.dtb \ da850-evm.dtb dtb-$(CONFIG_ARCH_EFM32) += efm32gg-dk3750.dtb @@ -72,10 +74,14 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \ exynos5250-arndale.dtb \ exynos5250-smdk5250.dtb \ exynos5250-snow.dtb \ + exynos5260-xyref5260.dtb \ + exynos5410-smdk5410.dtb \ exynos5420-arndale-octa.dtb \ + exynos5420-peach-pit.dtb \ exynos5420-smdk5420.dtb \ exynos5440-sd5v1.dtb \ - exynos5440-ssdk5440.dtb + exynos5440-ssdk5440.dtb \ + exynos5800-peach-pi.dtb dtb-$(CONFIG_ARCH_HI3xxx) += hi3620-hi4511.dtb dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb \ ecx-2000.dtb @@ -127,6 +133,9 @@ kirkwood := \ kirkwood-nsa310a.dtb \ kirkwood-openblocks_a6.dtb \ kirkwood-openblocks_a7.dtb \ + kirkwood-openrd-base.dtb \ + kirkwood-openrd-client.dtb \ + kirkwood-openrd-ultimate.dtb \ kirkwood-rd88f6192.dtb \ kirkwood-rd88f6281-a0.dtb \ kirkwood-rd88f6281-a1.dtb \ @@ -157,10 +166,12 @@ dtb-$(CONFIG_ARCH_MXC) += \ imx27-phytec-phycard-s-rdk.dtb \ imx31-bug.dtb \ imx35-eukrea-mbimxsd35-baseboard.dtb \ + imx35-pdk.dtb \ imx50-evk.dtb \ imx51-apf51.dtb \ imx51-apf51dev.dtb \ imx51-babbage.dtb \ + imx51-digi-connectcore-jsk.dtb \ imx51-eukrea-mbimxsd51-baseboard.dtb \ imx53-ard.dtb \ imx53-m53evk.dtb \ @@ -179,6 +190,8 @@ dtb-$(CONFIG_ARCH_MXC) += \ imx6dl-gw54xx.dtb \ imx6dl-hummingboard.dtb \ imx6dl-nitrogen6x.dtb \ + imx6dl-phytec-pbab01.dtb \ + imx6dl-riotboard.dtb \ imx6dl-sabreauto.dtb \ imx6dl-sabrelite.dtb \ imx6dl-sabresd.dtb \ @@ -203,6 +216,7 @@ dtb-$(CONFIG_ARCH_MXC) += \ imx6q-udoo.dtb \ imx6q-wandboard.dtb \ imx6sl-evk.dtb \ + vf610-colibri.dtb \ vf610-cosmic.dtb \ vf610-twr.dtb dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \ @@ -230,76 +244,84 @@ dtb-$(CONFIG_ARCH_NOMADIK) += ste-nomadik-s8815.dtb dtb-$(CONFIG_ARCH_NSPIRE) += nspire-cx.dtb \ nspire-tp.dtb \ nspire-clp.dtb -dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \ - omap2430-sdp.dtb \ +dtb-$(CONFIG_ARCH_OMAP2) += omap2420-h4.dtb \ omap2420-n800.dtb \ omap2420-n810.dtb \ omap2420-n810-wimax.dtb \ + omap2430-sdp.dtb +dtb-$(CONFIG_ARCH_OMAP3) += am3517-craneboard.dtb \ + am3517-evm.dtb \ + am3517_mt_ventoux.dtb \ omap3430-sdp.dtb \ omap3-beagle.dtb \ + omap3-beagle-xm.dtb \ + omap3-beagle-xm-ab.dtb \ omap3-cm-t3517.dtb \ - omap3-sbc-t3517.dtb \ omap3-cm-t3530.dtb \ - omap3-sbc-t3530.dtb \ omap3-cm-t3730.dtb \ - omap3-sbc-t3730.dtb \ omap3-devkit8000.dtb \ - omap3-beagle-xm.dtb \ - omap3-beagle-xm-ab.dtb \ omap3-evm.dtb \ omap3-evm-37xx.dtb \ + omap3-gta04.dtb \ + omap3-igep0020.dtb \ + omap3-igep0030.dtb \ omap3-ldp.dtb \ + omap3-lilly-dbb056.dtb \ omap3-n900.dtb \ omap3-n9.dtb \ omap3-n950.dtb \ omap3-overo-alto35.dtb \ - omap3-overo-storm-alto35.dtb \ omap3-overo-chestnut43.dtb \ - omap3-overo-storm-chestnut43.dtb \ omap3-overo-gallop43.dtb \ - omap3-overo-storm-gallop43.dtb \ omap3-overo-palo43.dtb \ + omap3-overo-storm-alto35.dtb \ + omap3-overo-storm-chestnut43.dtb \ + omap3-overo-storm-gallop43.dtb \ omap3-overo-storm-palo43.dtb \ - omap3-overo-summit.dtb \ omap3-overo-storm-summit.dtb \ - omap3-overo-tobi.dtb \ omap3-overo-storm-tobi.dtb \ - omap3-gta04.dtb \ - omap3-igep0020.dtb \ - omap3-igep0030.dtb \ - omap3-lilly-dbb056.dtb \ - omap3-zoom3.dtb \ - omap4-duovero-parlor.dtb \ + omap3-overo-summit.dtb \ + omap3-overo-tobi.dtb \ + omap3-sbc-t3517.dtb \ + omap3-sbc-t3530.dtb \ + omap3-sbc-t3730.dtb \ + omap3-zoom3.dtb +dtb-$(CONFIG_SOC_AM33XX) += am335x-base0033.dtb \ + am335x-bone.dtb \ + am335x-boneblack.dtb \ + am335x-evm.dtb \ + am335x-evmsk.dtb \ + am335x-nano.dtb +dtb-$(CONFIG_ARCH_OMAP4) += omap4-duovero-parlor.dtb \ omap4-panda.dtb \ omap4-panda-a4.dtb \ omap4-panda-es.dtb \ - omap4-var-som.dtb \ omap4-sdp.dtb \ omap4-sdp-es23plus.dtb \ - omap5-uevm.dtb \ - am335x-evm.dtb \ - am335x-evmsk.dtb \ - am335x-bone.dtb \ - am335x-boneblack.dtb \ - am335x-nano.dtb \ - am335x-base0033.dtb \ - am3517-craneboard.dtb \ - am3517-evm.dtb \ - am3517_mt_ventoux.dtb \ - am43x-epos-evm.dtb \ - am437x-gp-evm.dtb \ - dra7-evm.dtb -dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-ethernet-disk-mini-v2.dtb + omap4-var-dvk-om44.dtb \ + omap4-var-stk-om44.dtb +dtb-$(CONFIG_SOC_AM43XX) += am43x-epos-evm.dtb \ + am437x-gp-evm.dtb +dtb-$(CONFIG_SOC_OMAP5) += omap5-cm-t54.dtb \ + omap5-sbc-t54.dtb \ + omap5-uevm.dtb +dtb-$(CONFIG_SOC_DRA7XX) += dra7-evm.dtb \ + dra72-evm.dtb +dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-d2-network.dtb \ + orion5x-lacie-ethernet-disk-mini-v2.dtb \ + orion5x-maxtor-shared-storage-2.dtb \ + orion5x-rd88f5182-nas.dtb dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb -dtb-$(CONFIG_ARCH_QCOM) += qcom-msm8660-surf.dtb \ - qcom-msm8960-cdp.dtb \ - qcom-apq8074-dragonboard.dtb +dtb-$(CONFIG_ARCH_QCOM) += \ + qcom-apq8064-ifc6410.dtb \ + qcom-apq8074-dragonboard.dtb \ + qcom-apq8084-mtp.dtb \ + qcom-msm8660-surf.dtb \ + qcom-msm8960-cdp.dtb dtb-$(CONFIG_ARCH_S3C24XX) += s3c2416-smdk2416.dtb dtb-$(CONFIG_ARCH_S3C64XX) += s3c6410-mini6410.dtb \ s3c6410-smdk6410.dtb -dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += emev2-kzm9d.dtb \ - r7s72100-genmai.dtb \ - r7s72100-genmai-reference.dtb \ +dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += r7s72100-genmai.dtb \ r8a7740-armadillo800eva.dtb \ r8a7778-bockw.dtb \ r8a7778-bockw-reference.dtb \ @@ -314,12 +336,14 @@ dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += emev2-kzm9d.dtb \ r8a73a4-ape6evm-reference.dtb \ sh7372-mackerel.dtb dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += emev2-kzm9d.dtb \ - r7s72100-genmai-reference.dtb \ + r7s72100-genmai.dtb \ + r8a7791-henninger.dtb \ r8a7791-koelsch.dtb \ r8a7790-lager.dtb dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_arria5_socdk.dtb \ socfpga_cyclone5_socdk.dtb \ socfpga_cyclone5_sockit.dtb \ + socfpga_cyclone5_socrates.dtb \ socfpga_vt.dtb dtb-$(CONFIG_ARCH_SPEAR13XX) += spear1310-evb.dtb \ spear1340-evb.dtb @@ -328,24 +352,33 @@ dtb-$(CONFIG_ARCH_SPEAR3XX)+= spear300-evb.dtb \ spear320-evb.dtb \ spear320-hmi.dtb dtb-$(CONFIG_ARCH_SPEAR6XX)+= spear600-evb.dtb -dtb-$(CONFIG_ARCH_STI)+= stih415-b2000.dtb \ - stih416-b2000.dtb \ +dtb-$(CONFIG_ARCH_STI)+= stih407-b2120.dtb \ + stih415-b2000.dtb \ stih415-b2020.dtb \ - stih416-b2020.dtb -dtb-$(CONFIG_ARCH_SUNXI) += \ + stih416-b2000.dtb \ + stih416-b2020.dtb \ + stih416-b2020-revE.dtb +dtb-$(CONFIG_MACH_SUN4I) += \ sun4i-a10-a1000.dtb \ sun4i-a10-cubieboard.dtb \ sun4i-a10-mini-xplus.dtb \ sun4i-a10-hackberry.dtb \ sun4i-a10-inet97fv2.dtb \ sun4i-a10-olinuxino-lime.dtb \ - sun4i-a10-pcduino.dtb \ + sun4i-a10-pcduino.dtb +dtb-$(CONFIG_MACH_SUN5I) += \ sun5i-a10s-olinuxino-micro.dtb \ + sun5i-a10s-r7-tv-dongle.dtb \ sun5i-a13-olinuxino.dtb \ - sun5i-a13-olinuxino-micro.dtb \ + sun5i-a13-olinuxino-micro.dtb +dtb-$(CONFIG_MACH_SUN6I) += \ + sun6i-a31-app4-evb1.dtb \ sun6i-a31-colombus.dtb \ + sun6i-a31-m9.dtb +dtb-$(CONFIG_MACH_SUN7I) += \ sun7i-a20-cubieboard2.dtb \ sun7i-a20-cubietruck.dtb \ + sun7i-a20-i12-tvbox.dtb \ sun7i-a20-olinuxino-micro.dtb dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \ tegra20-iris-512.dtb \ @@ -360,7 +393,11 @@ dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \ tegra30-beaver.dtb \ tegra30-cardhu-a02.dtb \ tegra30-cardhu-a04.dtb \ + tegra30-colibri-eval-v3.dtb \ tegra114-dalmore.dtb \ + tegra114-roth.dtb \ + tegra114-tn7.dtb \ + tegra124-jetson-tk1.dtb \ tegra124-venice2.dtb dtb-$(CONFIG_ARCH_U300) += ste-u300.dtb dtb-$(CONFIG_ARCH_U8500) += ste-snowball.dtb \ diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi b/arch/arm/boot/dts/am335x-bone-common.dtsi index 2e7d932887b5..bde1777b62be 100644 --- a/arch/arm/boot/dts/am335x-bone-common.dtsi +++ b/arch/arm/boot/dts/am335x-bone-common.dtsi @@ -182,31 +182,31 @@ &usb { status = "okay"; +}; - control@44e10620 { - status = "okay"; - }; +&usb_ctrl_mod { + status = "okay"; +}; - usb-phy@47401300 { - status = "okay"; - }; +&usb0_phy { + status = "okay"; +}; - usb-phy@47401b00 { - status = "okay"; - }; +&usb1_phy { + status = "okay"; +}; - usb@47401000 { - status = "okay"; - }; +&usb0 { + status = "okay"; +}; - usb@47401800 { - status = "okay"; - dr_mode = "host"; - }; +&usb1 { + status = "okay"; + dr_mode = "host"; +}; - dma-controller@47402000 { - status = "okay"; - }; +&cppi41dma { + status = "okay"; }; &i2c0 { @@ -280,13 +280,14 @@ pinctrl-names = "default", "sleep"; pinctrl-0 = <&cpsw_default>; pinctrl-1 = <&cpsw_sleep>; - + status = "okay"; }; &davinci_mdio { pinctrl-names = "default", "sleep"; pinctrl-0 = <&davinci_mdio_default>; pinctrl-1 = <&davinci_mdio_sleep>; + status = "okay"; }; &mmc1 { diff --git a/arch/arm/boot/dts/am335x-boneblack.dts b/arch/arm/boot/dts/am335x-boneblack.dts index 6b71ad95a5cf..305975d3f531 100644 --- a/arch/arm/boot/dts/am335x-boneblack.dts +++ b/arch/arm/boot/dts/am335x-boneblack.dts @@ -26,7 +26,6 @@ pinctrl-0 = <&emmc_pins>; bus-width = <8>; status = "okay"; - ti,vcc-aux-disable-is-sleep; }; &am33xx_pinmux { diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts index 6028217ace0f..ecb267767cf5 100644 --- a/arch/arm/boot/dts/am335x-evm.dts +++ b/arch/arm/boot/dts/am335x-evm.dts @@ -268,34 +268,34 @@ lcd_pins_s0: lcd_pins_s0 { pinctrl-single,pins = < - 0x20 0x01 /* gpmc_ad8.lcd_data16, OUTPUT | MODE1 */ - 0x24 0x01 /* gpmc_ad9.lcd_data17, OUTPUT | MODE1 */ - 0x28 0x01 /* gpmc_ad10.lcd_data18, OUTPUT | MODE1 */ - 0x2c 0x01 /* gpmc_ad11.lcd_data19, OUTPUT | MODE1 */ - 0x30 0x01 /* gpmc_ad12.lcd_data20, OUTPUT | MODE1 */ - 0x34 0x01 /* gpmc_ad13.lcd_data21, OUTPUT | MODE1 */ - 0x38 0x01 /* gpmc_ad14.lcd_data22, OUTPUT | MODE1 */ - 0x3c 0x01 /* gpmc_ad15.lcd_data23, OUTPUT | MODE1 */ - 0xa0 0x00 /* lcd_data0.lcd_data0, OUTPUT | MODE0 */ - 0xa4 0x00 /* lcd_data1.lcd_data1, OUTPUT | MODE0 */ - 0xa8 0x00 /* lcd_data2.lcd_data2, OUTPUT | MODE0 */ - 0xac 0x00 /* lcd_data3.lcd_data3, OUTPUT | MODE0 */ - 0xb0 0x00 /* lcd_data4.lcd_data4, OUTPUT | MODE0 */ - 0xb4 0x00 /* lcd_data5.lcd_data5, OUTPUT | MODE0 */ - 0xb8 0x00 /* lcd_data6.lcd_data6, OUTPUT | MODE0 */ - 0xbc 0x00 /* lcd_data7.lcd_data7, OUTPUT | MODE0 */ - 0xc0 0x00 /* lcd_data8.lcd_data8, OUTPUT | MODE0 */ - 0xc4 0x00 /* lcd_data9.lcd_data9, OUTPUT | MODE0 */ - 0xc8 0x00 /* lcd_data10.lcd_data10, OUTPUT | MODE0 */ - 0xcc 0x00 /* lcd_data11.lcd_data11, OUTPUT | MODE0 */ - 0xd0 0x00 /* lcd_data12.lcd_data12, OUTPUT | MODE0 */ - 0xd4 0x00 /* lcd_data13.lcd_data13, OUTPUT | MODE0 */ - 0xd8 0x00 /* lcd_data14.lcd_data14, OUTPUT | MODE0 */ - 0xdc 0x00 /* lcd_data15.lcd_data15, OUTPUT | MODE0 */ - 0xe0 0x00 /* lcd_vsync.lcd_vsync, OUTPUT | MODE0 */ - 0xe4 0x00 /* lcd_hsync.lcd_hsync, OUTPUT | MODE0 */ - 0xe8 0x00 /* lcd_pclk.lcd_pclk, OUTPUT | MODE0 */ - 0xec 0x00 /* lcd_ac_bias_en.lcd_ac_bias_en, OUTPUT | MODE0 */ + 0x20 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad8.lcd_data23 */ + 0x24 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad9.lcd_data22 */ + 0x28 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad10.lcd_data21 */ + 0x2c (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad11.lcd_data20 */ + 0x30 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad12.lcd_data19 */ + 0x34 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad13.lcd_data18 */ + 0x38 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad14.lcd_data17 */ + 0x3c (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad15.lcd_data16 */ + 0xa0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data0.lcd_data0 */ + 0xa4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data1.lcd_data1 */ + 0xa8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data2.lcd_data2 */ + 0xac (PIN_OUTPUT | MUX_MODE0) /* lcd_data3.lcd_data3 */ + 0xb0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data4.lcd_data4 */ + 0xb4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data5.lcd_data5 */ + 0xb8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data6.lcd_data6 */ + 0xbc (PIN_OUTPUT | MUX_MODE0) /* lcd_data7.lcd_data7 */ + 0xc0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data8.lcd_data8 */ + 0xc4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data9.lcd_data9 */ + 0xc8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data10.lcd_data10 */ + 0xcc (PIN_OUTPUT | MUX_MODE0) /* lcd_data11.lcd_data11 */ + 0xd0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data12.lcd_data12 */ + 0xd4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data13.lcd_data13 */ + 0xd8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data14.lcd_data14 */ + 0xdc (PIN_OUTPUT | MUX_MODE0) /* lcd_data15.lcd_data15 */ + 0xe0 (PIN_OUTPUT | MUX_MODE0) /* lcd_vsync.lcd_vsync */ + 0xe4 (PIN_OUTPUT | MUX_MODE0) /* lcd_hsync.lcd_hsync */ + 0xe8 (PIN_OUTPUT | MUX_MODE0) /* lcd_pclk.lcd_pclk */ + 0xec (PIN_OUTPUT | MUX_MODE0) /* lcd_ac_bias_en.lcd_ac_bias_en */ >; }; @@ -330,31 +330,31 @@ &usb { status = "okay"; +}; - control@44e10620 { - status = "okay"; - }; +&usb_ctrl_mod { + status = "okay"; +}; - usb-phy@47401300 { - status = "okay"; - }; +&usb0_phy { + status = "okay"; +}; - usb-phy@47401b00 { - status = "okay"; - }; +&usb1_phy { + status = "okay"; +}; - usb@47401000 { - status = "okay"; - }; +&usb0 { + status = "okay"; +}; - usb@47401800 { - status = "okay"; - dr_mode = "host"; - }; +&usb1 { + status = "okay"; + dr_mode = "host"; +}; - dma-controller@47402000 { - status = "okay"; - }; +&cppi41dma { + status = "okay"; }; &i2c1 { @@ -614,12 +614,14 @@ pinctrl-names = "default", "sleep"; pinctrl-0 = <&cpsw_default>; pinctrl-1 = <&cpsw_sleep>; + status = "okay"; }; &davinci_mdio { pinctrl-names = "default", "sleep"; pinctrl-0 = <&davinci_mdio_default>; pinctrl-1 = <&davinci_mdio_sleep>; + status = "okay"; }; &cpsw_emac0 { diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts index ab238850a7b2..ab9a34ce524c 100644 --- a/arch/arm/boot/dts/am335x-evmsk.dts +++ b/arch/arm/boot/dts/am335x-evmsk.dts @@ -57,6 +57,17 @@ enable-active-high; }; + vtt_fixed: fixedregulator@3 { + compatible = "regulator-fixed"; + regulator-name = "vtt"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + gpio = <&gpio0 7 GPIO_ACTIVE_HIGH>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + }; + leds { pinctrl-names = "default"; pinctrl-0 = <&user_leds_s0>; @@ -363,31 +374,31 @@ &usb { status = "okay"; +}; - control@44e10620 { - status = "okay"; - }; +&usb_ctrl_mod { + status = "okay"; +}; - usb-phy@47401300 { - status = "okay"; - }; +&usb0_phy { + status = "okay"; +}; - usb-phy@47401b00 { - status = "okay"; - }; +&usb1_phy { + status = "okay"; +}; - usb@47401000 { - status = "okay"; - }; +&usb0 { + status = "okay"; +}; - usb@47401800 { - status = "okay"; - dr_mode = "host"; - }; +&usb1 { + status = "okay"; + dr_mode = "host"; +}; - dma-controller@47402000 { - status = "okay"; - }; +&cppi41dma { + status = "okay"; }; &epwmss2 { @@ -484,12 +495,14 @@ pinctrl-0 = <&cpsw_default>; pinctrl-1 = <&cpsw_sleep>; dual_emac = <1>; + status = "okay"; }; &davinci_mdio { pinctrl-names = "default", "sleep"; pinctrl-0 = <&davinci_mdio_default>; pinctrl-1 = <&davinci_mdio_sleep>; + status = "okay"; }; &cpsw_emac0 { diff --git a/arch/arm/boot/dts/am335x-igep0033.dtsi b/arch/arm/boot/dts/am335x-igep0033.dtsi index 9f22c189f636..8a0a72dc7dd7 100644 --- a/arch/arm/boot/dts/am335x-igep0033.dtsi +++ b/arch/arm/boot/dts/am335x-igep0033.dtsi @@ -95,6 +95,14 @@ }; }; +&mac { + status = "okay"; +}; + +&davinci_mdio { + status = "okay"; +}; + &cpsw_emac0 { phy_id = <&davinci_mdio>, <0>; }; @@ -200,31 +208,31 @@ &usb { status = "okay"; +}; - control@44e10620 { - status = "okay"; - }; +&usb_ctrl_mod { + status = "okay"; +}; - usb-phy@47401300 { - status = "okay"; - }; +&usb0_phy { + status = "okay"; +}; - usb-phy@47401b00 { - status = "okay"; - }; +&usb1_phy { + status = "okay"; +}; - usb@47401000 { - status = "okay"; - }; +&usb0 { + status = "okay"; +}; - usb@47401800 { - status = "okay"; - dr_mode = "host"; - }; +&usb1 { + status = "okay"; + dr_mode = "host"; +}; - dma-controller@47402000 { - status = "okay"; - }; +&cppi41dma { + status = "okay"; }; #include "tps65910.dtsi" diff --git a/arch/arm/boot/dts/am335x-nano.dts b/arch/arm/boot/dts/am335x-nano.dts index 9907b494b99c..a3466455b171 100644 --- a/arch/arm/boot/dts/am335x-nano.dts +++ b/arch/arm/boot/dts/am335x-nano.dts @@ -344,6 +344,11 @@ &mac { dual_emac = <1>; + status = "okay"; +}; + +&davinci_mdio { + status = "okay"; }; &cpsw_emac0 { diff --git a/arch/arm/boot/dts/am33xx-clocks.dtsi b/arch/arm/boot/dts/am33xx-clocks.dtsi index 9ccfe508dea2..712edce7d6fb 100644 --- a/arch/arm/boot/dts/am33xx-clocks.dtsi +++ b/arch/arm/boot/dts/am33xx-clocks.dtsi @@ -96,47 +96,29 @@ clock-div = <1>; }; - ehrpwm0_gate_tbclk: ehrpwm0_gate_tbclk { + ehrpwm0_tbclk: ehrpwm0_tbclk@44e10664 { #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; + compatible = "ti,gate-clock"; clocks = <&dpll_per_m2_ck>; ti,bit-shift = <0>; reg = <0x0664>; }; - ehrpwm0_tbclk: ehrpwm0_tbclk { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&ehrpwm0_gate_tbclk>; - }; - - ehrpwm1_gate_tbclk: ehrpwm1_gate_tbclk { + ehrpwm1_tbclk: ehrpwm1_tbclk@44e10664 { #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; + compatible = "ti,gate-clock"; clocks = <&dpll_per_m2_ck>; ti,bit-shift = <1>; reg = <0x0664>; }; - ehrpwm1_tbclk: ehrpwm1_tbclk { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&ehrpwm1_gate_tbclk>; - }; - - ehrpwm2_gate_tbclk: ehrpwm2_gate_tbclk { + ehrpwm2_tbclk: ehrpwm2_tbclk@44e10664 { #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; + compatible = "ti,gate-clock"; clocks = <&dpll_per_m2_ck>; ti,bit-shift = <2>; reg = <0x0664>; }; - - ehrpwm2_tbclk: ehrpwm2_tbclk { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&ehrpwm2_gate_tbclk>; - }; }; &prcm_clocks { clk_32768_ck: clk_32768_ck { diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index 7ad75b4e0663..9f53e824b037 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -147,9 +147,6 @@ <0x44e10f90 0x40>; interrupts = <12 13 14>; #dma-cells = <1>; - dma-channels = <64>; - ti,edma-regions = <4>; - ti,edma-slots = <256>; }; gpio0: gpio@44e07000 { @@ -688,6 +685,7 @@ */ interrupts = <40 41 42 43>; ranges; + status = "disabled"; davinci_mdio: mdio@4a101000 { compatible = "ti,davinci_mdio"; @@ -696,6 +694,7 @@ ti,hwmods = "davinci_mdio"; bus_freq = <1000000>; reg = <0x4a101000 0x100>; + status = "disabled"; }; cpsw_emac0: slave@4a100200 { diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi index d1f8707ff1df..794c73e5c4e4 100644 --- a/arch/arm/boot/dts/am4372.dtsi +++ b/arch/arm/boot/dts/am4372.dtsi @@ -67,11 +67,15 @@ }; ocp { - compatible = "simple-bus"; + compatible = "ti,am4372-l3-noc", "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges; ti,hwmods = "l3_main"; + reg = <0x44000000 0x400000 + 0x44800000 0x400000>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; prcm: prcm@44df0000 { compatible = "ti,am4-prcm"; @@ -108,9 +112,6 @@ <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; #dma-cells = <1>; - dma-channels = <64>; - ti,edma-regions = <4>; - ti,edma-slots = <256>; }; uart0: serial@44e09000 { @@ -521,6 +522,12 @@ /* Filled in by U-Boot */ mac-address = [ 00 00 00 00 00 00 ]; }; + + phy_sel: cpsw-phy-sel@44e10650 { + compatible = "ti,am43xx-cpsw-phy-sel"; + reg= <0x44e10650 0x4>; + reg-names = "gmii-sel"; + }; }; epwmss0: epwmss@48300000 { @@ -735,6 +742,121 @@ #size-cells = <1>; status = "disabled"; }; + + am43xx_control_usb2phy1: control-phy@44e10620 { + compatible = "ti,control-phy-usb2-am437"; + reg = <0x44e10620 0x4>; + reg-names = "power"; + }; + + am43xx_control_usb2phy2: control-phy@0x44e10628 { + compatible = "ti,control-phy-usb2-am437"; + reg = <0x44e10628 0x4>; + reg-names = "power"; + }; + + ocp2scp0: ocp2scp@483a8000 { + compatible = "ti,omap-ocp2scp"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + ti,hwmods = "ocp2scp0"; + + usb2_phy1: phy@483a8000 { + compatible = "ti,am437x-usb2"; + reg = <0x483a8000 0x8000>; + ctrl-module = <&am43xx_control_usb2phy1>; + clocks = <&usb_phy0_always_on_clk32k>, + <&usb_otg_ss0_refclk960m>; + clock-names = "wkupclk", "refclk"; + #phy-cells = <0>; + status = "disabled"; + }; + }; + + ocp2scp1: ocp2scp@483e8000 { + compatible = "ti,omap-ocp2scp"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + ti,hwmods = "ocp2scp1"; + + usb2_phy2: phy@483e8000 { + compatible = "ti,am437x-usb2"; + reg = <0x483e8000 0x8000>; + ctrl-module = <&am43xx_control_usb2phy2>; + clocks = <&usb_phy1_always_on_clk32k>, + <&usb_otg_ss1_refclk960m>; + clock-names = "wkupclk", "refclk"; + #phy-cells = <0>; + status = "disabled"; + }; + }; + + dwc3_1: omap_dwc3@48380000 { + compatible = "ti,am437x-dwc3"; + ti,hwmods = "usb_otg_ss0"; + reg = <0x48380000 0x10000>; + interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <1>; + utmi-mode = <1>; + ranges; + + usb1: usb@48390000 { + compatible = "synopsys,dwc3"; + reg = <0x48390000 0x17000>; + interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; + phys = <&usb2_phy1>; + phy-names = "usb2-phy"; + maximum-speed = "high-speed"; + dr_mode = "otg"; + status = "disabled"; + }; + }; + + dwc3_2: omap_dwc3@483c0000 { + compatible = "ti,am437x-dwc3"; + ti,hwmods = "usb_otg_ss1"; + reg = <0x483c0000 0x10000>; + interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <1>; + utmi-mode = <1>; + ranges; + + usb2: usb@483d0000 { + compatible = "synopsys,dwc3"; + reg = <0x483d0000 0x17000>; + interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; + phys = <&usb2_phy2>; + phy-names = "usb2-phy"; + maximum-speed = "high-speed"; + dr_mode = "otg"; + status = "disabled"; + }; + }; + + qspi: qspi@47900000 { + compatible = "ti,am4372-qspi"; + reg = <0x47900000 0x100>; + #address-cells = <1>; + #size-cells = <0>; + ti,hwmods = "qspi"; + interrupts = <0 138 0x4>; + num-cs = <4>; + status = "disabled"; + }; + + hdq: hdq@48347000 { + compatible = "ti,am43xx-hdq"; + reg = <0x48347000 0x1000>; + interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&func_12m_clk>; + clock-names = "fck"; + ti,hwmods = "hdq1w"; + status = "disabled"; + }; }; }; diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts index a055f7f0f14a..c25d15837ce9 100644 --- a/arch/arm/boot/dts/am437x-gp-evm.dts +++ b/arch/arm/boot/dts/am437x-gp-evm.dts @@ -27,6 +27,17 @@ enable-active-high; }; + vtt_fixed: fixedregulator-vtt { + compatible = "regulator-fixed"; + regulator-name = "vtt_fixed"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>; + }; + backlight { compatible = "pwm-backlight"; pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>; @@ -81,6 +92,85 @@ 0x164 MUX_MODE0 /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */ >; }; + + pixcir_ts_pins: pixcir_ts_pins { + pinctrl-single,pins = < + 0x264 (PIN_INPUT_PULLUP | MUX_MODE7) /* spi2_d0.gpio3_22 */ + >; + }; + + cpsw_default: cpsw_default { + pinctrl-single,pins = < + /* Slave 1 */ + 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_txen */ + 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rxctl */ + 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd3 */ + 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd2 */ + 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd1 */ + 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd0 */ + 0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rmii1_tclk */ + 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */ + 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd3 */ + 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd2 */ + 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd1 */ + 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd0 */ + >; + }; + + cpsw_sleep: cpsw_sleep { + pinctrl-single,pins = < + /* Slave 1 reset value */ + 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + davinci_mdio_default: davinci_mdio_default { + pinctrl-single,pins = < + /* MDIO */ + 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ + 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ + >; + }; + + davinci_mdio_sleep: davinci_mdio_sleep { + pinctrl-single,pins = < + /* MDIO reset value */ + 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + nand_flash_x8: nand_flash_x8 { + pinctrl-single,pins = < + 0x26c(PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* spi2_cs0.gpio/eMMCorNANDsel */ + 0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ + 0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ + 0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ + 0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ + 0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ + 0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ + 0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ + 0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ + 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ + 0x74 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpmc_wpn */ + 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ + 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ + 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ + 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */ + 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ + >; + }; }; &i2c0 { @@ -93,6 +183,20 @@ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&i2c1_pins>; + + pixcir_ts@5c { + compatible = "pixcir,pixcir_tangoc"; + pinctrl-names = "default"; + pinctrl-0 = <&pixcir_ts_pins>; + reg = <0x5c>; + interrupt-parent = <&gpio3>; + interrupts = <22 0>; + + attb-gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + + x-size = <1024>; + y-size = <600>; + }; }; &epwmss0 { @@ -130,3 +234,128 @@ pinctrl-0 = <&mmc1_pins>; cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; }; + +&usb2_phy1 { + status = "okay"; +}; + +&usb1 { + dr_mode = "peripheral"; + status = "okay"; +}; + +&usb2_phy2 { + status = "okay"; +}; + +&usb2 { + dr_mode = "host"; + status = "okay"; +}; + +&mac { + slaves = <1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cpsw_default>; + pinctrl-1 = <&cpsw_sleep>; + status = "okay"; +}; + +&davinci_mdio { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&davinci_mdio_default>; + pinctrl-1 = <&davinci_mdio_sleep>; + status = "okay"; +}; + +&cpsw_emac0 { + phy_id = <&davinci_mdio>, <0>; + phy-mode = "rgmii"; +}; + +&elm { + status = "okay"; +}; + +&gpmc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&nand_flash_x8>; + ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */ + nand@0,0 { + reg = <0 0 4>; /* device IO registers */ + ti,nand-ecc-opt = "bch8"; + ti,elm-id = <&elm>; + nand-bus-width = <8>; + gpmc,device-width = <1>; + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <40>; + gpmc,cs-wr-off-ns = <40>; + gpmc,adv-on-ns = <0>; + gpmc,adv-rd-off-ns = <25>; + gpmc,adv-wr-off-ns = <25>; + gpmc,we-on-ns = <0>; + gpmc,we-off-ns = <20>; + gpmc,oe-on-ns = <3>; + gpmc,oe-off-ns = <30>; + gpmc,access-ns = <30>; + gpmc,rd-cycle-ns = <40>; + gpmc,wr-cycle-ns = <40>; + gpmc,wait-pin = <0>; + gpmc,wait-on-read; + gpmc,wait-on-write; + gpmc,bus-turnaround-ns = <0>; + gpmc,cycle2cycle-delay-ns = <0>; + gpmc,clk-activation-ns = <0>; + gpmc,wait-monitoring-ns = <0>; + gpmc,wr-access-ns = <40>; + gpmc,wr-data-mux-bus-ns = <0>; + /* MTD partition table */ + /* All SPL-* partitions are sized to minimal length + * which can be independently programmable. For + * NAND flash this is equal to size of erase-block */ + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "NAND.SPL"; + reg = <0x00000000 0x00040000>; + }; + partition@1 { + label = "NAND.SPL.backup1"; + reg = <0x00040000 0x00040000>; + }; + partition@2 { + label = "NAND.SPL.backup2"; + reg = <0x00080000 0x00040000>; + }; + partition@3 { + label = "NAND.SPL.backup3"; + reg = <0x000c0000 0x00040000>; + }; + partition@4 { + label = "NAND.u-boot-spl-os"; + reg = <0x00100000 0x00080000>; + }; + partition@5 { + label = "NAND.u-boot"; + reg = <0x00180000 0x00100000>; + }; + partition@6 { + label = "NAND.u-boot-env"; + reg = <0x00280000 0x00040000>; + }; + partition@7 { + label = "NAND.u-boot-env.backup1"; + reg = <0x002c0000 0x00040000>; + }; + partition@8 { + label = "NAND.kernel"; + reg = <0x00300000 0x00700000>; + }; + partition@9 { + label = "NAND.file-system"; + reg = <0x00a00000 0x1f600000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts index 167dbc8494de..ad362c50e32e 100644 --- a/arch/arm/boot/dts/am43x-epos-evm.dts +++ b/arch/arm/boot/dts/am43x-epos-evm.dts @@ -138,6 +138,29 @@ 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ >; }; + + qspi1_default: qspi1_default { + pinctrl-single,pins = < + 0x7c (PIN_INPUT_PULLUP | MUX_MODE3) + 0x88 (PIN_INPUT_PULLUP | MUX_MODE2) + 0x90 (PIN_INPUT_PULLUP | MUX_MODE3) + 0x94 (PIN_INPUT_PULLUP | MUX_MODE3) + 0x98 (PIN_INPUT_PULLUP | MUX_MODE3) + 0x9c (PIN_INPUT_PULLUP | MUX_MODE3) + >; + }; + + pixcir_ts_pins: pixcir_ts_pins { + pinctrl-single,pins = < + 0x44 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_a1.gpio1_17 */ + >; + }; + + hdq_pins: pinmux_hdq_pins { + pinctrl-single,pins = < + 0x234 (PIN_INPUT_PULLUP | MUX_MODE1) /* cam1_wen.hdq_gpio */ + >; + }; }; matrix_keypad: matrix_keypad@0 { @@ -226,7 +249,9 @@ }; pixcir_ts@5c { - compatible = "pixcir,pixcir_ts"; + compatible = "pixcir,pixcir_tangoc"; + pinctrl-names = "default"; + pinctrl-0 = <&pixcir_ts_pins>; reg = <0x5c>; interrupt-parent = <&gpio1>; interrupts = <17 0>; @@ -234,7 +259,7 @@ attb-gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>; x-size = <1024>; - y-size = <768>; + y-size = <600>; }; }; @@ -341,7 +366,7 @@ }; partition@9 { label = "NAND.file-system"; - reg = <0x00800000 0x1F600000>; + reg = <0x00a00000 0x1f600000>; }; }; }; @@ -367,3 +392,79 @@ pinctrl-0 = <&spi1_pins>; status = "okay"; }; + +&usb2_phy1 { + status = "okay"; +}; + +&usb1 { + dr_mode = "peripheral"; + status = "okay"; +}; + +&usb2_phy2 { + status = "okay"; +}; + +&usb2 { + dr_mode = "host"; + status = "okay"; +}; + +&qspi { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&qspi1_default>; + + spi-max-frequency = <48000000>; + m25p80@0 { + compatible = "mx66l51235l"; + spi-max-frequency = <48000000>; + reg = <0>; + spi-cpol; + spi-cpha; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + #address-cells = <1>; + #size-cells = <1>; + + /* MTD partition table. + * The ROM checks the first 512KiB + * for a valid file to boot(XIP). + */ + partition@0 { + label = "QSPI.U_BOOT"; + reg = <0x00000000 0x000080000>; + }; + partition@1 { + label = "QSPI.U_BOOT.backup"; + reg = <0x00080000 0x00080000>; + }; + partition@2 { + label = "QSPI.U-BOOT-SPL_OS"; + reg = <0x00100000 0x00010000>; + }; + partition@3 { + label = "QSPI.U_BOOT_ENV"; + reg = <0x00110000 0x00010000>; + }; + partition@4 { + label = "QSPI.U-BOOT-ENV.backup"; + reg = <0x00120000 0x00010000>; + }; + partition@5 { + label = "QSPI.KERNEL"; + reg = <0x00130000 0x0800000>; + }; + partition@6 { + label = "QSPI.FILESYSTEM"; + reg = <0x00930000 0x36D0000>; + }; + }; +}; + +&hdq { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&hdq_pins>; +}; diff --git a/arch/arm/boot/dts/am43xx-clocks.dtsi b/arch/arm/boot/dts/am43xx-clocks.dtsi index 142009cc9332..c7dc9dab93a4 100644 --- a/arch/arm/boot/dts/am43xx-clocks.dtsi +++ b/arch/arm/boot/dts/am43xx-clocks.dtsi @@ -11,6 +11,22 @@ sys_clkin_ck: sys_clkin_ck { #clock-cells = <0>; compatible = "ti,mux-clock"; + clocks = <&sysboot_freq_sel_ck>, <&crystal_freq_sel_ck>; + ti,bit-shift = <31>; + reg = <0x0040>; + }; + + crystal_freq_sel_ck: crystal_freq_sel_ck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>; + ti,bit-shift = <29>; + reg = <0x0040>; + }; + + sysboot_freq_sel_ck: sysboot_freq_sel_ck@44e10040 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>; ti,bit-shift = <22>; reg = <0x0040>; @@ -87,6 +103,54 @@ clock-mult = <1>; clock-div = <1>; }; + + ehrpwm0_tbclk: ehrpwm0_tbclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&dpll_per_m2_ck>; + ti,bit-shift = <0>; + reg = <0x0664>; + }; + + ehrpwm1_tbclk: ehrpwm1_tbclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&dpll_per_m2_ck>; + ti,bit-shift = <1>; + reg = <0x0664>; + }; + + ehrpwm2_tbclk: ehrpwm2_tbclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&dpll_per_m2_ck>; + ti,bit-shift = <2>; + reg = <0x0664>; + }; + + ehrpwm3_tbclk: ehrpwm3_tbclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&dpll_per_m2_ck>; + ti,bit-shift = <4>; + reg = <0x0664>; + }; + + ehrpwm4_tbclk: ehrpwm4_tbclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&dpll_per_m2_ck>; + ti,bit-shift = <5>; + reg = <0x0664>; + }; + + ehrpwm5_tbclk: ehrpwm5_tbclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&dpll_per_m2_ck>; + ti,bit-shift = <6>; + reg = <0x0664>; + }; }; &prcm_clocks { clk_32768_ck: clk_32768_ck { @@ -229,6 +293,7 @@ reg = <0x2e30>; ti,index-starts-at-one; ti,invert-autoidle-bit; + ti,set-rate-parent; }; dpll_per_ck: dpll_per_ck { @@ -511,6 +576,7 @@ compatible = "ti,mux-clock"; clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>; reg = <0x4244>; + ti,set-rate-parent; }; dpll_extdev_ck: dpll_extdev_ck { @@ -609,10 +675,13 @@ dpll_per_clkdcoldo: dpll_per_clkdcoldo { #clock-cells = <0>; - compatible = "fixed-factor-clock"; + compatible = "ti,fixed-factor-clock"; clocks = <&dpll_per_ck>; - clock-mult = <1>; - clock-div = <1>; + ti,clock-mult = <1>; + ti,clock-div = <1>; + ti,autoidle-shift = <8>; + reg = <0x2e14>; + ti,invert-autoidle-bit; }; dll_aging_clk_div: dll_aging_clk_div { @@ -653,4 +722,36 @@ clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>; reg = <0x4260>; }; + + usb_phy0_always_on_clk32k: usb_phy0_always_on_clk32k { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&usbphy_32khz_clkmux>; + ti,bit-shift = <8>; + reg = <0x2a40>; + }; + + usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&usbphy_32khz_clkmux>; + ti,bit-shift = <8>; + reg = <0x2a48>; + }; + + usb_otg_ss0_refclk960m: usb_otg_ss0_refclk960m { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&dpll_per_clkdcoldo>; + ti,bit-shift = <8>; + reg = <0x8a60>; + }; + + usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&dpll_per_clkdcoldo>; + ti,bit-shift = <8>; + reg = <0x8a68>; + }; }; diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts index 3383c4b66803..416f4e5a69c1 100644 --- a/arch/arm/boot/dts/armada-370-db.dts +++ b/arch/arm/boot/dts/armada-370-db.dts @@ -35,7 +35,6 @@ internal-regs { serial@12000 { - clock-frequency = <200000000>; status = "okay"; }; sata@a0000 { diff --git a/arch/arm/boot/dts/armada-370-mirabox.dts b/arch/arm/boot/dts/armada-370-mirabox.dts index 2354fe023ee0..097df7d8f0f6 100644 --- a/arch/arm/boot/dts/armada-370-mirabox.dts +++ b/arch/arm/boot/dts/armada-370-mirabox.dts @@ -47,7 +47,6 @@ internal-regs { serial@12000 { - clock-frequency = <200000000>; status = "okay"; }; timer@20300 { diff --git a/arch/arm/boot/dts/armada-370-netgear-rn102.dts b/arch/arm/boot/dts/armada-370-netgear-rn102.dts index 651aeb5ef439..d6d572e5af32 100644 --- a/arch/arm/boot/dts/armada-370-netgear-rn102.dts +++ b/arch/arm/boot/dts/armada-370-netgear-rn102.dts @@ -50,7 +50,6 @@ internal-regs { serial@12000 { - clock-frequency = <200000000>; status = "okay"; }; diff --git a/arch/arm/boot/dts/armada-370-netgear-rn104.dts b/arch/arm/boot/dts/armada-370-netgear-rn104.dts index 4e27587667bf..c5fe8b5dcdc7 100644 --- a/arch/arm/boot/dts/armada-370-netgear-rn104.dts +++ b/arch/arm/boot/dts/armada-370-netgear-rn104.dts @@ -50,7 +50,6 @@ internal-regs { serial@12000 { - clock-frequency = <200000000>; status = "okay"; }; diff --git a/arch/arm/boot/dts/armada-370-rd.dts b/arch/arm/boot/dts/armada-370-rd.dts index 3e2c857d6000..4169f4096ea3 100644 --- a/arch/arm/boot/dts/armada-370-rd.dts +++ b/arch/arm/boot/dts/armada-370-rd.dts @@ -51,7 +51,6 @@ internal-regs { serial@12000 { - clock-frequency = <200000000>; status = "okay"; }; sata@a0000 { diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi index bb77970c0b12..23227e0027ec 100644 --- a/arch/arm/boot/dts/armada-370-xp.dtsi +++ b/arch/arm/boot/dts/armada-370-xp.dtsi @@ -157,6 +157,7 @@ reg-shift = <2>; interrupts = <41>; reg-io-width = <1>; + clocks = <&coreclk 0>; status = "disabled"; }; serial@12100 { @@ -165,6 +166,7 @@ reg-shift = <2>; interrupts = <42>; reg-io-width = <1>; + clocks = <&coreclk 0>; status = "disabled"; }; @@ -203,6 +205,11 @@ reg = <0x20300 0x34>, <0x20704 0x4>; }; + pmsu@22000 { + compatible = "marvell,armada-370-pmsu"; + reg = <0x22000 0x1000>; + }; + usb@50000 { compatible = "marvell,orion-ehci"; reg = <0x50000 0x500>; diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi index af1f11e9e5a0..21b588b6f6bd 100644 --- a/arch/arm/boot/dts/armada-370.dtsi +++ b/arch/arm/boot/dts/armada-370.dtsi @@ -220,6 +220,11 @@ clocks = <&coreclk 2>; }; + cpurst@20800 { + compatible = "marvell,armada-370-cpu-reset"; + reg = <0x20800 0x8>; + }; + audio_controller: audio-controller@30000 { compatible = "marvell,armada370-audio"; reg = <0x30000 0x4000>; diff --git a/arch/arm/boot/dts/armada-375-db.dts b/arch/arm/boot/dts/armada-375-db.dts index 0451124e8ebf..772fec2d26ce 100644 --- a/arch/arm/boot/dts/armada-375-db.dts +++ b/arch/arm/boot/dts/armada-375-db.dts @@ -68,7 +68,6 @@ }; serial@12000 { - clock-frequency = <200000000>; status = "okay"; }; @@ -107,6 +106,14 @@ }; }; + usb@54000 { + status = "okay"; + }; + + usb3@58000 { + status = "okay"; + }; + mvsdio@d4000 { pinctrl-0 = <&sdio_pins &sdio_st_pins>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/armada-375.dtsi b/arch/arm/boot/dts/armada-375.dtsi index 3877693fb2d8..fb92551a1e71 100644 --- a/arch/arm/boot/dts/armada-375.dtsi +++ b/arch/arm/boot/dts/armada-375.dtsi @@ -39,6 +39,8 @@ cpus { #address-cells = <1>; #size-cells = <0>; + enable-method = "marvell,armada-375-smp"; + cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a9"; @@ -128,6 +130,11 @@ cache-level = <2>; }; + scu@c000 { + compatible = "arm,cortex-a9-scu"; + reg = <0xc000 0x58>; + }; + timer@c600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0xc600 0x20>; @@ -194,6 +201,7 @@ reg-shift = <2>; interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; reg-io-width = <1>; + clocks = <&coreclk 0>; status = "disabled"; }; @@ -203,6 +211,7 @@ reg-shift = <2>; interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; reg-io-width = <1>; + clocks = <&coreclk 0>; status = "disabled"; }; @@ -320,6 +329,46 @@ clocks = <&coreclk 0>; }; + watchdog@20300 { + compatible = "marvell,armada-375-wdt"; + reg = <0x20300 0x34>, <0x20704 0x4>, <0x18254 0x4>; + clocks = <&coreclk 0>; + }; + + cpurst@20800 { + compatible = "marvell,armada-370-cpu-reset"; + reg = <0x20800 0x10>; + }; + + coherency-fabric@21010 { + compatible = "marvell,armada-375-coherency-fabric"; + reg = <0x21010 0x1c>; + }; + + usb@50000 { + compatible = "marvell,orion-ehci"; + reg = <0x50000 0x500>; + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gateclk 18>; + status = "disabled"; + }; + + usb@54000 { + compatible = "marvell,orion-ehci"; + reg = <0x54000 0x500>; + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gateclk 26>; + status = "disabled"; + }; + + usb3@58000 { + compatible = "marvell,armada-375-xhci"; + reg = <0x58000 0x20000>,<0x5b880 0x80>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gateclk 16>; + status = "disabled"; + }; + xor@60800 { compatible = "marvell,orion-xor"; reg = <0x60800 0x100 @@ -391,6 +440,12 @@ status = "disabled"; }; + thermal@e8078 { + compatible = "marvell,armada375-thermal"; + reg = <0xe8078 0x4>, <0xe807c 0x8>; + status = "okay"; + }; + coreclk: mvebu-sar@e8204 { compatible = "marvell,armada-375-core-clock"; reg = <0xe8204 0x04>; diff --git a/arch/arm/boot/dts/armada-380.dtsi b/arch/arm/boot/dts/armada-380.dtsi index 6d0f03c98ee9..e69bc6759c39 100644 --- a/arch/arm/boot/dts/armada-380.dtsi +++ b/arch/arm/boot/dts/armada-380.dtsi @@ -21,6 +21,8 @@ cpus { #address-cells = <1>; #size-cells = <0>; + enable-method = "marvell,armada-380-smp"; + cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a9"; diff --git a/arch/arm/boot/dts/armada-385-db.dts b/arch/arm/boot/dts/armada-385-db.dts index 6828d77696a6..ff9637dd8d0f 100644 --- a/arch/arm/boot/dts/armada-385-db.dts +++ b/arch/arm/boot/dts/armada-385-db.dts @@ -55,7 +55,6 @@ }; serial@12000 { - clock-frequency = <200000000>; status = "okay"; }; @@ -65,6 +64,10 @@ phy-mode = "rgmii-id"; }; + usb@50000 { + status = "ok"; + }; + ethernet@70000 { status = "okay"; phy = <&phy0>; @@ -81,6 +84,14 @@ }; }; + sata@a8000 { + status = "okay"; + }; + + sata@e0000 { + status = "okay"; + }; + flash@d0000 { status = "okay"; num-cs = <1>; @@ -101,6 +112,22 @@ reg = <0x1000000 0x3f000000>; }; }; + + sdhci@d8000 { + clock-frequency = <200000000>; + broken-cd; + wp-inverted; + bus-width = <8>; + status = "okay"; + }; + + usb3@f0000 { + status = "okay"; + }; + + usb3@f8000 { + status = "okay"; + }; }; pcie-controller { diff --git a/arch/arm/boot/dts/armada-385-rd.dts b/arch/arm/boot/dts/armada-385-rd.dts index 45250c88814b..40893255a3f0 100644 --- a/arch/arm/boot/dts/armada-385-rd.dts +++ b/arch/arm/boot/dts/armada-385-rd.dts @@ -51,7 +51,6 @@ }; serial@12000 { - clock-frequency = <200000000>; status = "okay"; }; @@ -77,6 +76,10 @@ reg = <1>; }; }; + + usb3@f0000 { + status = "okay"; + }; }; pcie-controller { diff --git a/arch/arm/boot/dts/armada-385.dtsi b/arch/arm/boot/dts/armada-385.dtsi index da801964a257..f011009bf4cf 100644 --- a/arch/arm/boot/dts/armada-385.dtsi +++ b/arch/arm/boot/dts/armada-385.dtsi @@ -21,6 +21,8 @@ cpus { #address-cells = <1>; #size-cells = <0>; + enable-method = "marvell,armada-380-smp"; + cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a9"; diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi index ca8813bb99ba..3de364e81b52 100644 --- a/arch/arm/boot/dts/armada-38x.dtsi +++ b/arch/arm/boot/dts/armada-38x.dtsi @@ -108,6 +108,11 @@ cache-level = <2>; }; + scu@c000 { + compatible = "arm,cortex-a9-scu"; + reg = <0xc000 0x58>; + }; + timer@c600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0xc600 0x20>; @@ -174,6 +179,7 @@ reg-shift = <2>; interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; reg-io-width = <1>; + clocks = <&coreclk 0>; status = "disabled"; }; @@ -183,6 +189,7 @@ reg-shift = <2>; interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; reg-io-width = <1>; + clocks = <&coreclk 0>; status = "disabled"; }; @@ -267,6 +274,28 @@ clock-names = "nbclk", "fixed"; }; + watchdog@20300 { + compatible = "marvell,armada-380-wdt"; + reg = <0x20300 0x34>, <0x20704 0x4>, <0x18260 0x4>; + clocks = <&coreclk 2>, <&refclk>; + clock-names = "nbclk", "fixed"; + }; + + cpurst@20800 { + compatible = "marvell,armada-370-cpu-reset"; + reg = <0x20800 0x10>; + }; + + coherency-fabric@21010 { + compatible = "marvell,armada-380-coherency-fabric"; + reg = <0x21010 0x1c>; + }; + + pmsu@22000 { + compatible = "marvell,armada-380-pmsu"; + reg = <0x22000 0x1000>; + }; + eth1: ethernet@30000 { compatible = "marvell,armada-370-neta"; reg = <0x30000 0x4000>; @@ -283,6 +312,14 @@ status = "disabled"; }; + usb@50000 { + compatible = "marvell,orion-ehci"; + reg = <0x58000 0x500>; + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gateclk 18>; + status = "disabled"; + }; + xor@60800 { compatible = "marvell,orion-xor"; reg = <0x60800 0x100 @@ -339,6 +376,22 @@ clocks = <&gateclk 4>; }; + sata@a8000 { + compatible = "marvell,armada-380-ahci"; + reg = <0xa8000 0x2000>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gateclk 15>; + status = "disabled"; + }; + + sata@e0000 { + compatible = "marvell,armada-380-ahci"; + reg = <0xe0000 0x2000>; + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gateclk 30>; + status = "disabled"; + }; + coredivclk: clock@e4250 { compatible = "marvell,armada-380-corediv-clock"; reg = <0xe4250 0xc>; @@ -347,6 +400,12 @@ clock-output-names = "nand"; }; + thermal@e8078 { + compatible = "marvell,armada380-thermal"; + reg = <0xe4078 0x4>, <0xe4074 0x4>; + status = "okay"; + }; + flash@d0000 { compatible = "marvell,armada370-nand"; reg = <0xd0000 0x54>; @@ -356,6 +415,31 @@ clocks = <&coredivclk 0>; status = "disabled"; }; + + sdhci@d8000 { + compatible = "marvell,armada-380-sdhci"; + reg = <0xd8000 0x1000>, <0xdc000 0x100>; + interrupts = <0 25 0x4>; + clocks = <&gateclk 17>; + mrvl,clk-delay-cycles = <0x1F>; + status = "disabled"; + }; + + usb3@f0000 { + compatible = "marvell,armada-380-xhci"; + reg = <0xf0000 0x4000>,<0xf4000 0x4000>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gateclk 9>; + status = "disabled"; + }; + + usb3@f8000 { + compatible = "marvell,armada-380-xhci"; + reg = <0xf8000 0x4000>,<0xfc000 0x4000>; + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gateclk 10>; + status = "disabled"; + }; }; }; diff --git a/arch/arm/boot/dts/armada-xp-axpwifiap.dts b/arch/arm/boot/dts/armada-xp-axpwifiap.dts index d83d7d69ac01..a55a97a70505 100644 --- a/arch/arm/boot/dts/armada-xp-axpwifiap.dts +++ b/arch/arm/boot/dts/armada-xp-axpwifiap.dts @@ -95,12 +95,10 @@ }; serial@12000 { - clock-frequency = <250000000>; status = "okay"; }; serial@12100 { - clock-frequency = <250000000>; status = "okay"; }; diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts index 90f0bf6f9271..42ddb2864365 100644 --- a/arch/arm/boot/dts/armada-xp-db.dts +++ b/arch/arm/boot/dts/armada-xp-db.dts @@ -106,19 +106,15 @@ internal-regs { serial@12000 { - clock-frequency = <250000000>; status = "okay"; }; serial@12100 { - clock-frequency = <250000000>; status = "okay"; }; serial@12200 { - clock-frequency = <250000000>; status = "okay"; }; serial@12300 { - clock-frequency = <250000000>; status = "okay"; }; diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts index 0c756421ae6a..0478c55ca656 100644 --- a/arch/arm/boot/dts/armada-xp-gp.dts +++ b/arch/arm/boot/dts/armada-xp-gp.dts @@ -104,19 +104,15 @@ internal-regs { serial@12000 { - clock-frequency = <250000000>; status = "okay"; }; serial@12100 { - clock-frequency = <250000000>; status = "okay"; }; serial@12200 { - clock-frequency = <250000000>; status = "okay"; }; serial@12300 { - clock-frequency = <250000000>; status = "okay"; }; diff --git a/arch/arm/boot/dts/armada-xp-matrix.dts b/arch/arm/boot/dts/armada-xp-matrix.dts index c2242745b9b8..25674fe81f70 100644 --- a/arch/arm/boot/dts/armada-xp-matrix.dts +++ b/arch/arm/boot/dts/armada-xp-matrix.dts @@ -37,19 +37,15 @@ internal-regs { serial@12000 { - clock-frequency = <250000000>; status = "okay"; }; serial@12100 { - clock-frequency = <250000000>; status = "okay"; }; serial@12200 { - clock-frequency = <250000000>; status = "okay"; }; serial@12300 { - clock-frequency = <250000000>; status = "okay"; }; diff --git a/arch/arm/boot/dts/armada-xp-mv78230.dtsi b/arch/arm/boot/dts/armada-xp-mv78230.dtsi index 98335fb34b7a..1257ff1ed278 100644 --- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi +++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi @@ -27,6 +27,7 @@ cpus { #address-cells = <1>; #size-cells = <0>; + enable-method = "marvell,armada-xp-smp"; cpu@0 { device_type = "cpu"; diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi index 9480cf891f8c..3396b25b39e1 100644 --- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi +++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi @@ -29,6 +29,7 @@ cpus { #address-cells = <1>; #size-cells = <0>; + enable-method = "marvell,armada-xp-smp"; cpu@0 { device_type = "cpu"; diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi index 31ba6d8fbadf..6da84bf40aaf 100644 --- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi +++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi @@ -30,6 +30,7 @@ cpus { #address-cells = <1>; #size-cells = <0>; + enable-method = "marvell,armada-xp-smp"; cpu@0 { device_type = "cpu"; diff --git a/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts b/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts index ff049ee862eb..0cf999abc4ed 100644 --- a/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts +++ b/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts @@ -138,7 +138,6 @@ }; serial@12000 { - clocks = <&coreclk 0>; status = "okay"; }; diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts index 5d42feb31049..e5c6a0492ca0 100644 --- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts +++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts @@ -72,11 +72,9 @@ internal-regs { serial@12000 { - clock-frequency = <250000000>; status = "okay"; }; serial@12100 { - clock-frequency = <250000000>; status = "okay"; }; pinctrl { diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi index abb9f9dcc525..5902e8359c91 100644 --- a/arch/arm/boot/dts/armada-xp.dtsi +++ b/arch/arm/boot/dts/armada-xp.dtsi @@ -58,6 +58,7 @@ reg-shift = <2>; interrupts = <43>; reg-io-width = <1>; + clocks = <&coreclk 0>; status = "disabled"; }; serial@12300 { @@ -66,6 +67,7 @@ reg-shift = <2>; interrupts = <44>; reg-io-width = <1>; + clocks = <&coreclk 0>; status = "disabled"; }; @@ -117,9 +119,9 @@ clock-names = "nbclk", "fixed"; }; - armada-370-xp-pmsu@22000 { - compatible = "marvell,armada-370-xp-pmsu"; - reg = <0x22100 0x400>, <0x20800 0x20>; + cpurst@20800 { + compatible = "marvell,armada-370-cpu-reset"; + reg = <0x20800 0x20>; }; eth2: ethernet@30000 { diff --git a/arch/arm/boot/dts/at91-cosino_mega2560.dts b/arch/arm/boot/dts/at91-cosino_mega2560.dts index a542d5837a17..27ebb0f722fd 100644 --- a/arch/arm/boot/dts/at91-cosino_mega2560.dts +++ b/arch/arm/boot/dts/at91-cosino_mega2560.dts @@ -32,11 +32,6 @@ status = "okay"; }; - - tsadcc: tsadcc@f804c000 { - status = "okay"; - }; - rtc@fffffeb0 { status = "okay"; }; diff --git a/arch/arm/boot/dts/at91-sama5d3_xplained.dts b/arch/arm/boot/dts/at91-sama5d3_xplained.dts index 4537259ce529..5b8e40400bec 100644 --- a/arch/arm/boot/dts/at91-sama5d3_xplained.dts +++ b/arch/arm/boot/dts/at91-sama5d3_xplained.dts @@ -21,6 +21,14 @@ reg = <0x20000000 0x10000000>; }; + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <12000000>; + }; + ahb { apb { mmc0: mmc@f0000000 { @@ -43,11 +51,54 @@ }; i2c0: i2c@f0014000 { + pinctrl-0 = <&pinctrl_i2c0_pu>; status = "okay"; }; i2c1: i2c@f0018000 { status = "okay"; + + pmic: act8865@5b { + compatible = "active-semi,act8865"; + reg = <0x5b>; + status = "okay"; + + regulators { + vcc_1v8_reg: DCDC_REG1 { + regulator-name = "VCC_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vcc_1v2_reg: DCDC_REG2 { + regulator-name = "VCC_1V2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + vcc_3v3_reg: DCDC_REG3 { + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vddfuse_reg: LDO_REG1 { + regulator-name = "FUSE_2V5"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + }; + + vddana_reg: LDO_REG2 { + regulator-name = "VDDANA"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; }; macb0: ethernet@f0028000 { @@ -55,6 +106,12 @@ status = "okay"; }; + pwm0: pwm@f002c000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_pwmh0_0 &pinctrl_pwm0_pwmh1_0>; + status = "okay"; + }; + usart0: serial@f001c000 { status = "okay"; }; @@ -102,6 +159,7 @@ i2c2: i2c@f801c000 { dmas = <0>, <0>; /* Do not use DMA for i2c2 */ + pinctrl-0 = <&pinctrl_i2c2_pu>; status = "okay"; }; @@ -116,6 +174,18 @@ pinctrl@fffff200 { board { + pinctrl_i2c0_pu: i2c0_pu { + atmel,pins = + <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>, + <AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; + }; + + pinctrl_i2c2_pu: i2c2_pu { + atmel,pins = + <AT91_PIOA 18 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>, + <AT91_PIOA 19 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; + }; + pinctrl_mmc0_cd: mmc0_cd { atmel,pins = <AT91_PIOE 0 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; diff --git a/arch/arm/boot/dts/at91sam9261.dtsi b/arch/arm/boot/dts/at91sam9261.dtsi index 3be973e9889a..b309c1c6e848 100644 --- a/arch/arm/boot/dts/at91sam9261.dtsi +++ b/arch/arm/boot/dts/at91sam9261.dtsi @@ -29,6 +29,7 @@ i2c0 = &i2c0; ssc0 = &ssc0; ssc1 = &ssc1; + ssc2 = &ssc2; }; cpus { @@ -45,6 +46,18 @@ reg = <0x20000000 0x08000000>; }; + main_xtal: main_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + slow_xtal: slow_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + ahb { compatible = "simple-bus"; #address-cells = <1>; @@ -182,6 +195,8 @@ interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; + clocks = <&ssc0_clk>; + clock-names = "pclk"; status = "disabled"; }; @@ -191,6 +206,19 @@ interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; + clocks = <&ssc1_clk>; + clock-names = "pclk"; + status = "disabled"; + }; + + ssc2: ssc@fffc4000 { + compatible = "atmel,at91rm9200-ssc"; + reg = <0xfffc4000 0x4000>; + interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ssc2_tx &pinctrl_ssc2_rx>; + clocks = <&ssc2_clk>; + clock-names = "pclk"; status = "disabled"; }; @@ -385,6 +413,22 @@ }; }; + ssc2 { + pinctrl_ssc2_tx: ssc2_tx-0 { + atmel,pins = + <AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE>, + <AT91_PIOC 26 AT91_PERIPH_B AT91_PINCTRL_NONE>, + <AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + + pinctrl_ssc2_rx: ssc2_rx-0 { + atmel,pins = + <AT91_PIOC 28 AT91_PERIPH_B AT91_PINCTRL_NONE>, + <AT91_PIOC 29 AT91_PERIPH_B AT91_PINCTRL_NONE>, + <AT91_PIOC 30 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + }; + spi0 { pinctrl_spi0: spi0-0 { atmel,pins = @@ -524,17 +568,24 @@ #size-cells = <0>; #interrupt-cells = <1>; - clk32k: slck { + slow_rc_osc: slow_rc_osc { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32768>; + clock-accuracy = <50000000>; + }; + + clk32k: slck { + compatible = "atmel,at91sam9260-clk-slow"; + #clock-cells = <0>; + clocks = <&slow_rc_osc &slow_xtal>; }; main: mainck { compatible = "atmel,at91rm9200-clk-main"; #clock-cells = <0>; interrupts-extended = <&pmc AT91_PMC_MOSCS>; - clocks = <&clk32k>; + clocks = <&main_xtal>; }; plla: pllack { @@ -545,7 +596,8 @@ reg = <0>; atmel,clk-input-range = <1000000 32000000>; #atmel,pll-clk-output-range-cells = <4>; - atmel,pll-clk-output-ranges = <80000000 200000000 190000000 240000000>; + atmel,pll-clk-output-ranges = <80000000 200000000 0 1>, + <190000000 240000000 2 1>; }; pllb: pllbck { @@ -554,9 +606,9 @@ interrupts-extended = <&pmc AT91_PMC_LOCKB>; clocks = <&main>; reg = <1>; - atmel,clk-input-range = <1000000 32000000>; + atmel,clk-input-range = <1000000 5000000>; #atmel,pll-clk-output-range-cells = <4>; - atmel,pll-clk-output-ranges = <80000000 200000000 190000000 240000000>; + atmel,pll-clk-output-ranges = <70000000 130000000 1 1>; }; mck: masterck { @@ -565,16 +617,48 @@ interrupts-extended = <&pmc AT91_PMC_MCKRDY>; clocks = <&clk32k>, <&main>, <&plla>, <&pllb>; atmel,clk-output-range = <0 94000000>; - atmel,clk-divisors = <1 2 4 3>; + atmel,clk-divisors = <1 2 4 0>; }; usb: usbck { compatible = "atmel,at91rm9200-clk-usb"; #clock-cells = <0>; - atmel,clk-divisors = <1 2 4 3>; + atmel,clk-divisors = <1 2 4 0>; clocks = <&pllb>; }; + prog: progck { + compatible = "atmel,at91rm9200-clk-programmable"; + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&pmc>; + clocks = <&clk32k>, <&main>, <&plla>, <&pllb>; + + prog0: prog0 { + #clock-cells = <0>; + reg = <0>; + interrupts = <AT91_PMC_PCKRDY(0)>; + }; + + prog1: prog1 { + #clock-cells = <0>; + reg = <1>; + interrupts = <AT91_PMC_PCKRDY(1)>; + }; + + prog2: prog2 { + #clock-cells = <0>; + reg = <2>; + interrupts = <AT91_PMC_PCKRDY(2)>; + }; + + prog3: prog3 { + #clock-cells = <0>; + reg = <3>; + interrupts = <AT91_PMC_PCKRDY(3)>; + }; + }; + systemck { compatible = "atmel,at91rm9200-clk-system"; #address-cells = <1>; @@ -592,6 +676,30 @@ clocks = <&usb>; }; + pck0: pck0 { + #clock-cells = <0>; + reg = <8>; + clocks = <&prog0>; + }; + + pck1: pck1 { + #clock-cells = <0>; + reg = <9>; + clocks = <&prog1>; + }; + + pck2: pck2 { + #clock-cells = <0>; + reg = <10>; + clocks = <&prog2>; + }; + + pck3: pck3 { + #clock-cells = <0>; + reg = <11>; + clocks = <&prog3>; + }; + hclk0: hclk0 { #clock-cells = <0>; reg = <16>; @@ -666,6 +774,21 @@ reg = <13>; }; + ssc0_clk: ssc0_clk { + #clock-cells = <0>; + reg = <14>; + }; + + ssc1_clk: ssc1_clk { + #clock-cells = <0>; + reg = <15>; + }; + + ssc2_clk: ssc2_clk { + #clock-cells = <0>; + reg = <16>; + }; + tc0_clk: tc0_clk { #clock-cells = <0>; reg = <17>; diff --git a/arch/arm/boot/dts/at91sam9261ek.dts b/arch/arm/boot/dts/at91sam9261ek.dts index 2ce527e70c7a..c6683ea8b743 100644 --- a/arch/arm/boot/dts/at91sam9261ek.dts +++ b/arch/arm/boot/dts/at91sam9261ek.dts @@ -20,6 +20,10 @@ reg = <0x20000000 0x4000000>; }; + main_xtal { + clock-frequency = <18432000>; + }; + clocks { #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi index 9cdaecff13b3..ace6bf197b70 100644 --- a/arch/arm/boot/dts/at91sam9g45.dtsi +++ b/arch/arm/boot/dts/at91sam9g45.dtsi @@ -136,6 +136,36 @@ >; /* shared pinctrl settings */ + adc0 { + pinctrl_adc0_adtrg: adc0_adtrg { + atmel,pins = <AT91_PIOD 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + pinctrl_adc0_ad0: adc0_ad0 { + atmel,pins = <AT91_PIOD 20 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; + }; + pinctrl_adc0_ad1: adc0_ad1 { + atmel,pins = <AT91_PIOD 21 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; + }; + pinctrl_adc0_ad2: adc0_ad2 { + atmel,pins = <AT91_PIOD 22 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; + }; + pinctrl_adc0_ad3: adc0_ad3 { + atmel,pins = <AT91_PIOD 23 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; + }; + pinctrl_adc0_ad4: adc0_ad4 { + atmel,pins = <AT91_PIOD 24 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; + }; + pinctrl_adc0_ad5: adc0_ad5 { + atmel,pins = <AT91_PIOD 25 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; + }; + pinctrl_adc0_ad6: adc0_ad6 { + atmel,pins = <AT91_PIOD 26 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; + }; + pinctrl_adc0_ad7: adc0_ad7 { + atmel,pins = <AT91_PIOD 27 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; + }; + }; + dbgu { pinctrl_dbgu: dbgu-0 { atmel,pins = @@ -634,10 +664,9 @@ adc0: adc@fffb0000 { #address-cells = <1>; #size-cells = <0>; - compatible = "atmel,at91sam9260-adc"; + compatible = "atmel,at91sam9g45-adc"; reg = <0xfffb0000 0x100>; interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; - atmel,adc-use-external-triggers; atmel,adc-channels-used = <0xff>; atmel,adc-vref = <3300>; atmel,adc-startup-time = <40>; diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts index 7ff665a8c708..9f5b0a674995 100644 --- a/arch/arm/boot/dts/at91sam9m10g45ek.dts +++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts @@ -8,6 +8,7 @@ */ /dts-v1/; #include "at91sam9g45.dtsi" +#include <dt-bindings/pwm/pwm.h> / { model = "Atmel AT91SAM9M10G45-EK"; @@ -130,6 +131,21 @@ status = "okay"; }; + adc0: adc@fffb0000 { + pinctrl-names = "default"; + pinctrl-0 = < + &pinctrl_adc0_ad0 + &pinctrl_adc0_ad1 + &pinctrl_adc0_ad2 + &pinctrl_adc0_ad3 + &pinctrl_adc0_ad4 + &pinctrl_adc0_ad5 + &pinctrl_adc0_ad6 + &pinctrl_adc0_ad7>; + atmel,adc-ts-wires = <4>; + status = "okay"; + }; + pwm0: pwm@fffb8000 { status = "okay"; @@ -216,14 +232,14 @@ d6 { label = "d6"; - pwms = <&pwm0 3 5000 0>; + pwms = <&pwm0 3 5000 PWM_POLARITY_INVERTED>; max-brightness = <255>; linux,default-trigger = "nand-disk"; }; d7 { label = "d7"; - pwms = <&pwm0 1 5000 0>; + pwms = <&pwm0 1 5000 PWM_POLARITY_INVERTED>; max-brightness = <255>; linux,default-trigger = "mmc0"; }; diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi index 9f04808fc697..d1b82e6635d5 100644 --- a/arch/arm/boot/dts/at91sam9n12.dtsi +++ b/arch/arm/boot/dts/at91sam9n12.dtsi @@ -12,6 +12,7 @@ #include <dt-bindings/pinctrl/at91.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/clock/at91.h> / { model = "Atmel AT91SAM9N12 SoC"; @@ -49,6 +50,18 @@ reg = <0x20000000 0x10000000>; }; + slow_xtal: slow_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + main_xtal: main_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + ahb { compatible = "simple-bus"; #address-cells = <1>; @@ -75,8 +88,280 @@ }; pmc: pmc@fffffc00 { - compatible = "atmel,at91rm9200-pmc"; - reg = <0xfffffc00 0x100>; + compatible = "atmel,at91sam9n12-pmc"; + reg = <0xfffffc00 0x200>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + interrupt-controller; + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + main_rc_osc: main_rc_osc { + compatible = "atmel,at91sam9x5-clk-main-rc-osc"; + #clock-cells = <0>; + interrupts-extended = <&pmc AT91_PMC_MOSCRCS>; + clock-frequency = <12000000>; + clock-accuracy = <50000000>; + }; + + main_osc: main_osc { + compatible = "atmel,at91rm9200-clk-main-osc"; + #clock-cells = <0>; + interrupts-extended = <&pmc AT91_PMC_MOSCS>; + clocks = <&main_xtal>; + }; + + main: mainck { + compatible = "atmel,at91sam9x5-clk-main"; + #clock-cells = <0>; + interrupts-extended = <&pmc AT91_PMC_MOSCSELS>; + clocks = <&main_rc_osc>, <&main_osc>; + }; + + plla: pllack { + compatible = "atmel,at91rm9200-clk-pll"; + #clock-cells = <0>; + interrupts-extended = <&pmc AT91_PMC_LOCKA>; + clocks = <&main>; + reg = <0>; + atmel,clk-input-range = <2000000 32000000>; + #atmel,pll-clk-output-range-cells = <4>; + atmel,pll-clk-output-ranges = <745000000 800000000 0 0>, + <695000000 750000000 1 0>, + <645000000 700000000 2 0>, + <595000000 650000000 3 0>, + <545000000 600000000 0 1>, + <495000000 555000000 1 1>, + <445000000 500000000 1 2>, + <400000000 450000000 1 3>; + }; + + plladiv: plladivck { + compatible = "atmel,at91sam9x5-clk-plldiv"; + #clock-cells = <0>; + clocks = <&plla>; + }; + + pllb: pllbck { + compatible = "atmel,at91rm9200-clk-pll"; + #clock-cells = <0>; + interrupts-extended = <&pmc AT91_PMC_LOCKB>; + clocks = <&main>; + reg = <1>; + atmel,clk-input-range = <2000000 32000000>; + #atmel,pll-clk-output-range-cells = <3>; + atmel,pll-clk-output-ranges = <30000000 100000000 0>; + }; + + mck: masterck { + compatible = "atmel,at91sam9x5-clk-master"; + #clock-cells = <0>; + interrupts-extended = <&pmc AT91_PMC_MCKRDY>; + clocks = <&clk32k>, <&main>, <&plladiv>, <&pllb>; + atmel,clk-output-range = <0 133333333>; + atmel,clk-divisors = <1 2 4 3>; + atmel,master-clk-have-div3-pres; + }; + + usb: usbck { + compatible = "atmel,at91sam9n12-clk-usb"; + #clock-cells = <0>; + clocks = <&pllb>; + }; + + prog: progck { + compatible = "atmel,at91sam9x5-clk-programmable"; + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&pmc>; + clocks = <&clk32k>, <&main>, <&plladiv>, <&pllb>, <&mck>; + + prog0: prog0 { + #clock-cells = <0>; + reg = <0>; + interrupts = <AT91_PMC_PCKRDY(0)>; + }; + + prog1: prog1 { + #clock-cells = <0>; + reg = <1>; + interrupts = <AT91_PMC_PCKRDY(1)>; + }; + }; + + systemck { + compatible = "atmel,at91rm9200-clk-system"; + #address-cells = <1>; + #size-cells = <0>; + + ddrck: ddrck { + #clock-cells = <0>; + reg = <2>; + clocks = <&mck>; + }; + + lcdck: lcdck { + #clock-cells = <0>; + reg = <3>; + clocks = <&mck>; + }; + + uhpck: uhpck { + #clock-cells = <0>; + reg = <6>; + clocks = <&usb>; + }; + + udpck: udpck { + #clock-cells = <0>; + reg = <7>; + clocks = <&usb>; + }; + + pck0: pck0 { + #clock-cells = <0>; + reg = <8>; + clocks = <&prog0>; + }; + + pck1: pck1 { + #clock-cells = <0>; + reg = <9>; + clocks = <&prog1>; + }; + }; + + periphck { + compatible = "atmel,at91sam9x5-clk-peripheral"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&mck>; + + pioAB_clk: pioAB_clk { + #clock-cells = <0>; + reg = <2>; + }; + + pioCD_clk: pioCD_clk { + #clock-cells = <0>; + reg = <3>; + }; + + fuse_clk: fuse_clk { + #clock-cells = <0>; + reg = <4>; + }; + + usart0_clk: usart0_clk { + #clock-cells = <0>; + reg = <5>; + }; + + usart1_clk: usart1_clk { + #clock-cells = <0>; + reg = <6>; + }; + + usart2_clk: usart2_clk { + #clock-cells = <0>; + reg = <7>; + }; + + usart3_clk: usart3_clk { + #clock-cells = <0>; + reg = <8>; + }; + + twi0_clk: twi0_clk { + reg = <9>; + #clock-cells = <0>; + }; + + twi1_clk: twi1_clk { + #clock-cells = <0>; + reg = <10>; + }; + + mci0_clk: mci0_clk { + #clock-cells = <0>; + reg = <12>; + }; + + spi0_clk: spi0_clk { + #clock-cells = <0>; + reg = <13>; + }; + + spi1_clk: spi1_clk { + #clock-cells = <0>; + reg = <14>; + }; + + uart0_clk: uart0_clk { + #clock-cells = <0>; + reg = <15>; + }; + + uart1_clk: uart1_clk { + #clock-cells = <0>; + reg = <16>; + }; + + tcb_clk: tcb_clk { + #clock-cells = <0>; + reg = <17>; + }; + + pwm_clk: pwm_clk { + #clock-cells = <0>; + reg = <18>; + }; + + adc_clk: adc_clk { + #clock-cells = <0>; + reg = <19>; + }; + + dma0_clk: dma0_clk { + #clock-cells = <0>; + reg = <20>; + }; + + uhphs_clk: uhphs_clk { + #clock-cells = <0>; + reg = <22>; + }; + + udphs_clk: udphs_clk { + #clock-cells = <0>; + reg = <23>; + }; + + lcdc_clk: lcdc_clk { + #clock-cells = <0>; + reg = <25>; + }; + + sha_clk: sha_clk { + #clock-cells = <0>; + reg = <27>; + }; + + ssc0_clk: ssc0_clk { + #clock-cells = <0>; + reg = <28>; + }; + + aes_clk: aes_clk { + #clock-cells = <0>; + reg = <29>; + }; + + trng_clk: trng_clk { + #clock-cells = <0>; + reg = <30>; + }; + }; }; rstc@fffffe00 { @@ -88,6 +373,7 @@ compatible = "atmel,at91sam9260-pit"; reg = <0xfffffe30 0xf>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&mck>; }; shdwc@fffffe10 { @@ -95,12 +381,38 @@ reg = <0xfffffe10 0x10>; }; + sckc@fffffe50 { + compatible = "atmel,at91sam9x5-sckc"; + reg = <0xfffffe50 0x4>; + + slow_osc: slow_osc { + compatible = "atmel,at91sam9x5-clk-slow-osc"; + #clock-cells = <0>; + clocks = <&slow_xtal>; + }; + + slow_rc_osc: slow_rc_osc { + compatible = "atmel,at91sam9x5-clk-slow-rc-osc"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-accuracy = <50000000>; + }; + + clk32k: slck { + compatible = "atmel,at91sam9x5-clk-slow"; + #clock-cells = <0>; + clocks = <&slow_rc_osc>, <&slow_osc>; + }; + }; + mmc0: mmc@f0008000 { compatible = "atmel,hsmci"; reg = <0xf0008000 0x600>; interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; dmas = <&dma 1 AT91_DMA_CFG_PER_ID(0)>; dma-names = "rxtx"; + clocks = <&mci0_clk>; + clock-names = "mci_clk"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -110,12 +422,16 @@ compatible = "atmel,at91sam9x5-tcb"; reg = <0xf8008000 0x100>; interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&tcb_clk>; + clock-names = "t0_clk"; }; tcb1: timer@f800c000 { compatible = "atmel,at91sam9x5-tcb"; reg = <0xf800c000 0x100>; interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&tcb_clk>; + clock-names = "t0_clk"; }; dma: dma-controller@ffffec00 { @@ -123,6 +439,8 @@ reg = <0xffffec00 0x200>; interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; #dma-cells = <2>; + clocks = <&dma0_clk>; + clock-names = "dma_clk"; }; pinctrl@fffff400 { @@ -392,6 +710,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; + clocks = <&pioAB_clk>; }; pioB: gpio@fffff600 { @@ -402,6 +721,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; + clocks = <&pioAB_clk>; }; pioC: gpio@fffff800 { @@ -412,6 +732,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; + clocks = <&pioCD_clk>; }; pioD: gpio@fffffa00 { @@ -422,6 +743,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; + clocks = <&pioCD_clk>; }; }; @@ -431,6 +753,8 @@ interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_dbgu>; + clocks = <&mck>; + clock-names = "usart"; status = "disabled"; }; @@ -443,6 +767,8 @@ dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; + clocks = <&ssc0_clk>; + clock-names = "pclk"; status = "disabled"; }; @@ -452,6 +778,8 @@ interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart0>; + clocks = <&usart0_clk>; + clock-names = "usart"; status = "disabled"; }; @@ -461,6 +789,8 @@ interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart1>; + clocks = <&usart1_clk>; + clock-names = "usart"; status = "disabled"; }; @@ -470,6 +800,8 @@ interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart2>; + clocks = <&usart2_clk>; + clock-names = "usart"; status = "disabled"; }; @@ -479,6 +811,8 @@ interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart3>; + clocks = <&usart3_clk>; + clock-names = "usart"; status = "disabled"; }; @@ -493,6 +827,7 @@ #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c0>; + clocks = <&twi0_clk>; status = "disabled"; }; @@ -507,6 +842,7 @@ #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c1>; + clocks = <&twi1_clk>; status = "disabled"; }; @@ -521,6 +857,8 @@ dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0>; + clocks = <&spi0_clk>; + clock-names = "spi_clk"; status = "disabled"; }; @@ -535,6 +873,8 @@ dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi1>; + clocks = <&spi1_clk>; + clock-names = "spi_clk"; status = "disabled"; }; @@ -554,6 +894,7 @@ reg = <0xf8034000 0x300>; interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>; #pwm-cells = <3>; + clocks = <&pwm_clk>; status = "disabled"; }; }; @@ -584,6 +925,9 @@ compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00500000 0x00100000>; interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; + clocks = <&usb>, <&uhphs_clk>, <&udphs_clk>, + <&uhpck>; + clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck"; status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/at91sam9n12ek.dts b/arch/arm/boot/dts/at91sam9n12ek.dts index 924a6a6ffd0f..64bbe46e4f90 100644 --- a/arch/arm/boot/dts/at91sam9n12ek.dts +++ b/arch/arm/boot/dts/at91sam9n12ek.dts @@ -21,6 +21,14 @@ reg = <0x20000000 0x8000000>; }; + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <16000000>; + }; + clocks { #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/at91sam9rl.dtsi b/arch/arm/boot/dts/at91sam9rl.dtsi index 92a52faebef7..1da183155eee 100644 --- a/arch/arm/boot/dts/at91sam9rl.dtsi +++ b/arch/arm/boot/dts/at91sam9rl.dtsi @@ -11,6 +11,7 @@ #include <dt-bindings/clock/at91.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pwm/pwm.h> / { model = "Atmel AT91SAM9RL family SoC"; @@ -32,6 +33,7 @@ i2c1 = &i2c1; ssc0 = &ssc0; ssc1 = &ssc1; + pwm0 = &pwm0; }; cpus { @@ -48,12 +50,43 @@ reg = <0x20000000 0x04000000>; }; + slow_xtal: slow_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + main_xtal: main_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + clocks { + adc_op_clk: adc_op_clk{ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1000000>; + }; + }; + ahb { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges; + fb0: fb@00500000 { + compatible = "atmel,at91sam9rl-lcdc"; + reg = <0x00500000 0x1000>; + interrupts = <23 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fb>; + clocks = <&lcd_clk>, <&lcd_clk>; + clock-names = "hclk", "lcdc_clk"; + status = "disabled"; + }; + nand0: nand@40000000 { compatible = "atmel,at91rm9200-nand"; #address-cells = <1>; @@ -187,6 +220,16 @@ status = "disabled"; }; + pwm0: pwm@fffc8000 { + compatible = "atmel,at91sam9rl-pwm"; + reg = <0xfffc8000 0x300>; + interrupts = <19 IRQ_TYPE_LEVEL_HIGH 4>; + #pwm-cells = <3>; + clocks = <&pwm_clk>; + clock-names = "pwm_clk"; + status = "disabled"; + }; + spi0: spi@fffcc000 { #address-cells = <1>; #size-cells = <0>; @@ -200,6 +243,111 @@ status = "disabled"; }; + adc0: adc@fffd0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "atmel,at91sam9rl-adc"; + reg = <0xfffd0000 0x100>; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&adc_clk>, <&adc_op_clk>; + clock-names = "adc_clk", "adc_op_clk"; + atmel,adc-use-external-triggers; + atmel,adc-channels-used = <0x3f>; + atmel,adc-vref = <3300>; + atmel,adc-startup-time = <40>; + atmel,adc-res = <8 10>; + atmel,adc-res-names = "lowres", "highres"; + atmel,adc-use-res = "highres"; + + trigger@0 { + reg = <0>; + trigger-name = "timer-counter-0"; + trigger-value = <0x1>; + }; + trigger@1 { + reg = <1>; + trigger-name = "timer-counter-1"; + trigger-value = <0x3>; + }; + + trigger@2 { + reg = <2>; + trigger-name = "timer-counter-2"; + trigger-value = <0x5>; + }; + + trigger@3 { + reg = <3>; + trigger-name = "external"; + trigger-value = <0x13>; + trigger-external; + }; + }; + + usb0: gadget@fffd4000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "atmel,at91sam9rl-udc"; + reg = <0x00600000 0x100000>, + <0xfffd4000 0x4000>; + interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; + clocks = <&udphs_clk>, <&utmi>; + clock-names = "pclk", "hclk"; + status = "disabled"; + + ep0 { + reg = <0>; + atmel,fifo-size = <64>; + atmel,nb-banks = <1>; + }; + + ep1 { + reg = <1>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + atmel,can-dma; + atmel,can-isoc; + }; + + ep2 { + reg = <2>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + atmel,can-dma; + atmel,can-isoc; + }; + + ep3 { + reg = <3>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <3>; + atmel,can-dma; + }; + + ep4 { + reg = <4>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <3>; + atmel,can-dma; + }; + + ep5 { + reg = <5>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <3>; + atmel,can-dma; + atmel,can-isoc; + }; + + ep6 { + reg = <6>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <3>; + atmel,can-dma; + atmel,can-isoc; + }; + }; + ramc0: ramc@ffffea00 { compatible = "atmel,at91sam9260-sdramc"; reg = <0xffffea00 0x200>; @@ -238,6 +386,44 @@ <0x003fffff 0x0001ff3c>; /* pioD */ /* shared pinctrl settings */ + adc0 { + pinctrl_adc0_ts: adc0_ts-0 { + atmel,pins = + <AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE>, + <AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE>, + <AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE>, + <AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + + pinctrl_adc0_ad0: adc0_ad0-0 { + atmel,pins = <AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + + pinctrl_adc0_ad1: adc0_ad1-0 { + atmel,pins = <AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + + pinctrl_adc0_ad2: adc0_ad2-0 { + atmel,pins = <AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + + pinctrl_adc0_ad3: adc0_ad3-0 { + atmel,pins = <AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + + pinctrl_adc0_ad4: adc0_ad4-0 { + atmel,pins = <AT91_PIOD 6 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + + pinctrl_adc0_ad5: adc0_ad5-0 { + atmel,pins = <AT91_PIOD 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + + pinctrl_adc0_adtrg: adc0_adtrg-0 { + atmel,pins = <AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + }; + dbgu { pinctrl_dbgu: dbgu-0 { atmel,pins = @@ -246,6 +432,33 @@ }; }; + fb { + pinctrl_fb: fb-0 { + atmel,pins = + <AT91_PIOC 1 AT91_PERIPH_B AT91_PINCTRL_NONE>, + <AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE>, + <AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE>, + <AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE>, + <AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE>, + <AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_NONE>, + <AT91_PIOC 10 AT91_PERIPH_B AT91_PINCTRL_NONE>, + <AT91_PIOC 11 AT91_PERIPH_B AT91_PINCTRL_NONE>, + <AT91_PIOC 12 AT91_PERIPH_B AT91_PINCTRL_NONE>, + <AT91_PIOC 13 AT91_PERIPH_B AT91_PINCTRL_NONE>, + <AT91_PIOC 15 AT91_PERIPH_B AT91_PINCTRL_NONE>, + <AT91_PIOC 16 AT91_PERIPH_B AT91_PINCTRL_NONE>, + <AT91_PIOC 17 AT91_PERIPH_B AT91_PINCTRL_NONE>, + <AT91_PIOC 18 AT91_PERIPH_B AT91_PINCTRL_NONE>, + <AT91_PIOC 19 AT91_PERIPH_B AT91_PINCTRL_NONE>, + <AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE>, + <AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE>, + <AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE>, + <AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE>, + <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE>, + <AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + }; + i2c_gpio0 { pinctrl_i2c_gpio0: i2c_gpio0-0 { atmel,pins = @@ -307,6 +520,61 @@ }; }; + pwm0 { + pinctrl_pwm0_pwm0_0: pwm0_pwm0-0 { + atmel,pins = <AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + + pinctrl_pwm0_pwm0_1: pwm0_pwm0-1 { + atmel,pins = <AT91_PIOC 2 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + + pinctrl_pwm0_pwm0_2: pwm0_pwm0-2 { + atmel,pins = <AT91_PIOD 14 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + + pinctrl_pwm0_pwm1_0: pwm0_pwm1-0 { + atmel,pins = <AT91_PIOB 9 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + + pinctrl_pwm0_pwm1_1: pwm0_pwm1-1 { + atmel,pins = <AT91_PIOC 3 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + + pinctrl_pwm0_pwm1_2: pwm0_pwm1-2 { + atmel,pins = <AT91_PIOD 15 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + + pinctrl_pwm0_pwm2_0: pwm0_pwm2-0 { + atmel,pins = <AT91_PIOD 5 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + + pinctrl_pwm0_pwm2_1: pwm0_pwm2-1 { + atmel,pins = <AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + + pinctrl_pwm0_pwm2_2: pwm0_pwm2-2 { + atmel,pins = <AT91_PIOD 16 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + + pinctrl_pwm0_pwm3_0: pwm0_pwm3-0 { + atmel,pins = <AT91_PIOD 8 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + + pinctrl_pwm0_pwm3_1: pwm0_pwm3-1 { + atmel,pins = <AT91_PIOD 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + }; + + spi0 { + pinctrl_spi0: spi0-0 { + atmel,pins = + <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE>, + <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE>, + <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + }; + ssc0 { pinctrl_ssc0_tx: ssc0_tx-0 { atmel,pins = @@ -339,15 +607,6 @@ }; }; - spi0 { - pinctrl_spi0: spi0-0 { - atmel,pins = - <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE>, - <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE>, - <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; - }; - }; - tcb0 { pinctrl_tcb0_tclk0: tcb0_tclk0-0 { atmel,pins = <AT91_PIOA 3 AT91_PERIPH_B AT91_PINCTRL_NONE>; @@ -548,17 +807,11 @@ #size-cells = <0>; #interrupt-cells = <1>; - clk32k: slck { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - main: mainck { compatible = "atmel,at91rm9200-clk-main"; #clock-cells = <0>; interrupts-extended = <&pmc AT91_PMC_MOSCS>; - clocks = <&clk32k>; + clocks = <&main_xtal>; }; plla: pllack { @@ -568,8 +821,9 @@ clocks = <&main>; reg = <0>; atmel,clk-input-range = <1000000 32000000>; - #atmel,pll-clk-output-range-cells = <4>; - atmel,pll-clk-output-ranges = <80000000 200000000 190000000 240000000>; + #atmel,pll-clk-output-range-cells = <3>; + atmel,pll-clk-output-ranges = <80000000 200000000 0>, + <190000000 240000000 2>; }; utmi: utmick { @@ -586,7 +840,7 @@ interrupts-extended = <&pmc AT91_PMC_MCKRDY>; clocks = <&clk32k>, <&main>, <&plla>, <&utmi>; atmel,clk-output-range = <0 94000000>; - atmel,clk-divisors = <1 2 4 3>; + atmel,clk-divisors = <1 2 4 0>; }; prog: progck { @@ -769,6 +1023,32 @@ interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; status = "disabled"; }; + + sckc@fffffd50 { + compatible = "atmel,at91sam9x5-sckc"; + reg = <0xfffffd50 0x4>; + + slow_osc: slow_osc { + compatible = "atmel,at91sam9x5-clk-slow-osc"; + #clock-cells = <0>; + atmel,startup-time-usec = <1200000>; + clocks = <&slow_xtal>; + }; + + slow_rc_osc: slow_rc_osc { + compatible = "atmel,at91sam9x5-clk-slow-rc-osc"; + #clock-cells = <0>; + atmel,startup-time-usec = <75>; + clock-frequency = <32768>; + clock-accuracy = <50000000>; + }; + + clk32k: slck { + compatible = "atmel,at91sam9x5-clk-slow"; + #clock-cells = <0>; + clocks = <&slow_rc_osc &slow_osc>; + }; + }; }; }; diff --git a/arch/arm/boot/dts/at91sam9rlek.dts b/arch/arm/boot/dts/at91sam9rlek.dts index cddb37825fad..d4a010e40fe3 100644 --- a/arch/arm/boot/dts/at91sam9rlek.dts +++ b/arch/arm/boot/dts/at91sam9rlek.dts @@ -20,6 +20,15 @@ reg = <0x20000000 0x4000000>; }; + + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <12000000>; + }; + clocks { #address-cells = <1>; #size-cells = <1>; @@ -32,6 +41,37 @@ }; ahb { + fb0: fb@00500000 { + display = <&display0>; + status = "okay"; + + display0: display { + bits-per-pixel = <16>; + atmel,lcdcon-backlight; + atmel,dmacon = <0x1>; + atmel,lcdcon2 = <0x80008002>; + atmel,guard-time = <1>; + atmel,lcd-wiring-mode = "RGB"; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <4965000>; + hactive = <240>; + vactive = <320>; + hback-porch = <1>; + hfront-porch = <33>; + vback-porch = <1>; + vfront-porch = <0>; + hsync-len = <5>; + vsync-len = <1>; + hsync-active = <1>; + vsync-active = <1>; + }; + }; + }; + }; + nand0: nand@40000000 { nand-bus-width = <8>; nand-ecc-mode = "soft"; @@ -92,6 +132,43 @@ status = "okay"; }; + adc0: adc@fffd0000 { + pinctrl-names = "default"; + pinctrl-0 = < + &pinctrl_adc0_ad0 + &pinctrl_adc0_ad1 + &pinctrl_adc0_ad2 + &pinctrl_adc0_ad3 + &pinctrl_adc0_ad4 + &pinctrl_adc0_ad5 + &pinctrl_adc0_adtrg>; + atmel,adc-ts-wires = <4>; + status = "okay"; + }; + + usb0: gadget@fffd4000 { + atmel,vbus-gpio = <&pioA 8 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + spi0: spi@fffcc000 { + status = "okay"; + cs-gpios = <&pioA 28 0>, <0>, <0>, <0>; + mtd_dataflash@0 { + compatible = "atmel,at45", "atmel,dataflash"; + spi-max-frequency = <15000000>; + reg = <0>; + }; + }; + + pwm0: pwm@fffc8000 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_pwm1_2>, + <&pinctrl_pwm0_pwm2_2>; + }; + dbgu: serial@fffff200 { status = "okay"; }; @@ -117,18 +194,24 @@ }; }; - leds { - compatible = "gpio-leds"; + pwmleds { + compatible = "pwm-leds"; ds1 { label = "ds1"; - gpios = <&pioD 15 GPIO_ACTIVE_LOW>; + pwms = <&pwm0 1 5000 PWM_POLARITY_INVERTED>; + max-brightness = <255>; }; ds2 { label = "ds2"; - gpios = <&pioD 16 GPIO_ACTIVE_LOW>; + pwms = <&pwm0 2 5000 PWM_POLARITY_INVERTED>; + max-brightness = <255>; }; + }; + + leds { + compatible = "gpio-leds"; ds3 { label = "ds3"; @@ -154,4 +237,12 @@ gpio-key,wakeup; }; }; + + i2c@0 { + status = "okay"; + }; + + i2c@1 { + status = "okay"; + }; }; diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi index fc13c9240da8..1a57298636a5 100644 --- a/arch/arm/boot/dts/at91sam9x5.dtsi +++ b/arch/arm/boot/dts/at91sam9x5.dtsi @@ -14,6 +14,7 @@ #include <dt-bindings/pinctrl/at91.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/clock/at91.h> / { model = "Atmel AT91SAM9x5 family SoC"; @@ -51,6 +52,24 @@ reg = <0x20000000 0x10000000>; }; + slow_xtal: slow_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + main_xtal: main_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + adc_op_clk: adc_op_clk{ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <5000000>; + }; + ahb { compatible = "simple-bus"; #address-cells = <1>; @@ -77,8 +96,272 @@ }; pmc: pmc@fffffc00 { - compatible = "atmel,at91rm9200-pmc"; + compatible = "atmel,at91sam9x5-pmc"; reg = <0xfffffc00 0x100>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + interrupt-controller; + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + main_rc_osc: main_rc_osc { + compatible = "atmel,at91sam9x5-clk-main-rc-osc"; + #clock-cells = <0>; + interrupts-extended = <&pmc AT91_PMC_MOSCRCS>; + clock-frequency = <12000000>; + clock-accuracy = <50000000>; + }; + + main_osc: main_osc { + compatible = "atmel,at91rm9200-clk-main-osc"; + #clock-cells = <0>; + interrupts-extended = <&pmc AT91_PMC_MOSCS>; + clocks = <&main_xtal>; + }; + + main: mainck { + compatible = "atmel,at91sam9x5-clk-main"; + #clock-cells = <0>; + interrupts-extended = <&pmc AT91_PMC_MOSCSELS>; + clocks = <&main_rc_osc>, <&main_osc>; + }; + + plla: pllack { + compatible = "atmel,at91rm9200-clk-pll"; + #clock-cells = <0>; + interrupts-extended = <&pmc AT91_PMC_LOCKA>; + clocks = <&main>; + reg = <0>; + atmel,clk-input-range = <2000000 32000000>; + #atmel,pll-clk-output-range-cells = <4>; + atmel,pll-clk-output-ranges = <745000000 800000000 0 0 + 695000000 750000000 1 0 + 645000000 700000000 2 0 + 595000000 650000000 3 0 + 545000000 600000000 0 1 + 495000000 555000000 1 1 + 445000000 500000000 1 2 + 400000000 450000000 1 3>; + }; + + plladiv: plladivck { + compatible = "atmel,at91sam9x5-clk-plldiv"; + #clock-cells = <0>; + clocks = <&plla>; + }; + + utmi: utmick { + compatible = "atmel,at91sam9x5-clk-utmi"; + #clock-cells = <0>; + interrupts-extended = <&pmc AT91_PMC_LOCKU>; + clocks = <&main>; + }; + + mck: masterck { + compatible = "atmel,at91sam9x5-clk-master"; + #clock-cells = <0>; + interrupts-extended = <&pmc AT91_PMC_MCKRDY>; + clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>; + atmel,clk-output-range = <0 133333333>; + atmel,clk-divisors = <1 2 4 3>; + atmel,master-clk-have-div3-pres; + }; + + usb: usbck { + compatible = "atmel,at91sam9x5-clk-usb"; + #clock-cells = <0>; + clocks = <&plladiv>, <&utmi>; + }; + + prog: progck { + compatible = "atmel,at91sam9x5-clk-programmable"; + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&pmc>; + clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>; + + prog0: prog0 { + #clock-cells = <0>; + reg = <0>; + interrupts = <AT91_PMC_PCKRDY(0)>; + }; + + prog1: prog1 { + #clock-cells = <0>; + reg = <1>; + interrupts = <AT91_PMC_PCKRDY(1)>; + }; + }; + + smd: smdclk { + compatible = "atmel,at91sam9x5-clk-smd"; + #clock-cells = <0>; + clocks = <&plladiv>, <&utmi>; + }; + + systemck { + compatible = "atmel,at91rm9200-clk-system"; + #address-cells = <1>; + #size-cells = <0>; + + ddrck: ddrck { + #clock-cells = <0>; + reg = <2>; + clocks = <&mck>; + }; + + smdck: smdck { + #clock-cells = <0>; + reg = <4>; + clocks = <&smd>; + }; + + uhpck: uhpck { + #clock-cells = <0>; + reg = <6>; + clocks = <&usb>; + }; + + udpck: udpck { + #clock-cells = <0>; + reg = <7>; + clocks = <&usb>; + }; + + pck0: pck0 { + #clock-cells = <0>; + reg = <8>; + clocks = <&prog0>; + }; + + pck1: pck1 { + #clock-cells = <0>; + reg = <9>; + clocks = <&prog1>; + }; + }; + + periphck { + compatible = "atmel,at91sam9x5-clk-peripheral"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&mck>; + + pioAB_clk: pioAB_clk { + #clock-cells = <0>; + reg = <2>; + }; + + pioCD_clk: pioCD_clk { + #clock-cells = <0>; + reg = <3>; + }; + + smd_clk: smd_clk { + #clock-cells = <0>; + reg = <4>; + }; + + usart0_clk: usart0_clk { + #clock-cells = <0>; + reg = <5>; + }; + + usart1_clk: usart1_clk { + #clock-cells = <0>; + reg = <6>; + }; + + usart2_clk: usart2_clk { + #clock-cells = <0>; + reg = <7>; + }; + + twi0_clk: twi0_clk { + reg = <9>; + #clock-cells = <0>; + }; + + twi1_clk: twi1_clk { + #clock-cells = <0>; + reg = <10>; + }; + + twi2_clk: twi2_clk { + #clock-cells = <0>; + reg = <11>; + }; + + mci0_clk: mci0_clk { + #clock-cells = <0>; + reg = <12>; + }; + + spi0_clk: spi0_clk { + #clock-cells = <0>; + reg = <13>; + }; + + spi1_clk: spi1_clk { + #clock-cells = <0>; + reg = <14>; + }; + + uart0_clk: uart0_clk { + #clock-cells = <0>; + reg = <15>; + }; + + uart1_clk: uart1_clk { + #clock-cells = <0>; + reg = <16>; + }; + + tcb0_clk: tcb0_clk { + #clock-cells = <0>; + reg = <17>; + }; + + pwm_clk: pwm_clk { + #clock-cells = <0>; + reg = <18>; + }; + + adc_clk: adc_clk { + #clock-cells = <0>; + reg = <19>; + }; + + dma0_clk: dma0_clk { + #clock-cells = <0>; + reg = <20>; + }; + + dma1_clk: dma1_clk { + #clock-cells = <0>; + reg = <21>; + }; + + uhphs_clk: uhphs_clk { + #clock-cells = <0>; + reg = <22>; + }; + + udphs_clk: udphs_clk { + #clock-cells = <0>; + reg = <23>; + }; + + mci1_clk: mci1_clk { + #clock-cells = <0>; + reg = <26>; + }; + + ssc0_clk: ssc0_clk { + #clock-cells = <0>; + reg = <28>; + }; + }; }; rstc@fffffe00 { @@ -95,18 +378,47 @@ compatible = "atmel,at91sam9260-pit"; reg = <0xfffffe30 0xf>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&mck>; + }; + + sckc@fffffe50 { + compatible = "atmel,at91sam9x5-sckc"; + reg = <0xfffffe50 0x4>; + + slow_osc: slow_osc { + compatible = "atmel,at91sam9x5-clk-slow-osc"; + #clock-cells = <0>; + clocks = <&slow_xtal>; + }; + + slow_rc_osc: slow_rc_osc { + compatible = "atmel,at91sam9x5-clk-slow-rc-osc"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-accuracy = <50000000>; + }; + + clk32k: slck { + compatible = "atmel,at91sam9x5-clk-slow"; + #clock-cells = <0>; + clocks = <&slow_rc_osc>, <&slow_osc>; + }; }; tcb0: timer@f8008000 { compatible = "atmel,at91sam9x5-tcb"; reg = <0xf8008000 0x100>; interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&tcb0_clk>; + clock-names = "t0_clk"; }; tcb1: timer@f800c000 { compatible = "atmel,at91sam9x5-tcb"; reg = <0xf800c000 0x100>; interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&tcb0_clk>; + clock-names = "t0_clk"; }; dma0: dma-controller@ffffec00 { @@ -114,6 +426,8 @@ reg = <0xffffec00 0x200>; interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; #dma-cells = <2>; + clocks = <&dma0_clk>; + clock-names = "dma_clk"; }; dma1: dma-controller@ffffee00 { @@ -121,6 +435,8 @@ reg = <0xffffee00 0x200>; interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>; #dma-cells = <2>; + clocks = <&dma1_clk>; + clock-names = "dma_clk"; }; pinctrl@fffff400 { @@ -453,6 +769,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; + clocks = <&pioAB_clk>; }; pioB: gpio@fffff600 { @@ -464,6 +781,7 @@ #gpio-lines = <19>; interrupt-controller; #interrupt-cells = <2>; + clocks = <&pioAB_clk>; }; pioC: gpio@fffff800 { @@ -474,6 +792,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; + clocks = <&pioCD_clk>; }; pioD: gpio@fffffa00 { @@ -485,6 +804,7 @@ #gpio-lines = <22>; interrupt-controller; #interrupt-cells = <2>; + clocks = <&pioCD_clk>; }; }; @@ -497,6 +817,8 @@ dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; + clocks = <&ssc0_clk>; + clock-names = "pclk"; status = "disabled"; }; @@ -507,6 +829,8 @@ dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(0)>; dma-names = "rxtx"; pinctrl-names = "default"; + clocks = <&mci0_clk>; + clock-names = "mci_clk"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -519,6 +843,8 @@ dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(0)>; dma-names = "rxtx"; pinctrl-names = "default"; + clocks = <&mci1_clk>; + clock-names = "mci_clk"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -530,6 +856,8 @@ interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_dbgu>; + clocks = <&mck>; + clock-names = "usart"; status = "disabled"; }; @@ -539,6 +867,8 @@ interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart0>; + clocks = <&usart0_clk>; + clock-names = "usart"; status = "disabled"; }; @@ -548,6 +878,8 @@ interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart1>; + clocks = <&usart1_clk>; + clock-names = "usart"; status = "disabled"; }; @@ -557,6 +889,8 @@ interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart2>; + clocks = <&usart2_clk>; + clock-names = "usart"; status = "disabled"; }; @@ -571,6 +905,7 @@ #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c0>; + clocks = <&twi0_clk>; status = "disabled"; }; @@ -585,6 +920,7 @@ #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c1>; + clocks = <&twi1_clk>; status = "disabled"; }; @@ -599,6 +935,7 @@ #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; + clocks = <&twi2_clk>; status = "disabled"; }; @@ -608,6 +945,8 @@ interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0>; + clocks = <&uart0_clk>; + clock-names = "usart"; status = "disabled"; }; @@ -617,6 +956,8 @@ interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; + clocks = <&uart1_clk>; + clock-names = "usart"; status = "disabled"; }; @@ -626,6 +967,9 @@ compatible = "atmel,at91sam9260-adc"; reg = <0xf804c000 0x100>; interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&adc_clk>, + <&adc_op_clk>; + clock-names = "adc_clk", "adc_op_clk"; atmel,adc-use-external-triggers; atmel,adc-channels-used = <0xffff>; atmel,adc-vref = <3300>; @@ -673,6 +1017,8 @@ dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0>; + clocks = <&spi0_clk>; + clock-names = "spi_clk"; status = "disabled"; }; @@ -687,6 +1033,8 @@ dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi1>; + clocks = <&spi1_clk>; + clock-names = "spi_clk"; status = "disabled"; }; @@ -805,6 +1153,9 @@ compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00600000 0x100000>; interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; + clocks = <&usb>, <&uhphs_clk>, <&udphs_clk>, + <&uhpck>; + clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck"; status = "disabled"; }; @@ -812,6 +1163,8 @@ compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; reg = <0x00700000 0x100000>; interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; + clocks = <&usb>, <&uhphs_clk>, <&uhpck>; + clock-names = "usb_clk", "ehci_clk", "uhpck"; status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/at91sam9x5_can.dtsi b/arch/arm/boot/dts/at91sam9x5_can.dtsi new file mode 100644 index 000000000000..f44ab7702a12 --- /dev/null +++ b/arch/arm/boot/dts/at91sam9x5_can.dtsi @@ -0,0 +1,31 @@ +/* + * at91sam9x5_macb0.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 1 + * Ethernet interface. + * + * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> + * + * Licensed under GPLv2. + */ + +#include <dt-bindings/pinctrl/at91.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + ahb { + apb { + pmc: pmc@fffffc00 { + periphck { + can0_clk: can0_clk { + #clock-cells = <0>; + reg = <29>; + }; + + can1_clk: can1_clk { + #clock-cells = <0>; + reg = <30>; + }; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/at91sam9x5_isi.dtsi b/arch/arm/boot/dts/at91sam9x5_isi.dtsi new file mode 100644 index 000000000000..98bc877a68ef --- /dev/null +++ b/arch/arm/boot/dts/at91sam9x5_isi.dtsi @@ -0,0 +1,26 @@ +/* + * at91sam9x5_isi.dtsi - Device Tree Include file for AT91SAM9x5 SoC with an + * Image Sensor Interface. + * + * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> + * + * Licensed under GPLv2. + */ + +#include <dt-bindings/pinctrl/at91.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + ahb { + apb { + pmc: pmc@fffffc00 { + periphck { + isi_clk: isi_clk { + #clock-cells = <0>; + reg = <25>; + }; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/at91sam9x5_lcd.dtsi b/arch/arm/boot/dts/at91sam9x5_lcd.dtsi new file mode 100644 index 000000000000..485302e8233d --- /dev/null +++ b/arch/arm/boot/dts/at91sam9x5_lcd.dtsi @@ -0,0 +1,26 @@ +/* + * at91sam9x5_lcd.dtsi - Device Tree Include file for AT91SAM9x5 SoC with an + * LCD controller. + * + * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> + * + * Licensed under GPLv2. + */ + +#include <dt-bindings/pinctrl/at91.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + ahb { + apb { + pmc: pmc@fffffc00 { + periphck { + lcdc_clk: lcdc_clk { + #clock-cells = <0>; + reg = <25>; + }; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/at91sam9x5_macb0.dtsi b/arch/arm/boot/dts/at91sam9x5_macb0.dtsi index 55731ffba764..57e89d1d0325 100644 --- a/arch/arm/boot/dts/at91sam9x5_macb0.dtsi +++ b/arch/arm/boot/dts/at91sam9x5_macb0.dtsi @@ -43,12 +43,23 @@ }; }; + pmc: pmc@fffffc00 { + periphck { + macb0_clk: macb0_clk { + #clock-cells = <0>; + reg = <24>; + }; + }; + }; + macb0: ethernet@f802c000 { compatible = "cdns,at32ap7000-macb", "cdns,macb"; reg = <0xf802c000 0x100>; interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_macb0_rmii>; + clocks = <&macb0_clk>, <&macb0_clk>; + clock-names = "hclk", "pclk"; status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/at91sam9x5_macb1.dtsi b/arch/arm/boot/dts/at91sam9x5_macb1.dtsi index 77425a627a94..663676c02861 100644 --- a/arch/arm/boot/dts/at91sam9x5_macb1.dtsi +++ b/arch/arm/boot/dts/at91sam9x5_macb1.dtsi @@ -31,12 +31,23 @@ }; }; + pmc: pmc@fffffc00 { + periphck { + macb1_clk: macb1_clk { + #clock-cells = <0>; + reg = <27>; + }; + }; + }; + macb1: ethernet@f8030000 { compatible = "cdns,at32ap7000-macb", "cdns,macb"; reg = <0xf8030000 0x100>; interrupts = <27 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_macb1_rmii>; + clocks = <&macb1_clk>, <&macb1_clk>; + clock-names = "hclk", "pclk"; status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/at91sam9x5_usart3.dtsi b/arch/arm/boot/dts/at91sam9x5_usart3.dtsi index 6801106fa1f8..140217a54384 100644 --- a/arch/arm/boot/dts/at91sam9x5_usart3.dtsi +++ b/arch/arm/boot/dts/at91sam9x5_usart3.dtsi @@ -42,12 +42,23 @@ }; }; + pmc: pmc@fffffc00 { + periphck { + usart3_clk: usart3_clk { + #clock-cells = <0>; + reg = <8>; + }; + }; + }; + usart3: serial@f8028000 { compatible = "atmel,at91sam9260-usart"; reg = <0xf8028000 0x200>; interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart3>; + clocks = <&usart3_clk>; + clock-names = "usart"; status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/at91sam9x5cm.dtsi b/arch/arm/boot/dts/at91sam9x5cm.dtsi index 4a5ee5cc115a..8413e21192eb 100644 --- a/arch/arm/boot/dts/at91sam9x5cm.dtsi +++ b/arch/arm/boot/dts/at91sam9x5cm.dtsi @@ -23,6 +23,14 @@ }; }; + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <12000000>; + }; + ahb { apb { pinctrl@fffff400 { diff --git a/arch/arm/boot/dts/atlas6.dtsi b/arch/arm/boot/dts/atlas6.dtsi index 9d72674049d6..bb22842a0826 100644 --- a/arch/arm/boot/dts/atlas6.dtsi +++ b/arch/arm/boot/dts/atlas6.dtsi @@ -39,6 +39,11 @@ }; }; + arm-pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts = <29>; + }; + axi { compatible = "simple-bus"; #address-cells = <1>; @@ -167,6 +172,7 @@ compatible = "sirf,prima2-dspif"; reg = <0xa8000000 0x10000>; interrupts = <9>; + resets = <&rstc 1>; }; gps@a8010000 { @@ -174,6 +180,7 @@ reg = <0xa8010000 0x10000>; interrupts = <7>; clocks = <&clks 9>; + resets = <&rstc 2>; }; dsp@a9000000 { @@ -181,6 +188,7 @@ reg = <0xa9000000 0x1000000>; interrupts = <8>; clocks = <&clks 8>; + resets = <&rstc 0>; }; }; @@ -195,6 +203,7 @@ compatible = "sirf,prima2-tick"; reg = <0xb0020000 0x1000>; interrupts = <0>; + clocks = <&clks 11>; }; nand@b0030000 { @@ -297,9 +306,9 @@ reg = <0xb00d0000 0x10000>; interrupts = <15>; sirf,spi-num-chipselects = <1>; - cs-gpios = <&gpio 0 0>; - sirf,spi-dma-rx-channel = <25>; - sirf,spi-dma-tx-channel = <20>; + dmas = <&dmac1 9>, + <&dmac1 4>; + dma-names = "rx", "tx"; #address-cells = <1>; #size-cells = <0>; clocks = <&clks 19>; @@ -312,8 +321,9 @@ reg = <0xb0170000 0x10000>; interrupts = <16>; sirf,spi-num-chipselects = <1>; - sirf,spi-dma-rx-channel = <12>; - sirf,spi-dma-tx-channel = <13>; + dmas = <&dmac0 12>, + <&dmac0 13>; + dma-names = "rx", "tx"; #address-cells = <1>; #size-cells = <0>; clocks = <&clks 20>; @@ -554,6 +564,18 @@ sirf,function = "usp0_uart_nostreamctrl"; }; }; + usp0_only_utfs_pins_a: usp0@2 { + usp0 { + sirf,pins = "usp0_only_utfs_grp"; + sirf,function = "usp0_only_utfs"; + }; + }; + usp0_only_urfs_pins_a: usp0@3 { + usp0 { + sirf,pins = "usp0_only_urfs_grp"; + sirf,function = "usp0_only_urfs"; + }; + }; usp1_pins_a: usp1@0 { usp1 { sirf,pins = "usp1grp"; diff --git a/arch/arm/boot/dts/axm5516-amarillo.dts b/arch/arm/boot/dts/axm5516-amarillo.dts new file mode 100644 index 000000000000..a9d60471d9ff --- /dev/null +++ b/arch/arm/boot/dts/axm5516-amarillo.dts @@ -0,0 +1,51 @@ +/* + * arch/arm/boot/dts/axm5516-amarillo.dts + * + * Copyright (C) 2013 LSI + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +/dts-v1/; + +/memreserve/ 0x00000000 0x00400000; + +#include "axm55xx.dtsi" +#include "axm5516-cpus.dtsi" + +/ { + model = "Amarillo AXM5516"; + compatible = "lsi,axm5516-amarillo", "lsi,axm5516"; + + memory { + device_type = "memory"; + reg = <0 0x00000000 0x02 0x00000000>; + }; +}; + +&serial0 { + status = "okay"; +}; + +&serial1 { + status = "okay"; +}; + +&serial2 { + status = "okay"; +}; + +&serial3 { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/axm5516-cpus.dtsi b/arch/arm/boot/dts/axm5516-cpus.dtsi new file mode 100644 index 000000000000..b85f360cb125 --- /dev/null +++ b/arch/arm/boot/dts/axm5516-cpus.dtsi @@ -0,0 +1,204 @@ +/* + * arch/arm/boot/dts/axm5516-cpus.dtsi + * + * Copyright (C) 2013 LSI + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + core1 { + cpu = <&CPU1>; + }; + core2 { + cpu = <&CPU2>; + }; + core3 { + cpu = <&CPU3>; + }; + }; + cluster1 { + core0 { + cpu = <&CPU4>; + }; + core1 { + cpu = <&CPU5>; + }; + core2 { + cpu = <&CPU6>; + }; + core3 { + cpu = <&CPU7>; + }; + }; + cluster2 { + core0 { + cpu = <&CPU8>; + }; + core1 { + cpu = <&CPU9>; + }; + core2 { + cpu = <&CPU10>; + }; + core3 { + cpu = <&CPU11>; + }; + }; + cluster3 { + core0 { + cpu = <&CPU12>; + }; + core1 { + cpu = <&CPU13>; + }; + core2 { + cpu = <&CPU14>; + }; + core3 { + cpu = <&CPU15>; + }; + }; + }; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x00>; + clock-frequency= <1400000000>; + cpu-release-addr = <0>; // Fixed by the boot loader + }; + + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x01>; + clock-frequency= <1400000000>; + cpu-release-addr = <0>; // Fixed by the boot loader + }; + + CPU2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x02>; + clock-frequency= <1400000000>; + cpu-release-addr = <0>; // Fixed by the boot loader + }; + + CPU3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x03>; + clock-frequency= <1400000000>; + cpu-release-addr = <0>; // Fixed by the boot loader + }; + + CPU4: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x100>; + clock-frequency= <1400000000>; + cpu-release-addr = <0>; // Fixed by the boot loader + }; + + CPU5: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x101>; + clock-frequency= <1400000000>; + cpu-release-addr = <0>; // Fixed by the boot loader + }; + + CPU6: cpu@102 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x102>; + clock-frequency= <1400000000>; + cpu-release-addr = <0>; // Fixed by the boot loader + }; + + CPU7: cpu@103 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x103>; + clock-frequency= <1400000000>; + cpu-release-addr = <0>; // Fixed by the boot loader + }; + + CPU8: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x200>; + clock-frequency= <1400000000>; + cpu-release-addr = <0>; // Fixed by the boot loader + }; + + CPU9: cpu@201 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x201>; + clock-frequency= <1400000000>; + cpu-release-addr = <0>; // Fixed by the boot loader + }; + + CPU10: cpu@202 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x202>; + clock-frequency= <1400000000>; + cpu-release-addr = <0>; // Fixed by the boot loader + }; + + CPU11: cpu@203 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x203>; + clock-frequency= <1400000000>; + cpu-release-addr = <0>; // Fixed by the boot loader + }; + + CPU12: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x300>; + clock-frequency= <1400000000>; + cpu-release-addr = <0>; // Fixed by the boot loader + }; + + CPU13: cpu@301 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x301>; + clock-frequency= <1400000000>; + cpu-release-addr = <0>; // Fixed by the boot loader + }; + + CPU14: cpu@302 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x302>; + clock-frequency= <1400000000>; + cpu-release-addr = <0>; // Fixed by the boot loader + }; + + CPU15: cpu@303 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x303>; + clock-frequency= <1400000000>; + cpu-release-addr = <0>; // Fixed by the boot loader + }; + }; +}; diff --git a/arch/arm/boot/dts/axm55xx.dtsi b/arch/arm/boot/dts/axm55xx.dtsi new file mode 100644 index 000000000000..ea288f0a1d39 --- /dev/null +++ b/arch/arm/boot/dts/axm55xx.dtsi @@ -0,0 +1,204 @@ +/* + * arch/arm/boot/dts/axm55xx.dtsi + * + * Copyright (C) 2013 LSI + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/lsi,axm5516-clks.h> + +#include "skeleton64.dtsi" + +/ { + interrupt-parent = <&gic>; + + aliases { + serial0 = &serial0; + serial1 = &serial1; + serial2 = &serial2; + serial3 = &serial3; + timer = &timer0; + }; + + clocks { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clk_ref0: clk_ref0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; + + clk_ref1: clk_ref1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; + + clk_ref2: clk_ref2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; + + clks: clock-controller@2010020000 { + compatible = "lsi,axm5516-clks"; + #clock-cells = <1>; + reg = <0x20 0x10020000 0 0x20000>; + }; + }; + + gic: interrupt-controller@2001001000 { + compatible = "arm,cortex-a15-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x20 0x01001000 0 0x1000>, + <0x20 0x01002000 0 0x1000>, + <0x20 0x01004000 0 0x2000>, + <0x20 0x01006000 0 0x2000>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | + IRQ_TYPE_LEVEL_HIGH)>; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = + <GIC_PPI 13 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + }; + + + pmu { + compatible = "arm,cortex-a15-pmu"; + interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; + }; + + soc { + compatible = "simple-bus"; + device_type = "soc"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&gic>; + ranges; + + syscon: syscon@2010030000 { + compatible = "lsi,axxia-syscon", "syscon"; + reg = <0x20 0x10030000 0 0x2000>; + }; + + reset: reset@2010031000 { + compatible = "lsi,axm55xx-reset"; + syscon = <&syscon>; + }; + + amba { + compatible = "arm,amba-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + serial0: uart@2010080000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x20 0x10080000 0 0x1000>; + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks AXXIA_CLK_PER>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + serial1: uart@2010081000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x20 0x10081000 0 0x1000>; + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks AXXIA_CLK_PER>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + serial2: uart@2010082000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x20 0x10082000 0 0x1000>; + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks AXXIA_CLK_PER>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + serial3: uart@2010083000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x20 0x10083000 0 0x1000>; + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks AXXIA_CLK_PER>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + timer0: timer@2010091000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x20 0x10091000 0 0x1000>; + interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks AXXIA_CLK_PER>; + clock-names = "apb_pclk"; + status = "okay"; + }; + + gpio0: gpio@2010092000 { + #gpio-cells = <2>; + compatible = "arm,pl061", "arm,primecell"; + gpio-controller; + reg = <0x20 0x10092000 0x00 0x1000>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks AXXIA_CLK_PER>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + gpio1: gpio@2010093000 { + #gpio-cells = <2>; + compatible = "arm,pl061", "arm,primecell"; + gpio-controller; + reg = <0x20 0x10093000 0x00 0x1000>; + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks AXXIA_CLK_PER>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + }; + }; +}; + +/* + Local Variables: + mode: C + End: +*/ diff --git a/arch/arm/boot/dts/bcm11351.dtsi b/arch/arm/boot/dts/bcm11351.dtsi index 64d069bcc409..6b05ae6d476f 100644 --- a/arch/arm/boot/dts/bcm11351.dtsi +++ b/arch/arm/boot/dts/bcm11351.dtsi @@ -193,6 +193,14 @@ status = "disabled"; }; + pwm: pwm@3e01a000 { + compatible = "brcm,bcm11351-pwm", "brcm,kona-pwm"; + reg = <0x3e01a000 0xcc>; + clocks = <&slave_ccu BCM281XX_SLAVE_CCU_PWM>; + #pwm-cells = <3>; + status = "disabled"; + }; + clocks { #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/bcm21664.dtsi b/arch/arm/boot/dts/bcm21664.dtsi index 08a44d41b672..8b366822bb43 100644 --- a/arch/arm/boot/dts/bcm21664.dtsi +++ b/arch/arm/boot/dts/bcm21664.dtsi @@ -14,6 +14,8 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h> +#include "dt-bindings/clock/bcm21664.h" + #include "skeleton.dtsi" / { @@ -43,7 +45,7 @@ compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart"; status = "disabled"; reg = <0x3e000000 0x118>; - clocks = <&uartb_clk>; + clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB>; interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; @@ -53,7 +55,7 @@ compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart"; status = "disabled"; reg = <0x3e001000 0x118>; - clocks = <&uartb2_clk>; + clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB2>; interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; @@ -63,7 +65,7 @@ compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart"; status = "disabled"; reg = <0x3e002000 0x118>; - clocks = <&uartb3_clk>; + clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB3>; interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; @@ -85,7 +87,7 @@ compatible = "brcm,kona-timer"; reg = <0x35006000 0x1c>; interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&hub_timer_clk>; + clocks = <&aon_ccu BCM21664_AON_CCU_HUB_TIMER>; }; gpio: gpio@35003000 { @@ -106,7 +108,7 @@ compatible = "brcm,kona-sdhci"; reg = <0x3f180000 0x801c>; interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&sdio1_clk>; + clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO1>; status = "disabled"; }; @@ -114,7 +116,7 @@ compatible = "brcm,kona-sdhci"; reg = <0x3f190000 0x801c>; interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&sdio2_clk>; + clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO2>; status = "disabled"; }; @@ -122,7 +124,7 @@ compatible = "brcm,kona-sdhci"; reg = <0x3f1a0000 0x801c>; interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&sdio3_clk>; + clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO3>; status = "disabled"; }; @@ -130,7 +132,7 @@ compatible = "brcm,kona-sdhci"; reg = <0x3f1b0000 0x801c>; interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&sdio4_clk>; + clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO4>; status = "disabled"; }; @@ -140,7 +142,7 @@ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; - clocks = <&bsc1_clk>; + clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC1>; status = "disabled"; }; @@ -150,7 +152,7 @@ interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; - clocks = <&bsc2_clk>; + clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC2>; status = "disabled"; }; @@ -160,7 +162,7 @@ interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; - clocks = <&bsc3_clk>; + clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC3>; status = "disabled"; }; @@ -170,105 +172,149 @@ interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; - clocks = <&bsc4_clk>; + clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC4>; status = "disabled"; }; clocks { - bsc1_clk: bsc1 { - compatible = "fixed-clock"; - clock-frequency = <13000000>; - #clock-cells = <0>; - }; + #address-cells = <1>; + #size-cells = <1>; + ranges; - bsc2_clk: bsc2 { - compatible = "fixed-clock"; - clock-frequency = <13000000>; + /* + * Fixed clocks are defined before CCUs whose + * clocks may depend on them. + */ + + ref_32k_clk: ref_32k { #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; }; - bsc3_clk: bsc3 { - compatible = "fixed-clock"; - clock-frequency = <13000000>; + bbl_32k_clk: bbl_32k { #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; }; - bsc4_clk: bsc4 { + ref_13m_clk: ref_13m { + #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <13000000>; - #clock-cells = <0>; }; - pmu_bsc_clk: pmu_bsc { + var_13m_clk: var_13m { + #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <13000000>; - #clock-cells = <0>; }; - hub_timer_clk: hub_timer { - compatible = "fixed-clock"; - clock-frequency = <32768>; + dft_19_5m_clk: dft_19_5m { #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <19500000>; }; - pwm_clk: pwm { + ref_crystal_clk: ref_crystal { + #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <26000000>; - #clock-cells = <0>; }; - sdio1_clk: sdio1 { - compatible = "fixed-clock"; - clock-frequency = <48000000>; + ref_52m_clk: ref_52m { #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <52000000>; }; - sdio2_clk: sdio2 { - compatible = "fixed-clock"; - clock-frequency = <48000000>; + var_52m_clk: var_52m { #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <52000000>; }; - sdio3_clk: sdio3 { - compatible = "fixed-clock"; - clock-frequency = <48000000>; + usb_otg_ahb_clk: usb_otg_ahb { #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <52000000>; }; - sdio4_clk: sdio4 { - compatible = "fixed-clock"; - clock-frequency = <48000000>; + ref_96m_clk: ref_96m { #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <96000000>; }; - tmon_1m_clk: tmon_1m { - compatible = "fixed-clock"; - clock-frequency = <1000000>; + var_96m_clk: var_96m { #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <96000000>; }; - uartb_clk: uartb { - compatible = "fixed-clock"; - clock-frequency = <13000000>; + ref_104m_clk: ref_104m { #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <104000000>; }; - uartb2_clk: uartb2 { - compatible = "fixed-clock"; - clock-frequency = <13000000>; + var_104m_clk: var_104m { #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <104000000>; }; - uartb3_clk: uartb3 { - compatible = "fixed-clock"; - clock-frequency = <13000000>; + ref_156m_clk: ref_156m { #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <156000000>; }; - usb_otg_ahb_clk: usb_otg_ahb { - compatible = "fixed-clock"; - clock-frequency = <52000000>; + var_156m_clk: var_156m { #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <156000000>; + }; + + root_ccu: root_ccu { + compatible = BCM21664_DT_ROOT_CCU_COMPAT; + reg = <0x35001000 0x0f00>; + #clock-cells = <1>; + clock-output-names = "frac_1m"; + }; + + aon_ccu: aon_ccu { + compatible = BCM21664_DT_AON_CCU_COMPAT; + reg = <0x35002000 0x0f00>; + #clock-cells = <1>; + clock-output-names = "hub_timer"; + }; + + master_ccu: master_ccu { + compatible = BCM21664_DT_MASTER_CCU_COMPAT; + reg = <0x3f001000 0x0f00>; + #clock-cells = <1>; + clock-output-names = "sdio1", + "sdio2", + "sdio3", + "sdio4", + "sdio1_sleep", + "sdio2_sleep", + "sdio3_sleep", + "sdio4_sleep"; + }; + + slave_ccu: slave_ccu { + compatible = BCM21664_DT_SLAVE_CCU_COMPAT; + reg = <0x3e011000 0x0f00>; + #clock-cells = <1>; + clock-output-names = "uartb", + "uartb2", + "uartb3", + "bsc1", + "bsc2", + "bsc3", + "bsc4"; }; }; diff --git a/arch/arm/boot/dts/bcm28155-ap.dts b/arch/arm/boot/dts/bcm28155-ap.dts index af3da55eef49..9ce91dd60cb6 100644 --- a/arch/arm/boot/dts/bcm28155-ap.dts +++ b/arch/arm/boot/dts/bcm28155-ap.dts @@ -69,6 +69,10 @@ status = "okay"; }; + pwm: pwm@3e01a000 { + status = "okay"; + }; + usbotg: usb@3f120000 { vusb_d-supply = <&usbldo_reg>; vusb_a-supply = <&iosr1_reg>; diff --git a/arch/arm/boot/dts/bcm59056.dtsi b/arch/arm/boot/dts/bcm59056.dtsi index dfadaaa89b05..066adfb10bd5 100644 --- a/arch/arm/boot/dts/bcm59056.dtsi +++ b/arch/arm/boot/dts/bcm59056.dtsi @@ -70,5 +70,26 @@ vsr_reg: vsr { }; + + gpldo1_reg: gpldo1 { + }; + + gpldo2_reg: gpldo2 { + }; + + gpldo3_reg: gpldo3 { + }; + + gpldo4_reg: gpldo4 { + }; + + gpldo5_reg: gpldo5 { + }; + + gpldo6_reg: gpldo6 { + }; + + vbus_reg: vbus { + }; }; }; diff --git a/arch/arm/boot/dts/berlin2.dtsi b/arch/arm/boot/dts/berlin2.dtsi index 56a1af2f1052..2477dac4d643 100644 --- a/arch/arm/boot/dts/berlin2.dtsi +++ b/arch/arm/boot/dts/berlin2.dtsi @@ -12,6 +12,7 @@ */ #include "skeleton.dtsi" +#include <dt-bindings/clock/berlin2.h> #include <dt-bindings/interrupt-controller/arm-gic.h> / { @@ -37,24 +38,10 @@ }; }; - clocks { - smclk: sysmgr-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - - cfgclk: cfg-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - }; - - sysclk: system-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <400000000>; - }; + refclk: oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; }; soc { @@ -72,6 +59,11 @@ cache-level = <2>; }; + scu: snoop-control-unit@ad0000 { + compatible = "arm,cortex-a9-scu"; + reg = <0xad0000 0x58>; + }; + gic: interrupt-controller@ad1000 { compatible = "arm,cortex-a9-gic"; reg = <0xad1000 0x1000>, <0xad0100 0x0100>; @@ -83,7 +75,7 @@ compatible = "arm,cortex-a9-twd-timer"; reg = <0xad0600 0x20>; interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&sysclk>; + clocks = <&chip CLKID_TWD>; }; apb@e80000 { @@ -94,11 +86,83 @@ ranges = <0 0xe80000 0x10000>; interrupt-parent = <&aic>; + gpio0: gpio@0400 { + compatible = "snps,dw-apb-gpio"; + reg = <0x0400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + porta: gpio-port@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <8>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0>; + }; + }; + + gpio1: gpio@0800 { + compatible = "snps,dw-apb-gpio"; + reg = <0x0800 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + portb: gpio-port@1 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <8>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <1>; + }; + }; + + gpio2: gpio@0c00 { + compatible = "snps,dw-apb-gpio"; + reg = <0x0c00 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + portc: gpio-port@2 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <8>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <2>; + }; + }; + + gpio3: gpio@1000 { + compatible = "snps,dw-apb-gpio"; + reg = <0x1000 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + portd: gpio-port@3 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <8>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <3>; + }; + }; + timer0: timer@2c00 { compatible = "snps,dw-apb-timer"; reg = <0x2c00 0x14>; interrupts = <8>; - clocks = <&cfgclk>; + clocks = <&chip CLKID_CFG>; clock-names = "timer"; status = "okay"; }; @@ -107,7 +171,7 @@ compatible = "snps,dw-apb-timer"; reg = <0x2c14 0x14>; interrupts = <9>; - clocks = <&cfgclk>; + clocks = <&chip CLKID_CFG>; clock-names = "timer"; status = "okay"; }; @@ -116,7 +180,7 @@ compatible = "snps,dw-apb-timer"; reg = <0x2c28 0x14>; interrupts = <10>; - clocks = <&cfgclk>; + clocks = <&chip CLKID_CFG>; clock-names = "timer"; status = "disabled"; }; @@ -125,7 +189,7 @@ compatible = "snps,dw-apb-timer"; reg = <0x2c3c 0x14>; interrupts = <11>; - clocks = <&cfgclk>; + clocks = <&chip CLKID_CFG>; clock-names = "timer"; status = "disabled"; }; @@ -134,7 +198,7 @@ compatible = "snps,dw-apb-timer"; reg = <0x2c50 0x14>; interrupts = <12>; - clocks = <&cfgclk>; + clocks = <&chip CLKID_CFG>; clock-names = "timer"; status = "disabled"; }; @@ -143,7 +207,7 @@ compatible = "snps,dw-apb-timer"; reg = <0x2c64 0x14>; interrupts = <13>; - clocks = <&cfgclk>; + clocks = <&chip CLKID_CFG>; clock-names = "timer"; status = "disabled"; }; @@ -152,7 +216,7 @@ compatible = "snps,dw-apb-timer"; reg = <0x2c78 0x14>; interrupts = <14>; - clocks = <&cfgclk>; + clocks = <&chip CLKID_CFG>; clock-names = "timer"; status = "disabled"; }; @@ -161,7 +225,7 @@ compatible = "snps,dw-apb-timer"; reg = <0x2c8c 0x14>; interrupts = <15>; - clocks = <&cfgclk>; + clocks = <&chip CLKID_CFG>; clock-names = "timer"; status = "disabled"; }; @@ -176,6 +240,14 @@ }; }; + chip: chip-control@ea0000 { + compatible = "marvell,berlin2-chip-ctrl"; + #clock-cells = <1>; + reg = <0xea0000 0x400>; + clocks = <&refclk>; + clock-names = "refclk"; + }; + apb@fc0000 { compatible = "simple-bus"; #address-cells = <1>; @@ -184,13 +256,48 @@ ranges = <0 0xfc0000 0x10000>; interrupt-parent = <&sic>; + sm_gpio1: gpio@5000 { + compatible = "snps,dw-apb-gpio"; + reg = <0x5000 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + portf: gpio-port@5 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <8>; + reg = <0>; + }; + }; + + sm_gpio0: gpio@c000 { + compatible = "snps,dw-apb-gpio"; + reg = <0xc000 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + porte: gpio-port@4 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <8>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <11>; + }; + }; + uart0: serial@9000 { compatible = "snps,dw-apb-uart"; reg = <0x9000 0x100>; reg-shift = <2>; reg-io-width = <1>; interrupts = <8>; - clocks = <&smclk>; + clocks = <&refclk>; + pinctrl-0 = <&uart0_pmux>; + pinctrl-names = "default"; status = "disabled"; }; @@ -200,7 +307,9 @@ reg-shift = <2>; reg-io-width = <1>; interrupts = <9>; - clocks = <&smclk>; + clocks = <&refclk>; + pinctrl-0 = <&uart1_pmux>; + pinctrl-names = "default"; status = "disabled"; }; @@ -210,10 +319,32 @@ reg-shift = <2>; reg-io-width = <1>; interrupts = <10>; - clocks = <&smclk>; + clocks = <&refclk>; + pinctrl-0 = <&uart2_pmux>; + pinctrl-names = "default"; status = "disabled"; }; + sysctrl: system-controller@d000 { + compatible = "marvell,berlin2-system-ctrl"; + reg = <0xd000 0x100>; + + uart0_pmux: uart0-pmux { + groups = "GSM4"; + function = "uart0"; + }; + + uart1_pmux: uart1-pmux { + groups = "GSM5"; + function = "uart1"; + }; + + uart2_pmux: uart2-pmux { + groups = "GSM3"; + function = "uart2"; + }; + }; + sic: interrupt-controller@e000 { compatible = "snps,dw-apb-ictl"; reg = <0xe000 0x400>; diff --git a/arch/arm/boot/dts/berlin2cd.dtsi b/arch/arm/boot/dts/berlin2cd.dtsi index 094968c27533..cc1df65da504 100644 --- a/arch/arm/boot/dts/berlin2cd.dtsi +++ b/arch/arm/boot/dts/berlin2cd.dtsi @@ -12,6 +12,7 @@ */ #include "skeleton.dtsi" +#include <dt-bindings/clock/berlin2.h> #include <dt-bindings/interrupt-controller/arm-gic.h> / { @@ -30,24 +31,10 @@ }; }; - clocks { - smclk: sysmgr-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - - cfgclk: cfg-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <75000000>; - }; - - sysclk: system-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <300000000>; - }; + refclk: oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; }; soc { @@ -76,7 +63,7 @@ compatible = "arm,cortex-a9-twd-timer"; reg = <0xad0600 0x20>; interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&sysclk>; + clocks = <&chip CLKID_TWD>; }; apb@e80000 { @@ -87,11 +74,83 @@ ranges = <0 0xe80000 0x10000>; interrupt-parent = <&aic>; + gpio0: gpio@0400 { + compatible = "snps,dw-apb-gpio"; + reg = <0x0400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + porta: gpio-port@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <8>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0>; + }; + }; + + gpio1: gpio@0800 { + compatible = "snps,dw-apb-gpio"; + reg = <0x0800 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + portb: gpio-port@1 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <8>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <1>; + }; + }; + + gpio2: gpio@0c00 { + compatible = "snps,dw-apb-gpio"; + reg = <0x0c00 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + portc: gpio-port@2 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <8>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <2>; + }; + }; + + gpio3: gpio@1000 { + compatible = "snps,dw-apb-gpio"; + reg = <0x1000 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + portd: gpio-port@3 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <8>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <3>; + }; + }; + timer0: timer@2c00 { compatible = "snps,dw-apb-timer"; reg = <0x2c00 0x14>; interrupts = <8>; - clocks = <&cfgclk>; + clocks = <&chip CLKID_CFG>; clock-names = "timer"; status = "okay"; }; @@ -100,7 +159,7 @@ compatible = "snps,dw-apb-timer"; reg = <0x2c14 0x14>; interrupts = <9>; - clocks = <&cfgclk>; + clocks = <&chip CLKID_CFG>; clock-names = "timer"; status = "okay"; }; @@ -109,7 +168,7 @@ compatible = "snps,dw-apb-timer"; reg = <0x2c28 0x14>; interrupts = <10>; - clocks = <&cfgclk>; + clocks = <&chip CLKID_CFG>; clock-names = "timer"; status = "disabled"; }; @@ -118,7 +177,7 @@ compatible = "snps,dw-apb-timer"; reg = <0x2c3c 0x14>; interrupts = <11>; - clocks = <&cfgclk>; + clocks = <&chip CLKID_CFG>; clock-names = "timer"; status = "disabled"; }; @@ -127,7 +186,7 @@ compatible = "snps,dw-apb-timer"; reg = <0x2c50 0x14>; interrupts = <12>; - clocks = <&cfgclk>; + clocks = <&chip CLKID_CFG>; clock-names = "timer"; status = "disabled"; }; @@ -136,7 +195,7 @@ compatible = "snps,dw-apb-timer"; reg = <0x2c64 0x14>; interrupts = <13>; - clocks = <&cfgclk>; + clocks = <&chip CLKID_CFG>; clock-names = "timer"; status = "disabled"; }; @@ -145,7 +204,7 @@ compatible = "snps,dw-apb-timer"; reg = <0x2c78 0x14>; interrupts = <14>; - clocks = <&cfgclk>; + clocks = <&chip CLKID_CFG>; clock-names = "timer"; status = "disabled"; }; @@ -154,7 +213,7 @@ compatible = "snps,dw-apb-timer"; reg = <0x2c8c 0x14>; interrupts = <15>; - clocks = <&cfgclk>; + clocks = <&chip CLKID_CFG>; clock-names = "timer"; status = "disabled"; }; @@ -169,6 +228,19 @@ }; }; + chip: chip-control@ea0000 { + compatible = "marvell,berlin2cd-chip-ctrl"; + #clock-cells = <1>; + reg = <0xea0000 0x400>; + clocks = <&refclk>; + clock-names = "refclk"; + + uart0_pmux: uart0-pmux { + groups = "G6"; + function = "uart0"; + }; + }; + apb@fc0000 { compatible = "simple-bus"; #address-cells = <1>; @@ -177,13 +249,45 @@ ranges = <0 0xfc0000 0x10000>; interrupt-parent = <&sic>; + sm_gpio1: gpio@5000 { + compatible = "snps,dw-apb-gpio"; + reg = <0x5000 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + portf: gpio-port@5 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <8>; + reg = <0>; + }; + }; + + sm_gpio0: gpio@c000 { + compatible = "snps,dw-apb-gpio"; + reg = <0xc000 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + porte: gpio-port@4 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <8>; + reg = <0>; + }; + }; + uart0: serial@9000 { compatible = "snps,dw-apb-uart"; reg = <0x9000 0x100>; reg-shift = <2>; reg-io-width = <1>; interrupts = <8>; - clocks = <&smclk>; + clocks = <&refclk>; + pinctrl-0 = <&uart0_pmux>; + pinctrl-names = "default"; status = "disabled"; }; @@ -193,10 +297,15 @@ reg-shift = <2>; reg-io-width = <1>; interrupts = <9>; - clocks = <&smclk>; + clocks = <&refclk>; status = "disabled"; }; + sysctrl: system-controller@d000 { + compatible = "marvell,berlin2cd-system-ctrl"; + reg = <0xd000 0x100>; + }; + sic: interrupt-controller@e000 { compatible = "snps,dw-apb-ictl"; reg = <0xe000 0x400>; diff --git a/arch/arm/boot/dts/berlin2q-marvell-dmp.dts b/arch/arm/boot/dts/berlin2q-marvell-dmp.dts new file mode 100644 index 000000000000..995150f93795 --- /dev/null +++ b/arch/arm/boot/dts/berlin2q-marvell-dmp.dts @@ -0,0 +1,39 @@ +/* + * Copyright (C) 2014 Antoine Ténart <antoine.tenart@free-electrons.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/dts-v1/; +#include "berlin2q.dtsi" + +/ { + model = "Marvell BG2-Q DMP"; + compatible = "marvell,berlin2q-dmp", "marvell,berlin2q", "marvell,berlin"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x80000000>; + }; + + choosen { + bootargs = "console=ttyS0,115200 earlyprintk"; + }; +}; + +&sdhci1 { + broken-cd; + sdhci,wp-inverted; + status = "okay"; +}; + +&sdhci2 { + non-removable; + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi new file mode 100644 index 000000000000..635a16a64cb4 --- /dev/null +++ b/arch/arm/boot/dts/berlin2q.dtsi @@ -0,0 +1,363 @@ +/* + * Copyright (C) 2014 Antoine Ténart <antoine.tenart@free-electrons.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <dt-bindings/clock/berlin2q.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +#include "skeleton.dtsi" + +/ { + model = "Marvell Armada 1500 pro (BG2-Q) SoC"; + compatible = "marvell,berlin2q", "marvell,berlin"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + next-level-cache = <&l2>; + reg = <0>; + }; + + cpu@1 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + next-level-cache = <&l2>; + reg = <1>; + }; + + cpu@2 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + next-level-cache = <&l2>; + reg = <2>; + }; + + cpu@3 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + next-level-cache = <&l2>; + reg = <3>; + }; + }; + + refclk: oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0 0xf7000000 0x1000000>; + interrupt-parent = <&gic>; + + sdhci0: sdhci@ab0000 { + compatible = "mrvl,pxav3-mmc"; + reg = <0xab0000 0x200>; + clocks = <&chip CLKID_SDIO1XIN>; + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + sdhci1: sdhci@ab0800 { + compatible = "mrvl,pxav3-mmc"; + reg = <0xab0800 0x200>; + clocks = <&chip CLKID_SDIO1XIN>; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + sdhci2: sdhci@ab1000 { + compatible = "mrvl,pxav3-mmc"; + reg = <0xab1000 0x200>; + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&chip CLKID_SDIO1XIN>; + status = "disabled"; + }; + + l2: l2-cache-controller@ac0000 { + compatible = "arm,pl310-cache"; + reg = <0xac0000 0x1000>; + cache-level = <2>; + }; + + scu: snoop-control-unit@ad0000 { + compatible = "arm,cortex-a9-scu"; + reg = <0xad0000 0x58>; + }; + + local-timer@ad0600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0xad0600 0x20>; + clocks = <&chip CLKID_TWD>; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>; + }; + + gic: interrupt-controller@ad1000 { + compatible = "arm,cortex-a9-gic"; + reg = <0xad1000 0x1000>, <0xad0100 0x100>; + interrupt-controller; + #interrupt-cells = <3>; + }; + + apb@e80000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0 0xe80000 0x10000>; + interrupt-parent = <&aic>; + + gpio0: gpio@0400 { + compatible = "snps,dw-apb-gpio"; + reg = <0x0400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + porta: gpio-port@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <32>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0>; + }; + }; + + gpio1: gpio@0800 { + compatible = "snps,dw-apb-gpio"; + reg = <0x0800 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + portb: gpio-port@1 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <32>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <1>; + }; + }; + + gpio2: gpio@0c00 { + compatible = "snps,dw-apb-gpio"; + reg = <0x0c00 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + portc: gpio-port@2 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <32>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <2>; + }; + }; + + gpio3: gpio@1000 { + compatible = "snps,dw-apb-gpio"; + reg = <0x1000 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + portd: gpio-port@3 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <32>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <3>; + }; + }; + + timer0: timer@2c00 { + compatible = "snps,dw-apb-timer"; + reg = <0x2c00 0x14>; + clocks = <&chip CLKID_CFG>; + clock-names = "timer"; + interrupts = <8>; + }; + + timer1: timer@2c14 { + compatible = "snps,dw-apb-timer"; + reg = <0x2c14 0x14>; + clocks = <&chip CLKID_CFG>; + clock-names = "timer"; + status = "disabled"; + }; + + timer2: timer@2c28 { + compatible = "snps,dw-apb-timer"; + reg = <0x2c28 0x14>; + clocks = <&chip CLKID_CFG>; + clock-names = "timer"; + status = "disabled"; + }; + + timer3: timer@2c3c { + compatible = "snps,dw-apb-timer"; + reg = <0x2c3c 0x14>; + clocks = <&chip CLKID_CFG>; + clock-names = "timer"; + status = "disabled"; + }; + + timer4: timer@2c50 { + compatible = "snps,dw-apb-timer"; + reg = <0x2c50 0x14>; + clocks = <&chip CLKID_CFG>; + clock-names = "timer"; + status = "disabled"; + }; + + timer5: timer@2c64 { + compatible = "snps,dw-apb-timer"; + reg = <0x2c64 0x14>; + clocks = <&chip CLKID_CFG>; + clock-names = "timer"; + status = "disabled"; + }; + + timer6: timer@2c78 { + compatible = "snps,dw-apb-timer"; + reg = <0x2c78 0x14>; + clocks = <&chip CLKID_CFG>; + clock-names = "timer"; + status = "disabled"; + }; + + timer7: timer@2c8c { + compatible = "snps,dw-apb-timer"; + reg = <0x2c8c 0x14>; + clocks = <&chip CLKID_CFG>; + clock-names = "timer"; + status = "disabled"; + }; + + aic: interrupt-controller@3800 { + compatible = "snps,dw-apb-ictl"; + reg = <0x3800 0x30>; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; + }; + + gpio4: gpio@5000 { + compatible = "snps,dw-apb-gpio"; + reg = <0x5000 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + porte: gpio-port@4 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <32>; + reg = <0>; + }; + }; + + gpio5: gpio@c000 { + compatible = "snps,dw-apb-gpio"; + reg = <0xc000 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + portf: gpio-port@5 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <32>; + reg = <0>; + }; + }; + }; + + chip: chip-control@ea0000 { + compatible = "marvell,berlin2q-chip-ctrl"; + #clock-cells = <1>; + reg = <0xea0000 0x400>, <0xdd0170 0x10>; + clocks = <&refclk>; + clock-names = "refclk"; + }; + + apb@fc0000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0 0xfc0000 0x10000>; + interrupt-parent = <&sic>; + + uart0: uart@9000 { + compatible = "snps,dw-apb-uart"; + reg = <0x9000 0x100>; + interrupt-parent = <&sic>; + interrupts = <8>; + clocks = <&refclk>; + reg-shift = <2>; + pinctrl-0 = <&uart0_pmux>; + pinctrl-names = "default"; + status = "disabled"; + }; + + uart1: uart@a000 { + compatible = "snps,dw-apb-uart"; + reg = <0xa000 0x100>; + interrupt-parent = <&sic>; + interrupts = <9>; + clocks = <&refclk>; + reg-shift = <2>; + pinctrl-0 = <&uart1_pmux>; + pinctrl-names = "default"; + status = "disabled"; + }; + + sysctrl: pin-controller@d000 { + compatible = "marvell,berlin2q-system-ctrl"; + reg = <0xd000 0x100>; + + uart0_pmux: uart0-pmux { + groups = "GSM12"; + function = "uart0"; + }; + + uart1_pmux: uart1-pmux { + groups = "GSM14"; + function = "uart1"; + }; + }; + + sic: interrupt-controller@e000 { + compatible = "snps,dw-apb-ictl"; + reg = <0xe000 0x30>; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts index 5babba0a3a75..4adc28039c30 100644 --- a/arch/arm/boot/dts/dra7-evm.dts +++ b/arch/arm/boot/dts/dra7-evm.dts @@ -7,11 +7,11 @@ */ /dts-v1/; -#include "dra7.dtsi" +#include "dra74x.dtsi" / { - model = "TI DRA7"; - compatible = "ti,dra7-evm", "ti,dra752", "ti,dra7"; + model = "TI DRA742"; + compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7"; memory { device_type = "memory"; @@ -93,6 +93,64 @@ 0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */ >; }; + + qspi1_pins: pinmux_qspi1_pins { + pinctrl-single,pins = < + 0x4c (PIN_INPUT | MUX_MODE1) /* gpmc_a3.qspi1_cs2 */ + 0x50 (PIN_INPUT | MUX_MODE1) /* gpmc_a4.qspi1_cs3 */ + 0x74 (PIN_INPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk */ + 0x78 (PIN_INPUT | MUX_MODE1) /* gpmc_a14.qspi1_d3 */ + 0x7c (PIN_INPUT | MUX_MODE1) /* gpmc_a15.qspi1_d2 */ + 0x80 (PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */ + 0x84 (PIN_INPUT | MUX_MODE1) /* gpmc_a17.qspi1_d0 */ + 0x88 (PIN_INPUT | MUX_MODE1) /* qpmc_a18.qspi1_sclk */ + 0xb8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs2.qspi1_cs0 */ + 0xbc (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs3.qspi1_cs1 */ + >; + }; + + usb1_pins: pinmux_usb1_pins { + pinctrl-single,pins = < + 0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */ + >; + }; + + usb2_pins: pinmux_usb2_pins { + pinctrl-single,pins = < + 0x284 (PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */ + >; + }; + + nand_flash_x16: nand_flash_x16 { + /* On DRA7 EVM, GPMC_WPN and NAND_BOOTn comes from DIP switch + * So NAND flash requires following switch settings: + * SW5.9 (GPMC_WPN) = LOW + * SW5.1 (NAND_BOOTn) = HIGH */ + pinctrl-single,pins = < + 0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */ + 0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */ + 0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */ + 0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */ + 0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */ + 0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */ + 0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */ + 0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */ + 0x20 (PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */ + 0x24 (PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */ + 0x28 (PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */ + 0x2c (PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */ + 0x30 (PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */ + 0x34 (PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */ + 0x38 (PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */ + 0x3c (PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */ + 0xd8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0 */ + 0xcc (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */ + 0xb4 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_csn0 */ + 0xc4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */ + 0xc8 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */ + 0xd0 (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle */ + >; + }; }; &i2c1 { @@ -273,3 +331,167 @@ &cpu0 { cpu0-supply = <&smps123_reg>; }; + +&qspi { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&qspi1_pins>; + + spi-max-frequency = <48000000>; + m25p80@0 { + compatible = "s25fl256s1"; + spi-max-frequency = <48000000>; + reg = <0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + spi-cpol; + spi-cpha; + #address-cells = <1>; + #size-cells = <1>; + + /* MTD partition table. + * The ROM checks the first four physical blocks + * for a valid file to boot and the flash here is + * 64KiB block size. + */ + partition@0 { + label = "QSPI.SPL"; + reg = <0x00000000 0x000010000>; + }; + partition@1 { + label = "QSPI.SPL.backup1"; + reg = <0x00010000 0x00010000>; + }; + partition@2 { + label = "QSPI.SPL.backup2"; + reg = <0x00020000 0x00010000>; + }; + partition@3 { + label = "QSPI.SPL.backup3"; + reg = <0x00030000 0x00010000>; + }; + partition@4 { + label = "QSPI.u-boot"; + reg = <0x00040000 0x00100000>; + }; + partition@5 { + label = "QSPI.u-boot-spl-os"; + reg = <0x00140000 0x00010000>; + }; + partition@6 { + label = "QSPI.u-boot-env"; + reg = <0x00150000 0x00010000>; + }; + partition@7 { + label = "QSPI.u-boot-env.backup1"; + reg = <0x00160000 0x0010000>; + }; + partition@8 { + label = "QSPI.kernel"; + reg = <0x00170000 0x0800000>; + }; + partition@9 { + label = "QSPI.file-system"; + reg = <0x00970000 0x01690000>; + }; + }; +}; + +&usb1 { + dr_mode = "peripheral"; + pinctrl-names = "default"; + pinctrl-0 = <&usb1_pins>; +}; + +&usb2 { + dr_mode = "host"; + pinctrl-names = "default"; + pinctrl-0 = <&usb2_pins>; +}; + +&elm { + status = "okay"; +}; + +&gpmc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&nand_flash_x16>; + ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */ + nand@0,0 { + reg = <0 0 4>; /* device IO registers */ + ti,nand-ecc-opt = "bch8"; + ti,elm-id = <&elm>; + nand-bus-width = <16>; + gpmc,device-width = <2>; + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <40>; + gpmc,cs-wr-off-ns = <40>; + gpmc,adv-on-ns = <0>; + gpmc,adv-rd-off-ns = <30>; + gpmc,adv-wr-off-ns = <30>; + gpmc,we-on-ns = <5>; + gpmc,we-off-ns = <25>; + gpmc,oe-on-ns = <2>; + gpmc,oe-off-ns = <20>; + gpmc,access-ns = <20>; + gpmc,wr-access-ns = <40>; + gpmc,rd-cycle-ns = <40>; + gpmc,wr-cycle-ns = <40>; + gpmc,wait-pin = <0>; + gpmc,wait-on-read; + gpmc,wait-on-write; + gpmc,bus-turnaround-ns = <0>; + gpmc,cycle2cycle-delay-ns = <0>; + gpmc,clk-activation-ns = <0>; + gpmc,wait-monitoring-ns = <0>; + gpmc,wr-data-mux-bus-ns = <0>; + /* MTD partition table */ + /* All SPL-* partitions are sized to minimal length + * which can be independently programmable. For + * NAND flash this is equal to size of erase-block */ + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "NAND.SPL"; + reg = <0x00000000 0x000020000>; + }; + partition@1 { + label = "NAND.SPL.backup1"; + reg = <0x00020000 0x00020000>; + }; + partition@2 { + label = "NAND.SPL.backup2"; + reg = <0x00040000 0x00020000>; + }; + partition@3 { + label = "NAND.SPL.backup3"; + reg = <0x00060000 0x00020000>; + }; + partition@4 { + label = "NAND.u-boot-spl-os"; + reg = <0x00080000 0x00040000>; + }; + partition@5 { + label = "NAND.u-boot"; + reg = <0x000c0000 0x00100000>; + }; + partition@6 { + label = "NAND.u-boot-env"; + reg = <0x001c0000 0x00020000>; + }; + partition@7 { + label = "NAND.u-boot-env"; + reg = <0x001e0000 0x00020000>; + }; + partition@8 { + label = "NAND.kernel"; + reg = <0x00200000 0x00800000>; + }; + partition@9 { + label = "NAND.file-system"; + reg = <0x00a00000 0x0f600000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 149b55099935..c29945e07c5a 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -33,33 +33,6 @@ serial5 = &uart6; }; - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0>; - - operating-points = < - /* kHz uV */ - 1000000 1060000 - 1176000 1160000 - >; - - clocks = <&dpll_mpu_ck>; - clock-names = "cpu"; - - clock-latency = <300000>; /* From omap-cpufreq driver */ - }; - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <1>; - }; - }; - timer { compatible = "arm,armv7-timer"; interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, @@ -99,13 +72,13 @@ * hierarchy. */ ocp { - compatible = "ti,omap4-l3-noc", "simple-bus"; + compatible = "ti,dra7-l3-noc", "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges; ti,hwmods = "l3_main_1", "l3_main_2"; - reg = <0x44000000 0x2000>, - <0x44800000 0x3000>; + reg = <0x44000000 0x1000000>, + <0x45000000 0x1000>; interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; @@ -789,6 +762,228 @@ dma-names = "tx0", "rx0"; status = "disabled"; }; + + qspi: qspi@4b300000 { + compatible = "ti,dra7xxx-qspi"; + reg = <0x4b300000 0x100>; + reg-names = "qspi_base"; + #address-cells = <1>; + #size-cells = <0>; + ti,hwmods = "qspi"; + clocks = <&qspi_gfclk_div>; + clock-names = "fck"; + num-cs = <4>; + interrupts = <0 343 0x4>; + status = "disabled"; + }; + + omap_control_sata: control-phy@4a002374 { + compatible = "ti,control-phy-pipe3"; + reg = <0x4a002374 0x4>; + reg-names = "power"; + clocks = <&sys_clkin1>; + clock-names = "sysclk"; + }; + + /* OCP2SCP3 */ + ocp2scp@4a090000 { + compatible = "ti,omap-ocp2scp"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + reg = <0x4a090000 0x20>; + ti,hwmods = "ocp2scp3"; + sata_phy: phy@4A096000 { + compatible = "ti,phy-pipe3-sata"; + reg = <0x4A096000 0x80>, /* phy_rx */ + <0x4A096400 0x64>, /* phy_tx */ + <0x4A096800 0x40>; /* pll_ctrl */ + reg-names = "phy_rx", "phy_tx", "pll_ctrl"; + ctrl-module = <&omap_control_sata>; + clocks = <&sys_clkin1>; + clock-names = "sysclk"; + #phy-cells = <0>; + }; + }; + + sata: sata@4a141100 { + compatible = "snps,dwc-ahci"; + reg = <0x4a140000 0x1100>, <0x4a141100 0x7>; + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; + phys = <&sata_phy>; + phy-names = "sata-phy"; + clocks = <&sata_ref_clk>; + ti,hwmods = "sata"; + }; + + omap_control_usb2phy1: control-phy@4a002300 { + compatible = "ti,control-phy-usb2"; + reg = <0x4a002300 0x4>; + reg-names = "power"; + }; + + omap_control_usb3phy1: control-phy@4a002370 { + compatible = "ti,control-phy-pipe3"; + reg = <0x4a002370 0x4>; + reg-names = "power"; + }; + + omap_control_usb2phy2: control-phy@0x4a002e74 { + compatible = "ti,control-phy-usb2-dra7"; + reg = <0x4a002e74 0x4>; + reg-names = "power"; + }; + + /* OCP2SCP1 */ + ocp2scp@4a080000 { + compatible = "ti,omap-ocp2scp"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + reg = <0x4a080000 0x20>; + ti,hwmods = "ocp2scp1"; + + usb2_phy1: phy@4a084000 { + compatible = "ti,omap-usb2"; + reg = <0x4a084000 0x400>; + ctrl-module = <&omap_control_usb2phy1>; + clocks = <&usb_phy1_always_on_clk32k>, + <&usb_otg_ss1_refclk960m>; + clock-names = "wkupclk", + "refclk"; + #phy-cells = <0>; + }; + + usb2_phy2: phy@4a085000 { + compatible = "ti,omap-usb2"; + reg = <0x4a085000 0x400>; + ctrl-module = <&omap_control_usb2phy2>; + clocks = <&usb_phy2_always_on_clk32k>, + <&usb_otg_ss2_refclk960m>; + clock-names = "wkupclk", + "refclk"; + #phy-cells = <0>; + }; + + usb3_phy1: phy@4a084400 { + compatible = "ti,omap-usb3"; + reg = <0x4a084400 0x80>, + <0x4a084800 0x64>, + <0x4a084c00 0x40>; + reg-names = "phy_rx", "phy_tx", "pll_ctrl"; + ctrl-module = <&omap_control_usb3phy1>; + clocks = <&usb_phy3_always_on_clk32k>, + <&sys_clkin1>, + <&usb_otg_ss1_refclk960m>; + clock-names = "wkupclk", + "sysclk", + "refclk"; + #phy-cells = <0>; + }; + }; + + omap_dwc3_1@48880000 { + compatible = "ti,dwc3"; + ti,hwmods = "usb_otg_ss1"; + reg = <0x48880000 0x10000>; + interrupts = <0 77 4>; + #address-cells = <1>; + #size-cells = <1>; + utmi-mode = <2>; + ranges; + usb1: usb@48890000 { + compatible = "snps,dwc3"; + reg = <0x48890000 0x17000>; + interrupts = <0 76 4>; + phys = <&usb2_phy1>, <&usb3_phy1>; + phy-names = "usb2-phy", "usb3-phy"; + tx-fifo-resize; + maximum-speed = "super-speed"; + dr_mode = "otg"; + }; + }; + + omap_dwc3_2@488c0000 { + compatible = "ti,dwc3"; + ti,hwmods = "usb_otg_ss2"; + reg = <0x488c0000 0x10000>; + interrupts = <0 92 4>; + #address-cells = <1>; + #size-cells = <1>; + utmi-mode = <2>; + ranges; + usb2: usb@488d0000 { + compatible = "snps,dwc3"; + reg = <0x488d0000 0x17000>; + interrupts = <0 78 4>; + phys = <&usb2_phy2>; + phy-names = "usb2-phy"; + tx-fifo-resize; + maximum-speed = "high-speed"; + dr_mode = "otg"; + }; + }; + + /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */ + omap_dwc3_3@48900000 { + compatible = "ti,dwc3"; + ti,hwmods = "usb_otg_ss3"; + reg = <0x48900000 0x10000>; + /* interrupts = <0 TBD 4>; */ + #address-cells = <1>; + #size-cells = <1>; + utmi-mode = <2>; + ranges; + status = "disabled"; + usb3: usb@48910000 { + compatible = "snps,dwc3"; + reg = <0x48910000 0x17000>; + /* interrupts = <0 93 4>; */ + tx-fifo-resize; + maximum-speed = "high-speed"; + dr_mode = "otg"; + }; + }; + + omap_dwc3_4@48940000 { + compatible = "ti,dwc3"; + ti,hwmods = "usb_otg_ss4"; + reg = <0x48940000 0x10000>; + /* interrupts = <0 TBD 4>; */ + #address-cells = <1>; + #size-cells = <1>; + utmi-mode = <2>; + ranges; + status = "disabled"; + usb4: usb@48950000 { + compatible = "snps,dwc3"; + reg = <0x48950000 0x17000>; + /* interrupts = <0 TBD 4>; */ + tx-fifo-resize; + maximum-speed = "high-speed"; + dr_mode = "otg"; + }; + }; + + elm: elm@48078000 { + compatible = "ti,am3352-elm"; + reg = <0x48078000 0xfc0>; /* device IO registers */ + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; + ti,hwmods = "elm"; + status = "disabled"; + }; + + gpmc: gpmc@50000000 { + compatible = "ti,am3352-gpmc"; + ti,hwmods = "gpmc"; + reg = <0x50000000 0x37c>; /* device IO registers */ + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + gpmc,num-cs = <8>; + gpmc,num-waitpins = <2>; + #address-cells = <2>; + #size-cells = <1>; + status = "disabled"; + }; }; }; diff --git a/arch/arm/boot/dts/dra72-evm.dts b/arch/arm/boot/dts/dra72-evm.dts new file mode 100644 index 000000000000..514702348818 --- /dev/null +++ b/arch/arm/boot/dts/dra72-evm.dts @@ -0,0 +1,24 @@ +/* + * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +#include "dra72x.dtsi" + +/ { + model = "TI DRA722"; + compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x40000000>; /* 1024 MB */ + }; +}; + +&uart1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/dra72x.dtsi b/arch/arm/boot/dts/dra72x.dtsi new file mode 100644 index 000000000000..f1ec22f6ebf4 --- /dev/null +++ b/arch/arm/boot/dts/dra72x.dtsi @@ -0,0 +1,25 @@ +/* + * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * Based on "omap4.dtsi" + */ + +#include "dra7.dtsi" + +/ { + compatible = "ti,dra722", "ti,dra72", "ti,dra7"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0>; + }; + }; +}; diff --git a/arch/arm/boot/dts/dra74x.dtsi b/arch/arm/boot/dts/dra74x.dtsi new file mode 100644 index 000000000000..a4e8bb9f95c0 --- /dev/null +++ b/arch/arm/boot/dts/dra74x.dtsi @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * Based on "omap4.dtsi" + */ + +#include "dra7.dtsi" + +/ { + compatible = "ti,dra742", "ti,dra74", "ti,dra7"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0>; + + operating-points = < + /* kHz uV */ + 1000000 1060000 + 1176000 1160000 + >; + + clocks = <&dpll_mpu_ck>; + clock-names = "cpu"; + + clock-latency = <300000>; /* From omap-cpufreq driver */ + }; + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <1>; + }; + }; +}; diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi index cfb8fc753f50..c7676871d9c0 100644 --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi @@ -1386,6 +1386,14 @@ ti,dividers = <1>, <8>; }; + l3init_960m_gfclk: l3init_960m_gfclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&dpll_usb_clkdcoldo>; + ti,bit-shift = <8>; + reg = <0x06c0>; + }; + dss_32khz_clk: dss_32khz_clk { #clock-cells = <0>; compatible = "ti,gate-clock"; @@ -1533,7 +1541,7 @@ usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m { #clock-cells = <0>; compatible = "ti,gate-clock"; - clocks = <&dpll_usb_clkdcoldo>; + clocks = <&l3init_960m_gfclk>; ti,bit-shift = <8>; reg = <0x13f0>; }; @@ -1541,7 +1549,7 @@ usb_otg_ss2_refclk960m: usb_otg_ss2_refclk960m { #clock-cells = <0>; compatible = "ti,gate-clock"; - clocks = <&dpll_usb_clkdcoldo>; + clocks = <&l3init_960m_gfclk>; ti,bit-shift = <8>; reg = <0x1340>; }; diff --git a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi new file mode 100644 index 000000000000..47b92c150f4e --- /dev/null +++ b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi @@ -0,0 +1,475 @@ +/* + * Samsung's Exynos3250 SoCs pin-mux and pin-config device tree source + * + * Copyright (c) 2014 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Samsung's Exynos3250 SoCs pin-mux and pin-config optiosn are listed as device + * tree nodes are listed in this file. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +&pinctrl_0 { + gpa0: gpa0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpa1: gpa1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb: gpb { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc0: gpc0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc1: gpc1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd0: gpd0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd1: gpd1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + uart0_data: uart0-data { + samsung,pins = "gpa0-0", "gpa0-1"; + samsung,pin-function = <0x2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + uart0_fctl: uart0-fctl { + samsung,pins = "gpa0-2", "gpa0-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + uart1_data: uart1-data { + samsung,pins = "gpa0-4", "gpa0-5"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + uart1_fctl: uart1-fctl { + samsung,pins = "gpa0-6", "gpa0-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + i2c2_bus: i2c2-bus { + samsung,pins = "gpa0-6", "gpa0-7"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c3_bus: i2c3-bus { + samsung,pins = "gpa1-2", "gpa1-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + spi0_bus: spi0-bus { + samsung,pins = "gpb-0", "gpb-2", "gpb-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c4_bus: i2c4-bus { + samsung,pins = "gpb-0", "gpb-1"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + spi1_bus: spi1-bus { + samsung,pins = "gpb-4", "gpb-6", "gpb-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c5_bus: i2c5-bus { + samsung,pins = "gpb-2", "gpb-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2s2_bus: i2s2-bus { + samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", + "gpc1-4"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + pcm2_bus: pcm2-bus { + samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", + "gpc1-4"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + i2c6_bus: i2c6-bus { + samsung,pins = "gpc1-3", "gpc1-4"; + samsung,pin-function = <4>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + pwm0_out: pwm0-out { + samsung,pins = "gpd0-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + pwm1_out: pwm1-out { + samsung,pins = "gpd0-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + i2c7_bus: i2c7-bus { + samsung,pins = "gpd0-2", "gpd0-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + pwm2_out: pwm2-out { + samsung,pins = "gpd0-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + pwm3_out: pwm3-out { + samsung,pins = "gpd0-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + i2c0_bus: i2c0-bus { + samsung,pins = "gpd1-0", "gpd1-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + mipi0_clk: mipi0-clk { + samsung,pins = "gpd1-0", "gpd1-1"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + i2c1_bus: i2c1-bus { + samsung,pins = "gpd1-2", "gpd1-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; +}; + +&pinctrl_1 { + gpe0: gpe0 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpe1: gpe1 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpe2: gpe2 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpk0: gpk0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpk1: gpk1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpk2: gpk2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpl0: gpl0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpm0: gpm0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpm1: gpm1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpm2: gpm2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpm3: gpm3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpm4: gpm4 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpx0: gpx0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + interrupt-parent = <&gic>; + interrupts = <0 32 0>, <0 33 0>, <0 34 0>, <0 35 0>, + <0 36 0>, <0 37 0>, <0 38 0>, <0 39 0>; + #interrupt-cells = <2>; + }; + + gpx1: gpx1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + interrupt-parent = <&gic>; + interrupts = <0 40 0>, <0 41 0>, <0 42 0>, <0 43 0>, + <0 44 0>, <0 45 0>, <0 46 0>, <0 47 0>; + #interrupt-cells = <2>; + }; + + gpx2: gpx2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpx3: gpx3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + sd0_clk: sd0-clk { + samsung,pins = "gpk0-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd0_cmd: sd0-cmd { + samsung,pins = "gpk0-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd0_cd: sd0-cd { + samsung,pins = "gpk0-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd0_rdqs: sd0-rdqs { + samsung,pins = "gpk0-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd0_bus1: sd0-bus-width1 { + samsung,pins = "gpk0-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd0_bus4: sd0-bus-width4 { + samsung,pins = "gpk0-4", "gpk0-5", "gpk0-6"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd0_bus8: sd0-bus-width8 { + samsung,pins = "gpl0-0", "gpl0-1", "gpl0-2", "gpl0-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd1_clk: sd1-clk { + samsung,pins = "gpk1-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd1_cmd: sd1-cmd { + samsung,pins = "gpk1-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd1_cd: sd1-cd { + samsung,pins = "gpk1-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd1_bus1: sd1-bus-width1 { + samsung,pins = "gpk1-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd1_bus4: sd1-bus-width4 { + samsung,pins = "gpk1-4", "gpk1-5", "gpk1-6"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + cam_port_b_io: cam-port-b-io { + samsung,pins = "gpm0-0", "gpm0-1", "gpm0-2", "gpm0-3", + "gpm0-4", "gpm0-5", "gpm0-6", "gpm0-7", + "gpm1-0", "gpm1-1", "gpm2-0", "gpm2-1"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + cam_port_b_clk_active: cam-port-b-clk-active { + samsung,pins = "gpm2-2"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + cam_port_b_clk_idle: cam-port-b-clk-idle { + samsung,pins = "gpm2-2"; + samsung,pin-function = <0>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + fimc_is_i2c0: fimc-is-i2c0 { + samsung,pins = "gpm4-0", "gpm4-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + fimc_is_i2c1: fimc-is-i2c1 { + samsung,pins = "gpm4-2", "gpm4-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + fimc_is_uart: fimc-is-uart { + samsung,pins = "gpm3-5", "gpm3-7"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; +}; diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi new file mode 100644 index 000000000000..3e678fa335bf --- /dev/null +++ b/arch/arm/boot/dts/exynos3250.dtsi @@ -0,0 +1,444 @@ +/* + * Samsung's Exynos3250 SoC device tree source + * + * Copyright (c) 2014 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Samsung's Exynos3250 SoC device nodes are listed in this file. Exynos3250 + * based board files can include this file and provide values for board specfic + * bindings. + * + * Note: This file does not include device nodes for all the controllers in + * Exynos3250 SoC. As device tree coverage for Exynos3250 increases, additional + * nodes can be added to this file. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "skeleton.dtsi" +#include <dt-bindings/clock/exynos3250.h> + +/ { + compatible = "samsung,exynos3250"; + interrupt-parent = <&gic>; + + aliases { + pinctrl0 = &pinctrl_0; + pinctrl1 = &pinctrl_1; + mshc0 = &mshc_0; + mshc1 = &mshc_1; + spi0 = &spi_0; + spi1 = &spi_1; + i2c0 = &i2c_0; + i2c1 = &i2c_1; + i2c2 = &i2c_2; + i2c3 = &i2c_3; + i2c4 = &i2c_4; + i2c5 = &i2c_5; + i2c6 = &i2c_6; + i2c7 = &i2c_7; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0>; + clock-frequency = <1000000000>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <1>; + clock-frequency = <1000000000>; + }; + }; + + soc: soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + fixed-rate-clocks { + #address-cells = <1>; + #size-cells = <0>; + + xusbxti: clock@0 { + compatible = "fixed-clock"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + clock-frequency = <0>; + #clock-cells = <0>; + clock-output-names = "xusbxti"; + }; + + xxti: clock@1 { + compatible = "fixed-clock"; + reg = <1>; + clock-frequency = <0>; + #clock-cells = <0>; + clock-output-names = "xxti"; + }; + + xtcxo: clock@2 { + compatible = "fixed-clock"; + reg = <2>; + clock-frequency = <0>; + #clock-cells = <0>; + clock-output-names = "xtcxo"; + }; + }; + + sysram@02020000 { + compatible = "mmio-sram"; + reg = <0x02020000 0x40000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x02020000 0x40000>; + + smp-sysram@0 { + compatible = "samsung,exynos4210-sysram"; + reg = <0x0 0x1000>; + }; + + smp-sysram@3f000 { + compatible = "samsung,exynos4210-sysram-ns"; + reg = <0x3f000 0x1000>; + }; + }; + + chipid@10000000 { + compatible = "samsung,exynos4210-chipid"; + reg = <0x10000000 0x100>; + }; + + sys_reg: syscon@10010000 { + compatible = "samsung,exynos3-sysreg", "syscon"; + reg = <0x10010000 0x400>; + }; + + pmu_system_controller: system-controller@10020000 { + compatible = "samsung,exynos3250-pmu", "syscon"; + reg = <0x10020000 0x4000>; + }; + + pd_cam: cam-power-domain@10023C00 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10023C00 0x20>; + }; + + pd_mfc: mfc-power-domain@10023C40 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10023C40 0x20>; + }; + + pd_g3d: g3d-power-domain@10023C60 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10023C60 0x20>; + }; + + pd_lcd0: lcd0-power-domain@10023C80 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10023C80 0x20>; + }; + + pd_isp: isp-power-domain@10023CA0 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10023CA0 0x20>; + }; + + cmu: clock-controller@10030000 { + compatible = "samsung,exynos3250-cmu"; + reg = <0x10030000 0x20000>; + #clock-cells = <1>; + }; + + rtc: rtc@10070000 { + compatible = "samsung,s3c6410-rtc"; + reg = <0x10070000 0x100>; + interrupts = <0 73 0>, <0 74 0>; + status = "disabled"; + }; + + gic: interrupt-controller@10481000 { + compatible = "arm,cortex-a15-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x10481000 0x1000>, + <0x10482000 0x1000>, + <0x10484000 0x2000>, + <0x10486000 0x2000>; + interrupts = <1 9 0xf04>; + }; + + mct@10050000 { + compatible = "samsung,exynos4210-mct"; + reg = <0x10050000 0x800>; + interrupts = <0 218 0>, <0 219 0>, <0 220 0>, <0 221 0>, + <0 223 0>, <0 226 0>, <0 227 0>, <0 228 0>; + clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>; + clock-names = "fin_pll", "mct"; + }; + + pinctrl_1: pinctrl@11000000 { + compatible = "samsung,exynos3250-pinctrl"; + reg = <0x11000000 0x1000>; + interrupts = <0 225 0>; + + wakeup-interrupt-controller { + compatible = "samsung,exynos4210-wakeup-eint"; + interrupt-parent = <&gic>; + interrupts = <0 48 0>; + }; + }; + + pinctrl_0: pinctrl@11400000 { + compatible = "samsung,exynos3250-pinctrl"; + reg = <0x11400000 0x1000>; + interrupts = <0 240 0>; + }; + + mshc_0: mshc@12510000 { + compatible = "samsung,exynos5250-dw-mshc"; + reg = <0x12510000 0x1000>; + interrupts = <0 142 0>; + clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>; + clock-names = "biu", "ciu"; + fifo-depth = <0x80>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + mshc_1: mshc@12520000 { + compatible = "samsung,exynos5250-dw-mshc"; + reg = <0x12520000 0x1000>; + interrupts = <0 143 0>; + clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>; + clock-names = "biu", "ciu"; + fifo-depth = <0x80>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + amba { + compatible = "arm,amba-bus"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; + ranges; + + pdma0: pdma@12680000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x12680000 0x1000>; + interrupts = <0 138 0>; + clocks = <&cmu CLK_PDMA0>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; + }; + + pdma1: pdma@12690000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x12690000 0x1000>; + interrupts = <0 139 0>; + clocks = <&cmu CLK_PDMA1>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; + }; + }; + + adc: adc@126C0000 { + compatible = "samsung,exynos-adc-v3"; + reg = <0x126C0000 0x100>, <0x10020718 0x4>; + interrupts = <0 137 0>; + clock-names = "adc", "sclk_tsadc"; + clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>; + #io-channel-cells = <1>; + io-channel-ranges; + status = "disabled"; + }; + + serial_0: serial@13800000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x13800000 0x100>; + interrupts = <0 109 0>; + clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>; + clock-names = "uart", "clk_uart_baud0"; + status = "disabled"; + }; + + serial_1: serial@13810000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x13810000 0x100>; + interrupts = <0 110 0>; + clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>; + clock-names = "uart", "clk_uart_baud0"; + status = "disabled"; + }; + + i2c_0: i2c@13860000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + reg = <0x13860000 0x100>; + interrupts = <0 113 0>; + clocks = <&cmu CLK_I2C0>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_bus>; + status = "disabled"; + }; + + i2c_1: i2c@13870000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + reg = <0x13870000 0x100>; + interrupts = <0 114 0>; + clocks = <&cmu CLK_I2C1>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_bus>; + status = "disabled"; + }; + + i2c_2: i2c@13880000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + reg = <0x13880000 0x100>; + interrupts = <0 115 0>; + clocks = <&cmu CLK_I2C2>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_bus>; + status = "disabled"; + }; + + i2c_3: i2c@13890000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + reg = <0x13890000 0x100>; + interrupts = <0 116 0>; + clocks = <&cmu CLK_I2C3>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_bus>; + status = "disabled"; + }; + + i2c_4: i2c@138A0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + reg = <0x138A0000 0x100>; + interrupts = <0 117 0>; + clocks = <&cmu CLK_I2C4>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_bus>; + status = "disabled"; + }; + + i2c_5: i2c@138B0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + reg = <0x138B0000 0x100>; + interrupts = <0 118 0>; + clocks = <&cmu CLK_I2C5>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_bus>; + status = "disabled"; + }; + + i2c_6: i2c@138C0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + reg = <0x138C0000 0x100>; + interrupts = <0 119 0>; + clocks = <&cmu CLK_I2C6>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6_bus>; + status = "disabled"; + }; + + i2c_7: i2c@138D0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + reg = <0x138D0000 0x100>; + interrupts = <0 120 0>; + clocks = <&cmu CLK_I2C7>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c7_bus>; + status = "disabled"; + }; + + spi_0: spi@13920000 { + compatible = "samsung,exynos4210-spi"; + reg = <0x13920000 0x100>; + interrupts = <0 121 0>; + dmas = <&pdma0 7>, <&pdma0 6>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>; + clock-names = "spi", "spi_busclk0"; + samsung,spi-src-clk = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_bus>; + status = "disabled"; + }; + + spi_1: spi@13930000 { + compatible = "samsung,exynos4210-spi"; + reg = <0x13930000 0x100>; + interrupts = <0 122 0>; + dmas = <&pdma1 7>, <&pdma1 6>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>; + clock-names = "spi", "spi_busclk0"; + samsung,spi-src-clk = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_bus>; + status = "disabled"; + }; + + pwm: pwm@139D0000 { + compatible = "samsung,exynos4210-pwm"; + reg = <0x139D0000 0x1000>; + interrupts = <0 104 0>, <0 105 0>, <0 106 0>, + <0 107 0>, <0 108 0>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = <0 18 0>, <0 19 0>; + }; + }; +}; + +#include "exynos3250-pinctrl.dtsi" diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi index 2f8bcd068d17..b8ece4be41ca 100644 --- a/arch/arm/boot/dts/exynos4.dtsi +++ b/arch/arm/boot/dts/exynos4.dtsi @@ -20,6 +20,7 @@ */ #include <dt-bindings/clock/exynos4.h> +#include <dt-bindings/clock/exynos-audss-clk.h> #include "skeleton.dtsi" / { @@ -45,6 +46,23 @@ fimc3 = &fimc_3; }; + clock_audss: clock-controller@03810000 { + compatible = "samsung,exynos4210-audss-clock"; + reg = <0x03810000 0x0C>; + #clock-cells = <1>; + }; + + i2s0: i2s@03830000 { + compatible = "samsung,s5pv210-i2s"; + reg = <0x03830000 0x100>; + clocks = <&clock_audss EXYNOS_I2S_BUS>; + clock-names = "iis"; + dmas = <&pdma0 12>, <&pdma0 11>, <&pdma0 10>; + dma-names = "tx", "rx", "tx-sec"; + samsung,idma-addr = <0x03000000>; + status = "disabled"; + }; + chipid@10000000 { compatible = "samsung,exynos4210-chipid"; reg = <0x10000000 0x100>; @@ -110,6 +128,11 @@ reg = <0x10010000 0x400>; }; + pmu_system_controller: system-controller@10020000 { + compatible = "samsung,exynos4210-pmu", "syscon"; + reg = <0x10020000 0x4000>; + }; + dsi_0: dsi@11C80000 { compatible = "samsung,exynos4210-mipi-dsi"; reg = <0x11C80000 0x10000>; @@ -117,7 +140,7 @@ samsung,power-domain = <&pd_lcd0>; phys = <&mipi_phy 1>; phy-names = "dsim"; - clocks = <&clock 286>, <&clock 143>; + clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI0>; clock-names = "bus_clk", "pll_clk"; status = "disabled"; #address-cells = <1>; @@ -129,12 +152,10 @@ status = "disabled"; #address-cells = <1>; #size-cells = <1>; + #clock-cells = <1>; + clock-output-names = "cam_a_clkout", "cam_b_clkout"; ranges; - clock_cam: clock-controller { - #clock-cells = <1>; - }; - fimc_0: fimc@11800000 { compatible = "samsung,exynos4210-fimc"; reg = <0x11800000 0x1000>; @@ -273,6 +294,27 @@ status = "disabled"; }; + exynos_usbphy: exynos-usbphy@125B0000 { + compatible = "samsung,exynos4210-usb2-phy"; + reg = <0x125B0000 0x100>; + samsung,pmureg-phandle = <&pmu_system_controller>; + clocks = <&clock CLK_USB_DEVICE>, <&clock CLK_XUSBXTI>; + clock-names = "phy", "ref"; + #phy-cells = <1>; + status = "disabled"; + }; + + hsotg@12480000 { + compatible = "samsung,s3c6400-hsotg"; + reg = <0x12480000 0x20000>; + interrupts = <0 71 0>; + clocks = <&clock CLK_USB_DEVICE>; + clock-names = "otg"; + phys = <&exynos_usbphy 0>; + phy-names = "usb2-phy"; + status = "disabled"; + }; + ehci@12580000 { compatible = "samsung,exynos4210-ehci"; reg = <0x12580000 0x100>; @@ -291,6 +333,26 @@ status = "disabled"; }; + i2s1: i2s@13960000 { + compatible = "samsung,s5pv210-i2s"; + reg = <0x13960000 0x100>; + clocks = <&clock CLK_I2S1>; + clock-names = "iis"; + dmas = <&pdma1 12>, <&pdma1 11>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + i2s2: i2s@13970000 { + compatible = "samsung,s5pv210-i2s"; + reg = <0x13970000 0x100>; + clocks = <&clock CLK_I2S2>; + clock-names = "iis"; + dmas = <&pdma0 14>, <&pdma0 13>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + mfc: codec@13400000 { compatible = "samsung,mfc-v5"; reg = <0x13400000 0x10000>; @@ -371,6 +433,8 @@ interrupts = <0 60 0>; clocks = <&clock CLK_I2C2>; clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_bus>; status = "disabled"; }; @@ -382,6 +446,8 @@ interrupts = <0 61 0>; clocks = <&clock CLK_I2C3>; clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_bus>; status = "disabled"; }; @@ -393,6 +459,8 @@ interrupts = <0 62 0>; clocks = <&clock CLK_I2C4>; clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_bus>; status = "disabled"; }; @@ -404,6 +472,8 @@ interrupts = <0 63 0>; clocks = <&clock CLK_I2C5>; clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_bus>; status = "disabled"; }; @@ -415,6 +485,8 @@ interrupts = <0 64 0>; clocks = <&clock CLK_I2C6>; clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6_bus>; status = "disabled"; }; @@ -426,6 +498,8 @@ interrupts = <0 65 0>; clocks = <&clock CLK_I2C7>; clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c7_bus>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts index 72fb11f7ea21..f767c425d0b5 100644 --- a/arch/arm/boot/dts/exynos4210-origen.dts +++ b/arch/arm/boot/dts/exynos4210-origen.dts @@ -16,6 +16,7 @@ /dts-v1/; #include "exynos4210.dtsi" +#include <dt-bindings/input/input.h> / { model = "Insignal Origen evaluation board based on Exynos4210"; @@ -48,6 +49,14 @@ }; }; + watchdog@10060000 { + status = "okay"; + }; + + rtc@10070000 { + status = "okay"; + }; + tmu@100C0000 { status = "okay"; }; @@ -251,35 +260,35 @@ up { label = "Up"; gpios = <&gpx2 0 1>; - linux,code = <103>; + linux,code = <KEY_UP>; gpio-key,wakeup; }; down { label = "Down"; gpios = <&gpx2 1 1>; - linux,code = <108>; + linux,code = <KEY_DOWN>; gpio-key,wakeup; }; back { label = "Back"; gpios = <&gpx1 7 1>; - linux,code = <158>; + linux,code = <KEY_BACK>; gpio-key,wakeup; }; home { label = "Home"; gpios = <&gpx1 6 1>; - linux,code = <102>; + linux,code = <KEY_HOME>; gpio-key,wakeup; }; menu { label = "Menu"; gpios = <&gpx1 5 1>; - linux,code = <139>; + linux,code = <KEY_MENU>; gpio-key,wakeup; }; }; diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts index 63aa2bb24a4b..f516da9e8b3a 100644 --- a/arch/arm/boot/dts/exynos4210-trats.dts +++ b/arch/arm/boot/dts/exynos4210-trats.dts @@ -88,6 +88,12 @@ }; }; + hsotg@12480000 { + vusb_d-supply = <&vusb_reg>; + vusb_a-supply = <&vusbdac_reg>; + status = "okay"; + }; + sdhci_emmc: sdhci@12510000 { bus-width = <8>; non-removable; @@ -97,6 +103,10 @@ status = "okay"; }; + exynos-usbphy@125B0000 { + status = "okay"; + }; + serial@13800000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts b/arch/arm/boot/dts/exynos4210-universal_c210.dts index 63e34b24b04f..d50eb3aa708e 100644 --- a/arch/arm/boot/dts/exynos4210-universal_c210.dts +++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts @@ -28,6 +28,21 @@ bootargs = "console=ttySAC2,115200N8 root=/dev/mmcblk0p5 rw rootwait earlyprintk panic=5 maxcpus=1"; }; + sysram@02020000 { + smp-sysram@0 { + status = "disabled"; + }; + + smp-sysram@5000 { + compatible = "samsung,exynos4210-sysram"; + reg = <0x5000 0x1000>; + }; + + smp-sysram@1f000 { + status = "disabled"; + }; + }; + mct@10050000 { compatible = "none"; }; @@ -53,6 +68,12 @@ enable-active-high; }; + hsotg@12480000 { + vusb_d-supply = <&ldo3_reg>; + vusb_a-supply = <&ldo8_reg>; + status = "okay"; + }; + sdhci_emmc: sdhci@12510000 { bus-width = <8>; non-removable; @@ -62,6 +83,34 @@ status = "okay"; }; + sdhci_sd: sdhci@12530000 { + bus-width = <4>; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4>; + pinctrl-names = "default"; + vmmc-supply = <&ldo5_reg>; + cd-gpios = <&gpx3 4 0>; + cd-inverted; + status = "okay"; + }; + + ehci@12580000 { + status = "okay"; + port@0 { + status = "okay"; + }; + }; + + ohci@12590000 { + status = "okay"; + port@0 { + status = "okay"; + }; + }; + + exynos-usbphy@125B0000 { + status = "okay"; + }; + serial@13800000 { status = "okay"; }; @@ -201,6 +250,7 @@ regulator-name = "VUSB+MIPI_1.1V"; regulator-min-microvolt = <1100000>; regulator-max-microvolt = <1100000>; + regulator-always-on; }; ldo4_reg: LDO4 { @@ -231,6 +281,7 @@ regulator-name = "VUSB+VDAC_3.3V"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; + regulator-always-on; }; ldo9_reg: LDO9 { @@ -413,6 +464,29 @@ compatible = "samsung,s5p6440-pwm"; status = "okay"; }; + + camera { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <>; + + fimc_0: fimc@11800000 { + status = "okay"; + }; + + fimc_1: fimc@11810000 { + status = "okay"; + }; + + fimc_2: fimc@11820000 { + status = "okay"; + }; + + fimc_3: fimc@11830000 { + status = "okay"; + }; + }; }; &mdma1 { diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi index cacf6140dd2f..ee3001f38821 100644 --- a/arch/arm/boot/dts/exynos4210.dtsi +++ b/arch/arm/boot/dts/exynos4210.dtsi @@ -31,6 +31,24 @@ pinctrl2 = &pinctrl_2; }; + sysram@02020000 { + compatible = "mmio-sram"; + reg = <0x02020000 0x20000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x02020000 0x20000>; + + smp-sysram@0 { + compatible = "samsung,exynos4210-sysram"; + reg = <0x0 0x1000>; + }; + + smp-sysram@1f000 { + compatible = "samsung,exynos4210-sysram-ns"; + reg = <0x1f000 0x1000>; + }; + }; + pd_lcd1: lcd1-power-domain@10023CA0 { compatible = "samsung,exynos4210-pd"; reg = <0x10023CA0 0x20>; diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts index e2c0dcab4d81..e925c9fbfb07 100644 --- a/arch/arm/boot/dts/exynos4412-origen.dts +++ b/arch/arm/boot/dts/exynos4412-origen.dts @@ -14,6 +14,7 @@ /dts-v1/; #include "exynos4412.dtsi" +#include <dt-bindings/input/input.h> / { model = "Insignal Origen evaluation board based on Exynos4412"; @@ -48,6 +49,14 @@ }; }; + watchdog@10060000 { + status = "okay"; + }; + + rtc@10070000 { + status = "okay"; + }; + pinctrl@11000000 { keypad_rows: keypad-rows { samsung,pins = "gpx2-0", "gpx2-1", "gpx2-2"; @@ -76,37 +85,37 @@ key_home { keypad,row = <0>; keypad,column = <0>; - linux,code = <102>; + linux,code = <KEY_HOME>; }; key_down { keypad,row = <0>; keypad,column = <1>; - linux,code = <108>; + linux,code = <KEY_DOWN>; }; key_up { keypad,row = <1>; keypad,column = <0>; - linux,code = <103>; + linux,code = <KEY_UP>; }; key_menu { keypad,row = <1>; keypad,column = <1>; - linux,code = <139>; + linux,code = <KEY_MENU>; }; key_back { keypad,row = <2>; keypad,column = <0>; - linux,code = <158>; + linux,code = <KEY_BACK>; }; key_enter { keypad,row = <2>; keypad,column = <1>; - linux,code = <28>; + linux,code = <KEY_ENTER>; }; }; diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts b/arch/arm/boot/dts/exynos4412-trats2.dts index 8a558b7ac999..77878447b312 100644 --- a/arch/arm/boot/dts/exynos4412-trats2.dts +++ b/arch/arm/boot/dts/exynos4412-trats2.dts @@ -20,7 +20,8 @@ compatible = "samsung,trats2", "samsung,exynos4412", "samsung,exynos4"; aliases { - i2c8 = &i2c_ak8975; + i2c9 = &i2c_ak8975; + i2c10 = &i2c_cm36651; }; memory { @@ -80,39 +81,67 @@ enable-active-high; }; - /* More to come */ + cam_af_reg: voltage-regulator-3 { + compatible = "regulator-fixed"; + regulator-name = "CAM_AF"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpm0 4 0>; + enable-active-high; + }; + + cam_isp_core_reg: voltage-regulator-4 { + compatible = "regulator-fixed"; + regulator-name = "CAM_ISP_CORE_1.2V_EN"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + gpio = <&gpm0 3 0>; + enable-active-high; + regulator-always-on; + }; + + ps_als_reg: voltage-regulator-5 { + compatible = "regulator-fixed"; + regulator-name = "LED_A_3.0V"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpj0 5 0>; + enable-active-high; + }; }; gpio-keys { compatible = "gpio-keys"; key-down { - interrupt-parent = <&gpj1>; - interrupts = <2 0>; - gpios = <&gpj1 2 1>; + gpios = <&gpx3 3 1>; linux,code = <114>; label = "volume down"; debounce-interval = <10>; }; key-up { - interrupt-parent = <&gpj1>; - interrupts = <1 0>; - gpios = <&gpj1 1 1>; + gpios = <&gpx2 2 1>; linux,code = <115>; label = "volume up"; debounce-interval = <10>; }; key-power { - interrupt-parent = <&gpx2>; - interrupts = <7 0>; gpios = <&gpx2 7 1>; linux,code = <116>; label = "power"; debounce-interval = <10>; gpio-key,wakeup; }; + + key-ok { + gpios = <&gpx0 1 1>; + linux,code = <139>; + label = "ok"; + debounce-inteval = <10>; + gpio-key,wakeup; + }; }; adc: adc@126C0000 { @@ -140,6 +169,38 @@ }; }; + i2c_0: i2c@13860000 { + samsung,i2c-sda-delay = <100>; + samsung,i2c-slave-addr = <0x10>; + samsung,i2c-max-bus-freq = <400000>; + pinctrl-0 = <&i2c0_bus>; + pinctrl-names = "default"; + status = "okay"; + + s5c73m3@3c { + compatible = "samsung,s5c73m3"; + reg = <0x3c>; + standby-gpios = <&gpm0 1 1>; /* ISP_STANDBY */ + xshutdown-gpios = <&gpf1 3 1>; /* ISP_RESET */ + vdd-int-supply = <&buck9_reg>; + vddio-cis-supply = <&ldo9_reg>; + vdda-supply = <&ldo17_reg>; + vddio-host-supply = <&ldo18_reg>; + vdd-af-supply = <&cam_af_reg>; + vdd-reg-supply = <&cam_io_reg>; + clock-frequency = <24000000>; + /* CAM_A_CLKOUT */ + clocks = <&camera 0>; + clock-names = "cis_extclk"; + port { + s5c73m3_ep: endpoint { + remote-endpoint = <&csis0_ep>; + data-lanes = <1 2 3 4>; + }; + }; + }; + }; + i2c@138D0000 { samsung,i2c-sda-delay = <100>; samsung,i2c-slave-addr = <0x10>; @@ -509,6 +570,22 @@ }; }; + i2c_cm36651: i2c-gpio-2 { + compatible = "i2c-gpio"; + gpios = <&gpf0 0 1>, <&gpf0 1 1>; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + + cm36651@18 { + compatible = "capella,cm36651"; + reg = <0x18>; + interrupt-parent = <&gpx0>; + interrupts = <2 2>; + vled-supply = <&ps_als_reg>; + }; + }; + spi_1: spi@13930000 { pinctrl-names = "default"; pinctrl-0 = <&spi1_bus>; @@ -586,8 +663,8 @@ status = "okay"; }; - camera { - pinctrl-0 = <&cam_port_b_clk_active>; + camera: camera { + pinctrl-0 = <&cam_port_a_clk_active &cam_port_b_clk_active>; pinctrl-names = "default"; status = "okay"; @@ -607,6 +684,23 @@ status = "okay"; }; + csis_0: csis@11880000 { + status = "okay"; + vddcore-supply = <&ldo8_reg>; + vddio-supply = <&ldo10_reg>; + clock-frequency = <176000000>; + + /* Camera C (3) MIPI CSI-2 (CSIS0) */ + port@3 { + reg = <3>; + csis0_ep: endpoint { + remote-endpoint = <&s5c73m3_ep>; + data-lanes = <1 2 3 4>; + samsung,csis-hs-settle = <12>; + }; + }; + }; + csis_1: csis@11890000 { vddcore-supply = <&ldo8_reg>; vddio-supply = <&ldo10_reg>; @@ -647,10 +741,11 @@ reg = <0x10>; svdda-supply = <&cam_io_reg>; svddio-supply = <&ldo19_reg>; + afvdd-supply = <&ldo19_reg>; clock-frequency = <24000000>; /* CAM_B_CLKOUT */ - clocks = <&clock_cam 1>; - clock-names = "mclk"; + clocks = <&camera 1>; + clock-names = "extclk"; samsung,camclk-out = <1>; gpios = <&gpm1 6 0>; @@ -665,6 +760,16 @@ }; }; + exynos-usbphy@125B0000 { + status = "okay"; + }; + + hsotg@12480000 { + vusb_d-supply = <&ldo15_reg>; + vusb_a-supply = <&ldo12_reg>; + status = "okay"; + }; + thermistor-ap@0 { compatible = "ntc,ncp15wb473"; pullup-uv = <1800000>; /* VCC_1.8V_AP */ diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi index 15d3c0ac2f5f..c42a3e196cd5 100644 --- a/arch/arm/boot/dts/exynos4412.dtsi +++ b/arch/arm/boot/dts/exynos4412.dtsi @@ -29,4 +29,8 @@ gic: interrupt-controller@10490000 { cpu-offset = <0x4000>; }; + + pmu_system_controller: system-controller@10020000 { + compatible = "samsung,exynos4412-pmu", "syscon"; + }; }; diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi index c4a9306f8529..c5a943df1cd7 100644 --- a/arch/arm/boot/dts/exynos4x12.dtsi +++ b/arch/arm/boot/dts/exynos4x12.dtsi @@ -37,6 +37,24 @@ interrupts = <2 2>, <3 2>, <18 2>, <19 2>; }; + sysram@02020000 { + compatible = "mmio-sram"; + reg = <0x02020000 0x40000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x02020000 0x40000>; + + smp-sysram@0 { + compatible = "samsung,exynos4210-sysram"; + reg = <0x0 0x1000>; + }; + + smp-sysram@2f000 { + compatible = "samsung,exynos4210-sysram-ns"; + reg = <0x2f000 0x1000>; + }; + }; + pd_isp: isp-power-domain@10023CA0 { compatible = "samsung,exynos4210-pd"; reg = <0x10023CA0 0x20>; @@ -119,6 +137,10 @@ interrupts = <0 72 0>; }; + pmu_system_controller: system-controller@10020000 { + compatible = "samsung,exynos4212-pmu", "syscon"; + }; + g2d@10800000 { compatible = "samsung,exynos4212-g2d"; reg = <0x10800000 0x1000>; @@ -243,4 +265,9 @@ clock-names = "biu", "ciu"; status = "disabled"; }; + + exynos-usbphy@125B0000 { + compatible = "samsung,exynos4x12-usb2-phy"; + samsung,sysreg-phandle = <&sys_reg>; + }; }; diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts index cde19c818667..d0de1f50d15b 100644 --- a/arch/arm/boot/dts/exynos5250-arndale.dts +++ b/arch/arm/boot/dts/exynos5250-arndale.dts @@ -12,6 +12,7 @@ /dts-v1/; #include "exynos5250.dtsi" #include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/input/input.h> / { model = "Insignal Arndale evaluation board based on EXYNOS5250"; @@ -445,42 +446,42 @@ menu { label = "SW-TACT2"; gpios = <&gpx1 4 1>; - linux,code = <139>; + linux,code = <KEY_MENU>; gpio-key,wakeup; }; home { label = "SW-TACT3"; gpios = <&gpx1 5 1>; - linux,code = <102>; + linux,code = <KEY_HOME>; gpio-key,wakeup; }; up { label = "SW-TACT4"; gpios = <&gpx1 6 1>; - linux,code = <103>; + linux,code = <KEY_UP>; gpio-key,wakeup; }; down { label = "SW-TACT5"; gpios = <&gpx1 7 1>; - linux,code = <108>; + linux,code = <KEY_DOWN>; gpio-key,wakeup; }; back { label = "SW-TACT6"; gpios = <&gpx2 0 1>; - linux,code = <158>; + linux,code = <KEY_BACK>; gpio-key,wakeup; }; wakeup { label = "SW-TACT7"; gpios = <&gpx2 1 1>; - linux,code = <143>; + linux,code = <KEY_WAKEUP>; gpio-key,wakeup; }; }; diff --git a/arch/arm/boot/dts/exynos5250-cros-common.dtsi b/arch/arm/boot/dts/exynos5250-cros-common.dtsi index 2c1560d52f1a..89ac90f59e2e 100644 --- a/arch/arm/boot/dts/exynos5250-cros-common.dtsi +++ b/arch/arm/boot/dts/exynos5250-cros-common.dtsi @@ -240,7 +240,7 @@ samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <378000>; - hdmiphy@38 { + hdmiphy: hdmiphy@38 { compatible = "samsung,exynos4212-hdmiphy"; reg = <0x38>; }; @@ -304,6 +304,10 @@ hdmi { hpd-gpio = <&gpx3 7 0>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_hpd_irq>; + phy = <&hdmiphy>; + ddc = <&i2c_2>; }; gpio-keys { diff --git a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi b/arch/arm/boot/dts/exynos5250-pinctrl.dtsi index 9a49e6804ae1..886cfca044ac 100644 --- a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos5250-pinctrl.dtsi @@ -351,6 +351,34 @@ samsung,pin-drv = <0>; }; + pwm0_out: pwm0-out { + samsung,pins = "gpb2-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + pwm1_out: pwm1-out { + samsung,pins = "gpb2-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + pwm2_out: pwm2-out { + samsung,pins = "gpb2-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + pwm3_out: pwm3-out { + samsung,pins = "gpb2-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + i2c7_bus: i2c7-bus { samsung,pins = "gpb2-2", "gpb2-3"; samsung,pin-function = <3>; diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts index 1ce1088a00fb..079fdf9e3f18 100644 --- a/arch/arm/boot/dts/exynos5250-snow.dts +++ b/arch/arm/boot/dts/exynos5250-snow.dts @@ -25,6 +25,13 @@ }; pinctrl@11400000 { + ec_irq: ec-irq { + samsung,pins = "gpx1-6"; + samsung,pin-function = <0>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + sd3_clk: sd3-clk { samsung,pin-drv = <0>; }; @@ -37,6 +44,50 @@ sd3_bus4: sd3-bus-width4 { samsung,pin-drv = <0>; }; + + max98095_en: max98095-en { + samsung,pins = "gpx1-7"; + samsung,pin-function = <0>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + tps65090_irq: tps65090-irq { + samsung,pins = "gpx2-6"; + samsung,pin-function = <0>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + usb3_vbus_en: usb3-vbus-en { + samsung,pins = "gpx2-7"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + hdmi_hpd_irq: hdmi-hpd-irq { + samsung,pins = "gpx3-7"; + samsung,pin-function = <0>; + samsung,pin-pud = <1>; + samsung,pin-drv = <0>; + }; + }; + + pinctrl@13400000 { + arb_their_claim: arb-their-claim { + samsung,pins = "gpe0-4"; + samsung,pin-function = <0>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + arb_our_claim: arb-our-claim { + samsung,pins = "gpf0-3"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; }; gpio-keys { @@ -52,6 +103,12 @@ }; }; + vbat: vbat-fixed-regulator { + compatible = "regulator-fixed"; + regulator-name = "vbat-supply"; + regulator-boot-on; + }; + i2c-arbitrator { compatible = "i2c-arb-gpio-challenge"; #address-cells = <1>; @@ -65,6 +122,9 @@ wait-retry-us = <3000>; wait-free-us = <50000>; + pinctrl-names = "default"; + pinctrl-0 = <&arb_our_claim &arb_their_claim>; + /* Use ID 104 as a hint that we're on physical bus 4 */ i2c_104: i2c@0 { reg = <0>; @@ -82,6 +142,8 @@ reg = <0x1e>; interrupts = <6 0>; interrupt-parent = <&gpx1>; + pinctrl-names = "default"; + pinctrl-0 = <&ec_irq>; wakeup-source; keyboard-controller { @@ -173,6 +235,83 @@ 0x070c0069>; /* LEFT */ }; }; + + power-regulator { + compatible = "ti,tps65090"; + reg = <0x48>; + + /* + * Config irq to disable internal pulls + * even though we run in polling mode. + */ + pinctrl-names = "default"; + pinctrl-0 = <&tps65090_irq>; + + vsys1-supply = <&vbat>; + vsys2-supply = <&vbat>; + vsys3-supply = <&vbat>; + infet1-supply = <&vbat>; + infet2-supply = <&vbat>; + infet3-supply = <&vbat>; + infet4-supply = <&vbat>; + infet5-supply = <&vbat>; + infet6-supply = <&vbat>; + infet7-supply = <&vbat>; + vsys-l1-supply = <&vbat>; + vsys-l2-supply = <&vbat>; + + regulators { + dcdc1 { + ti,enable-ext-control; + }; + dcdc2 { + ti,enable-ext-control; + }; + dcdc3 { + ti,enable-ext-control; + }; + fet1 { + regulator-name = "vcd_led"; + ti,overcurrent-wait = <3>; + }; + tps65090_fet2: fet2 { + regulator-name = "video_mid"; + regulator-always-on; + ti,overcurrent-wait = <3>; + }; + fet3 { + regulator-name = "wwan_r"; + regulator-always-on; + ti,overcurrent-wait = <3>; + }; + fet4 { + regulator-name = "sdcard"; + ti,overcurrent-wait = <3>; + }; + fet5 { + regulator-name = "camout"; + regulator-always-on; + ti,overcurrent-wait = <3>; + }; + fet6 { + regulator-name = "lcd_vdd"; + ti,overcurrent-wait = <3>; + }; + tps65090_fet7: fet7 { + regulator-name = "video_mid_1a"; + regulator-always-on; + ti,overcurrent-wait = <3>; + }; + ldo1 { + }; + ldo2 { + }; + }; + + charger { + compatible = "ti,tps65090-charger"; + }; + }; }; }; @@ -196,6 +335,41 @@ }; }; + i2c@12CD0000 { + max98095: codec@11 { + compatible = "maxim,max98095"; + reg = <0x11>; + pinctrl-0 = <&max98095_en>; + pinctrl-names = "default"; + }; + }; + + i2s0: i2s@03830000 { + status = "okay"; + }; + + sound { + compatible = "google,snow-audio-max98095"; + + samsung,i2s-controller = <&i2s0>; + samsung,audio-codec = <&max98095>; + }; + + usb3_vbus_reg: regulator-usb3 { + compatible = "regulator-fixed"; + regulator-name = "P5.0V_USB3CON"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpx2 7 0>; + pinctrl-names = "default"; + pinctrl-0 = <&usb3_vbus_en>; + enable-active-high; + }; + + phy@12100000 { + vbus-supply = <&usb3_vbus_reg>; + }; + usb@12110000 { samsung,vbus-gpio = <&gpx1 1 0>; }; @@ -206,4 +380,54 @@ clock-frequency = <24000000>; }; }; + + hdmi { + hdmi-en-supply = <&tps65090_fet7>; + vdd-supply = <&ldo8_reg>; + vdd_osc-supply = <&ldo10_reg>; + vdd_pll-supply = <&ldo8_reg>; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm 0 1000000 0>; + brightness-levels = <0 100 500 1000 1500 2000 2500 2800>; + default-brightness-level = <7>; + pinctrl-0 = <&pwm0_out>; + pinctrl-names = "default"; + }; + + fimd@14400000 { + status = "okay"; + samsung,invert-vclk; + }; + + dp-controller@145B0000 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&dp_hpd>; + samsung,color-space = <0>; + samsung,dynamic-range = <0>; + samsung,ycbcr-coeff = <0>; + samsung,color-depth = <1>; + samsung,link-rate = <0x0a>; + samsung,lane-count = <2>; + samsung,hpd-gpio = <&gpx0 7 0>; + + display-timings { + native-mode = <&timing1>; + + timing1: timing@1 { + clock-frequency = <70589280>; + hactive = <1366>; + vactive = <768>; + hfront-porch = <40>; + hback-porch = <40>; + hsync-len = <32>; + vback-porch = <10>; + vfront-porch = <12>; + vsync-len = <6>; + }; + }; + }; }; diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index 37423314a028..834fb5a5306f 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -72,6 +72,24 @@ }; }; + sysram@02020000 { + compatible = "mmio-sram"; + reg = <0x02020000 0x30000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x02020000 0x30000>; + + smp-sysram@0 { + compatible = "samsung,exynos4210-sysram"; + reg = <0x0 0x1000>; + }; + + smp-sysram@2f000 { + compatible = "samsung,exynos4210-sysram-ns"; + reg = <0x2f000 0x1000>; + }; + }; + pd_gsc: gsc-power-domain@10044000 { compatible = "samsung,exynos4210-pd"; reg = <0x10044000 0x20>; @@ -175,6 +193,11 @@ reg = <0x10040000 0x5000>; }; + sysreg_system_controller: syscon@10050000 { + compatible = "samsung,exynos5-sysreg", "syscon"; + reg = <0x10050000 0x5000>; + }; + watchdog@101D0000 { compatible = "samsung,exynos5250-wdt"; reg = <0x101D0000 0x100>; @@ -250,7 +273,7 @@ sata_phy: sata-phy@12170000 { compatible = "samsung,exynos5250-sata-phy"; reg = <0x12170000 0x1ff>; - clocks = <&clock 287>; + clocks = <&clock CLK_SATA_PHYCTRL>; clock-names = "sata_phyctrl"; #phy-cells = <0>; samsung,syscon-phandle = <&pmu_system_controller>; @@ -533,22 +556,18 @@ compatible = "synopsys,dwc3"; reg = <0x12000000 0x10000>; interrupts = <0 72 0>; - usb-phy = <&usb2_phy &usb3_phy>; + phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>; + phy-names = "usb2-phy", "usb3-phy"; }; }; - usb3_phy: usbphy@12100000 { - compatible = "samsung,exynos5250-usb3phy"; + usbdrd_phy: phy@12100000 { + compatible = "samsung,exynos5250-usbdrd-phy"; reg = <0x12100000 0x100>; - clocks = <&clock CLK_FIN_PLL>, <&clock CLK_USB3>; - clock-names = "ext_xtal", "usbdrd30"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - usbphy-sys { - reg = <0x10040704 0x8>; - }; + clocks = <&clock CLK_USB3>, <&clock CLK_FIN_PLL>; + clock-names = "phy", "ref"; + samsung,pmu-syscon = <&pmu_system_controller>; + #phy-cells = <1>; }; usb@12110000 { @@ -558,6 +577,12 @@ clocks = <&clock CLK_USB2>; clock-names = "usbhost"; + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + phys = <&usb2_phy_gen 1>; + }; }; usb@12120000 { @@ -567,6 +592,12 @@ clocks = <&clock CLK_USB2>; clock-names = "usbhost"; + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + phys = <&usb2_phy_gen 1>; + }; }; usb2_phy: usbphy@12130000 { @@ -584,6 +615,16 @@ }; }; + usb2_phy_gen: phy@12130000 { + compatible = "samsung,exynos5250-usb2-phy"; + reg = <0x12130000 0x100>; + clocks = <&clock CLK_USB2>, <&clock CLK_FIN_PLL>; + clock-names = "phy", "ref"; + #phy-cells = <1>; + samsung,sysreg-phandle = <&sysreg_system_controller>; + samsung,pmureg-phandle = <&pmu_system_controller>; + }; + pwm: pwm@12dd0000 { compatible = "samsung,exynos4210-pwm"; reg = <0x12dd0000 0x100>; @@ -690,6 +731,7 @@ <&clock CLK_MOUT_HDMI>; clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", "sclk_hdmiphy", "mout_hdmi"; + samsung,syscon-phandle = <&pmu_system_controller>; }; mixer { @@ -733,7 +775,7 @@ compatible = "samsung,exynos4210-secss"; reg = <0x10830000 0x10000>; interrupts = <0 112 0>; - clocks = <&clock 348>; + clocks = <&clock CLK_SSS>; clock-names = "secss"; }; }; diff --git a/arch/arm/boot/dts/exynos5260-pinctrl.dtsi b/arch/arm/boot/dts/exynos5260-pinctrl.dtsi new file mode 100644 index 000000000000..f6ee55ea0708 --- /dev/null +++ b/arch/arm/boot/dts/exynos5260-pinctrl.dtsi @@ -0,0 +1,574 @@ +/* + * Samsung's Exynos5260 SoC pin-mux and pin-config device tree source + * + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Samsung's Exynos5260 SoC pin-mux and pin-config options are listed as device + * tree nodes are listed in this file. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#define PIN_PULL_NONE 0 +#define PIN_PULL_DOWN 1 +#define PIN_PULL_UP 3 + +&pinctrl_0 { + gpa0: gpa0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpa1: gpa1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpa2: gpa2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb0: gpb0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb1: gpb1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb2: gpb2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb3: gpb3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb4: gpb4 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb5: gpb5 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd0: gpd0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd1: gpd1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd2: gpd2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpe0: gpe0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpe1: gpe1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf0: gpf0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf1: gpf1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpk0: gpk0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpx0: gpx0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpx1: gpx1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpx2: gpx2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpx3: gpx3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + uart0_data: uart0-data { + samsung,pins = "gpa0-0", "gpa0-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-drv = <0>; + }; + + uart0_fctl: uart0-fctl { + samsung,pins = "gpa0-2", "gpa0-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-drv = <0>; + }; + + uart1_data: uart1-data { + samsung,pins = "gpa1-0", "gpa1-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-drv = <0>; + }; + + uart1_fctl: uart1-fctl { + samsung,pins = "gpa1-2", "gpa1-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-drv = <0>; + }; + + uart2_data: uart2-data { + samsung,pins = "gpa1-4", "gpa1-5"; + samsung,pin-function = <2>; + samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-drv = <0>; + }; + + spi0_bus: spi0-bus { + samsung,pins = "gpa2-0", "gpa2-2", "gpa2-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <PIN_PULL_UP>; + samsung,pin-drv = <0>; + }; + + spi1_bus: spi1-bus { + samsung,pins = "gpa2-4", "gpa2-6", "gpa2-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <PIN_PULL_UP>; + samsung,pin-drv = <0>; + }; + + usb3_vbus0_en: usb3-vbus0-en { + samsung,pins = "gpa2-4"; + samsung,pin-function = <1>; + samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-drv = <0>; + }; + + i2s1_bus: i2s1-bus { + samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", + "gpb0-4"; + samsung,pin-function = <2>; + samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-drv = <0>; + }; + + pcm1_bus: pcm1-bus { + samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", + "gpb0-4"; + samsung,pin-function = <3>; + samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-drv = <0>; + }; + + spdif1_bus: spdif1-bus { + samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2"; + samsung,pin-function = <4>; + samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-drv = <0>; + }; + + spi2_bus: spi2-bus { + samsung,pins = "gpb1-0", "gpb1-2", "gpb1-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <PIN_PULL_UP>; + samsung,pin-drv = <0>; + }; + + i2c0_hs_bus: i2c0-hs-bus { + samsung,pins = "gpb3-0", "gpb3-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <PIN_PULL_UP>; + samsung,pin-drv = <0>; + }; + + i2c1_hs_bus: i2c1-hs-bus { + samsung,pins = "gpb3-2", "gpb3-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <PIN_PULL_UP>; + samsung,pin-drv = <0>; + }; + + i2c2_hs_bus: i2c2-hs-bus { + samsung,pins = "gpb3-4", "gpb3-5"; + samsung,pin-function = <2>; + samsung,pin-pud = <PIN_PULL_UP>; + samsung,pin-drv = <0>; + }; + + i2c3_hs_bus: i2c3-hs-bus { + samsung,pins = "gpb3-6", "gpb3-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <PIN_PULL_UP>; + samsung,pin-drv = <0>; + }; + + i2c4_bus: i2c4-bus { + samsung,pins = "gpb4-0", "gpb4-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <PIN_PULL_UP>; + samsung,pin-drv = <0>; + }; + + i2c5_bus: i2c5-bus { + samsung,pins = "gpb4-2", "gpb4-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <PIN_PULL_UP>; + samsung,pin-drv = <0>; + }; + + i2c6_bus: i2c6-bus { + samsung,pins = "gpb4-4", "gpb4-5"; + samsung,pin-function = <2>; + samsung,pin-pud = <PIN_PULL_UP>; + samsung,pin-drv = <0>; + }; + + i2c7_bus: i2c7-bus { + samsung,pins = "gpb4-6", "gpb4-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <PIN_PULL_UP>; + samsung,pin-drv = <0>; + }; + + i2c8_bus: i2c8-bus { + samsung,pins = "gpb5-0", "gpb5-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <PIN_PULL_UP>; + samsung,pin-drv = <0>; + }; + + i2c9_bus: i2c9-bus { + samsung,pins = "gpb5-2", "gpb5-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <PIN_PULL_UP>; + samsung,pin-drv = <0>; + }; + + i2c10_bus: i2c10-bus { + samsung,pins = "gpb5-4", "gpb5-5"; + samsung,pin-function = <2>; + samsung,pin-pud = <PIN_PULL_UP>; + samsung,pin-drv = <0>; + }; + + i2c11_bus: i2c11-bus { + samsung,pins = "gpb5-6", "gpb5-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <PIN_PULL_UP>; + samsung,pin-drv = <0>; + }; + + cam_gpio_a: cam-gpio-a { + samsung,pins = "gpe0-0", "gpe0-1", "gpe0-2", "gpe0-3", + "gpe0-4", "gpe0-5", "gpe0-6", "gpe0-7", + "gpe1-0", "gpe1-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-drv = <0>; + }; + + cam_gpio_b: cam-gpio-b { + samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3", + "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-drv = <0>; + }; + + cam_i2c1_bus: cam-i2c1-bus { + samsung,pins = "gpf0-2", "gpf0-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <PIN_PULL_UP>; + samsung,pin-drv = <0>; + }; + + cam_i2c0_bus: cam-i2c0-bus { + samsung,pins = "gpf0-0", "gpf0-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <PIN_PULL_UP>; + samsung,pin-drv = <0>; + }; + + cam_spi0_bus: cam-spi0-bus { + samsung,pins = "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-drv = <0>; + }; + + cam_spi1_bus: cam-spi1-bus { + samsung,pins = "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-drv = <0>; + }; +}; + +&pinctrl_1 { + gpc0: gpc0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc1: gpc1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc2: gpc2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc3: gpc3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc4: gpc4 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + sd0_clk: sd0-clk { + samsung,pins = "gpc0-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-drv = <3>; + }; + + sd0_cmd: sd0-cmd { + samsung,pins = "gpc0-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-drv = <3>; + }; + + sd0_bus1: sd0-bus-width1 { + samsung,pins = "gpc0-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <PIN_PULL_UP>; + samsung,pin-drv = <3>; + }; + + sd0_bus4: sd0-bus-width4 { + samsung,pins = "gpc0-3", "gpc0-4", "gpc0-5"; + samsung,pin-function = <2>; + samsung,pin-pud = <PIN_PULL_UP>; + samsung,pin-drv = <3>; + }; + + sd0_bus8: sd0-bus-width8 { + samsung,pins = "gpc3-0", "gpc3-1", "gpc3-2", "gpc3-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <PIN_PULL_UP>; + samsung,pin-drv = <3>; + }; + + sd0_rdqs: sd0-rdqs { + samsung,pins = "gpc0-6"; + samsung,pin-function = <2>; + samsung,pin-pud = <PIN_PULL_UP>; + samsung,pin-drv = <3>; + }; + + sd1_clk: sd1-clk { + samsung,pins = "gpc1-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-drv = <3>; + }; + + sd1_cmd: sd1-cmd { + samsung,pins = "gpc1-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-drv = <3>; + }; + + sd1_bus1: sd1-bus-width1 { + samsung,pins = "gpc1-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <PIN_PULL_UP>; + samsung,pin-drv = <3>; + }; + + sd1_bus4: sd1-bus-width4 { + samsung,pins = "gpc1-3", "gpc1-4", "gpc1-5"; + samsung,pin-function = <2>; + samsung,pin-pud = <PIN_PULL_UP>; + samsung,pin-drv = <3>; + }; + + sd1_bus8: sd1-bus-width8 { + samsung,pins = "gpc4-0", "gpc4-1", "gpc4-2", "gpc4-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <PIN_PULL_UP>; + samsung,pin-drv = <3>; + }; + + sd2_clk: sd2-clk { + samsung,pins = "gpc2-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-drv = <3>; + }; + + sd2_cmd: sd2-cmd { + samsung,pins = "gpc2-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <PIN_PULL_NONE>; + samsung,pin-drv = <3>; + }; + + sd2_cd: sd2-cd { + samsung,pins = "gpc2-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <PIN_PULL_UP>; + samsung,pin-drv = <3>; + }; + + sd2_bus1: sd2-bus-width1 { + samsung,pins = "gpc2-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <PIN_PULL_UP>; + samsung,pin-drv = <3>; + }; + + sd2_bus4: sd2-bus-width4 { + samsung,pins = "gpc2-4", "gpc2-5", "gpc2-6"; + samsung,pin-function = <2>; + samsung,pin-pud = <PIN_PULL_UP>; + samsung,pin-drv = <3>; + }; +}; + +&pinctrl_2 { + gpz0: gpz0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpz1: gpz1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; +}; diff --git a/arch/arm/boot/dts/exynos5260-xyref5260.dts b/arch/arm/boot/dts/exynos5260-xyref5260.dts new file mode 100644 index 000000000000..8c84ab27c19b --- /dev/null +++ b/arch/arm/boot/dts/exynos5260-xyref5260.dts @@ -0,0 +1,103 @@ +/* + * SAMSUNG XYREF5260 board device tree source + * + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/dts-v1/; +#include "exynos5260.dtsi" + +/ { + model = "SAMSUNG XYREF5260 board based on EXYNOS5260"; + compatible = "samsung,xyref5260", "samsung,exynos5260", "samsung,exynos5"; + + memory { + reg = <0x20000000 0x80000000>; + }; + + chosen { + bootargs = "console=ttySAC2,115200"; + }; + + fin_pll: xxti { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "fin_pll"; + #clock-cells = <0>; + }; + + xrtcxti: xrtcxti { + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "xrtcxti"; + #clock-cells = <0>; + }; +}; + +&pinctrl_0 { + hdmi_hpd_irq: hdmi-hpd-irq { + samsung,pins = "gpx3-7"; + samsung,pin-function = <0>; + samsung,pin-pud = <1>; + samsung,pin-drv = <0>; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&mmc_0 { + status = "okay"; + num-slots = <1>; + broken-cd; + bypass-smu; + supports-highspeed; + supports-hs200-mode; /* 200 Mhz */ + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <0 4>; + samsung,dw-mshc-ddr-timing = <0 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd0_rdqs &sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>; + + slot@0 { + reg = <0>; + bus-width = <8>; + }; +}; + +&mmc_2 { + status = "okay"; + num-slots = <1>; + supports-highspeed; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <2 3>; + samsung,dw-mshc-ddr-timing = <1 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>; + + slot@0 { + reg = <0>; + bus-width = <4>; + disable-wp; + }; +}; diff --git a/arch/arm/boot/dts/exynos5260.dtsi b/arch/arm/boot/dts/exynos5260.dtsi new file mode 100644 index 000000000000..5398a60207ca --- /dev/null +++ b/arch/arm/boot/dts/exynos5260.dtsi @@ -0,0 +1,304 @@ +/* + * SAMSUNG EXYNOS5260 SoC device tree source + * + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include "skeleton.dtsi" + +#include <dt-bindings/clock/exynos5260-clk.h> + +/ { + compatible = "samsung,exynos5260", "samsung,exynos5"; + interrupt-parent = <&gic>; + + aliases { + pinctrl0 = &pinctrl_0; + pinctrl1 = &pinctrl_1; + pinctrl2 = &pinctrl_2; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x0>; + cci-control-port = <&cci_control1>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x1>; + cci-control-port = <&cci_control1>; + }; + + cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x100>; + cci-control-port = <&cci_control0>; + }; + + cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x101>; + cci-control-port = <&cci_control0>; + }; + + cpu@102 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x102>; + cci-control-port = <&cci_control0>; + }; + + cpu@103 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x103>; + cci-control-port = <&cci_control0>; + }; + }; + + soc: soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clock_top: clock-controller@10010000 { + compatible = "samsung,exynos5260-clock-top"; + reg = <0x10010000 0x10000>; + #clock-cells = <1>; + }; + + clock_peri: clock-controller@10200000 { + compatible = "samsung,exynos5260-clock-peri"; + reg = <0x10200000 0x10000>; + #clock-cells = <1>; + }; + + clock_egl: clock-controller@10600000 { + compatible = "samsung,exynos5260-clock-egl"; + reg = <0x10600000 0x10000>; + #clock-cells = <1>; + }; + + clock_kfc: clock-controller@10700000 { + compatible = "samsung,exynos5260-clock-kfc"; + reg = <0x10700000 0x10000>; + #clock-cells = <1>; + }; + + clock_g2d: clock-controller@10A00000 { + compatible = "samsung,exynos5260-clock-g2d"; + reg = <0x10A00000 0x10000>; + #clock-cells = <1>; + }; + + clock_mif: clock-controller@10CE0000 { + compatible = "samsung,exynos5260-clock-mif"; + reg = <0x10CE0000 0x10000>; + #clock-cells = <1>; + }; + + clock_mfc: clock-controller@11090000 { + compatible = "samsung,exynos5260-clock-mfc"; + reg = <0x11090000 0x10000>; + #clock-cells = <1>; + }; + + clock_g3d: clock-controller@11830000 { + compatible = "samsung,exynos5260-clock-g3d"; + reg = <0x11830000 0x10000>; + #clock-cells = <1>; + }; + + clock_fsys: clock-controller@122E0000 { + compatible = "samsung,exynos5260-clock-fsys"; + reg = <0x122E0000 0x10000>; + #clock-cells = <1>; + }; + + clock_aud: clock-controller@128C0000 { + compatible = "samsung,exynos5260-clock-aud"; + reg = <0x128C0000 0x10000>; + #clock-cells = <1>; + }; + + clock_isp: clock-controller@133C0000 { + compatible = "samsung,exynos5260-clock-isp"; + reg = <0x133C0000 0x10000>; + #clock-cells = <1>; + }; + + clock_gscl: clock-controller@13F00000 { + compatible = "samsung,exynos5260-clock-gscl"; + reg = <0x13F00000 0x10000>; + #clock-cells = <1>; + }; + + clock_disp: clock-controller@14550000 { + compatible = "samsung,exynos5260-clock-disp"; + reg = <0x14550000 0x10000>; + #clock-cells = <1>; + }; + + gic: interrupt-controller@10481000 { + compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + #size-cells = <0>; + interrupt-controller; + reg = <0x10481000 0x1000>, + <0x10482000 0x1000>, + <0x10484000 0x2000>, + <0x10486000 0x2000>; + interrupts = <1 9 0xf04>; + }; + + chipid: chipid@10000000 { + compatible = "samsung,exynos4210-chipid"; + reg = <0x10000000 0x100>; + }; + + mct: mct@100B0000 { + compatible = "samsung,exynos4210-mct"; + reg = <0x100B0000 0x1000>; + clocks = <&fin_pll>, <&clock_peri PERI_CLK_MCT>; + clock-names = "fin_pll", "mct"; + interrupts = <0 104 0>, <0 105 0>, <0 106 0>, + <0 107 0>, <0 122 0>, <0 123 0>, + <0 124 0>, <0 125 0>, <0 126 0>, + <0 127 0>, <0 128 0>, <0 129 0>; + }; + + cci: cci@10F00000 { + compatible = "arm,cci-400"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x10F00000 0x1000>; + ranges = <0x0 0x10F00000 0x6000>; + + cci_control0: slave-if@4000 { + compatible = "arm,cci-400-ctrl-if"; + interface-type = "ace"; + reg = <0x4000 0x1000>; + }; + + cci_control1: slave-if@5000 { + compatible = "arm,cci-400-ctrl-if"; + interface-type = "ace"; + reg = <0x5000 0x1000>; + }; + }; + + pinctrl_0: pinctrl@11600000 { + compatible = "samsung,exynos5260-pinctrl"; + reg = <0x11600000 0x1000>; + interrupts = <0 79 0>; + + wakeup-interrupt-controller { + compatible = "samsung,exynos4210-wakeup-eint"; + interrupt-parent = <&gic>; + interrupts = <0 32 0>; + }; + }; + + pinctrl_1: pinctrl@12290000 { + compatible = "samsung,exynos5260-pinctrl"; + reg = <0x12290000 0x1000>; + interrupts = <0 157 0>; + }; + + pinctrl_2: pinctrl@128B0000 { + compatible = "samsung,exynos5260-pinctrl"; + reg = <0x128B0000 0x1000>; + interrupts = <0 243 0>; + }; + + uart0: serial@12C00000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x12C00000 0x100>; + interrupts = <0 146 0>; + clocks = <&clock_peri PERI_CLK_UART0>, <&clock_peri PERI_SCLK_UART0>; + clock-names = "uart", "clk_uart_baud0"; + status = "disabled"; + }; + + uart1: serial@12C10000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x12C10000 0x100>; + interrupts = <0 147 0>; + clocks = <&clock_peri PERI_CLK_UART1>, <&clock_peri PERI_SCLK_UART1>; + clock-names = "uart", "clk_uart_baud0"; + status = "disabled"; + }; + + uart2: serial@12C20000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x12C20000 0x100>; + interrupts = <0 148 0>; + clocks = <&clock_peri PERI_CLK_UART2>, <&clock_peri PERI_SCLK_UART2>; + clock-names = "uart", "clk_uart_baud0"; + status = "disabled"; + }; + + uart3: serial@12860000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x12860000 0x100>; + interrupts = <0 145 0>; + clocks = <&clock_aud AUD_CLK_AUD_UART>, <&clock_aud AUD_SCLK_AUD_UART>; + clock-names = "uart", "clk_uart_baud0"; + status = "disabled"; + }; + + mmc_0: mmc@12140000 { + compatible = "samsung,exynos5250-dw-mshc"; + reg = <0x12140000 0x2000>; + interrupts = <0 156 0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clock_fsys FSYS_CLK_MMC0>, <&clock_top TOP_SCLK_MMC0>; + clock-names = "biu", "ciu"; + fifo-depth = <64>; + status = "disabled"; + }; + + mmc_1: mmc@12150000 { + compatible = "samsung,exynos5250-dw-mshc"; + reg = <0x12150000 0x2000>; + interrupts = <0 158 0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clock_fsys FSYS_CLK_MMC1>, <&clock_top TOP_SCLK_MMC1>; + clock-names = "biu", "ciu"; + fifo-depth = <64>; + status = "disabled"; + }; + + mmc_2: mmc@12160000 { + compatible = "samsung,exynos5250-dw-mshc"; + reg = <0x12160000 0x2000>; + interrupts = <0 159 0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clock_fsys FSYS_CLK_MMC2>, <&clock_top TOP_SCLK_MMC2>; + clock-names = "biu", "ciu"; + fifo-depth = <64>; + status = "disabled"; + }; + }; +}; + +#include "exynos5260-pinctrl.dtsi" diff --git a/arch/arm/boot/dts/exynos5410-smdk5410.dts b/arch/arm/boot/dts/exynos5410-smdk5410.dts new file mode 100644 index 000000000000..7275bbd6fc4b --- /dev/null +++ b/arch/arm/boot/dts/exynos5410-smdk5410.dts @@ -0,0 +1,82 @@ +/* + * SAMSUNG SMDK5410 board device tree source + * + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/dts-v1/; +#include "exynos5410.dtsi" +/ { + model = "Samsung SMDK5410 board based on EXYNOS5410"; + compatible = "samsung,smdk5410", "samsung,exynos5410", "samsung,exynos5"; + + memory { + reg = <0x40000000 0x80000000>; + }; + + chosen { + bootargs = "console=ttySAC2,115200"; + }; + + fin_pll: xxti { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "fin_pll"; + #clock-cells = <0>; + }; + + firmware@02037000 { + compatible = "samsung,secure-firmware"; + reg = <0x02037000 0x1000>; + }; + +}; + +&mmc_0 { + status = "okay"; + num-slots = <1>; + supports-highspeed; + broken-cd; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <2 3>; + samsung,dw-mshc-ddr-timing = <1 2>; + + slot@0 { + reg = <0>; + bus-width = <8>; + }; +}; + +&mmc_2 { + status = "okay"; + num-slots = <1>; + supports-highspeed; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <2 3>; + samsung,dw-mshc-ddr-timing = <1 2>; + + slot@0 { + reg = <0>; + bus-width = <4>; + disable-wp; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/exynos5410.dtsi b/arch/arm/boot/dts/exynos5410.dtsi new file mode 100644 index 000000000000..3839c26f467f --- /dev/null +++ b/arch/arm/boot/dts/exynos5410.dtsi @@ -0,0 +1,206 @@ +/* + * SAMSUNG EXYNOS5410 SoC device tree source + * + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * SAMSUNG EXYNOS5410 SoC device nodes are listed in this file. + * EXYNOS5410 based board files can include this file and provide + * values for board specfic bindings. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "skeleton.dtsi" +#include <dt-bindings/clock/exynos5410.h> + +/ { + compatible = "samsung,exynos5410", "samsung,exynos5"; + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x0>; + }; + + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x1>; + }; + + CPU2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x2>; + }; + + CPU3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x3>; + }; + }; + + soc: soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + combiner: interrupt-controller@10440000 { + compatible = "samsung,exynos4210-combiner"; + #interrupt-cells = <2>; + interrupt-controller; + samsung,combiner-nr = <32>; + reg = <0x10440000 0x1000>; + interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>, + <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>, + <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>, + <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>, + <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>, + <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>, + <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>, + <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>; + }; + + gic: interrupt-controller@10481000 { + compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x10481000 0x1000>, + <0x10482000 0x1000>, + <0x10484000 0x2000>, + <0x10486000 0x2000>; + interrupts = <1 9 0xf04>; + }; + + chipid@10000000 { + compatible = "samsung,exynos4210-chipid"; + reg = <0x10000000 0x100>; + }; + + mct: mct@101C0000 { + compatible = "samsung,exynos4210-mct"; + reg = <0x101C0000 0xB00>; + interrupt-parent = <&interrupt_map>; + interrupts = <0>, <1>, <2>, <3>, + <4>, <5>, <6>, <7>, + <8>, <9>, <10>, <11>; + clocks = <&fin_pll>, <&clock CLK_MCT>; + clock-names = "fin_pll", "mct"; + + interrupt_map: interrupt-map { + #interrupt-cells = <1>; + #address-cells = <0>; + #size-cells = <0>; + interrupt-map = <0 &combiner 23 3>, + <1 &combiner 23 4>, + <2 &combiner 25 2>, + <3 &combiner 25 3>, + <4 &gic 0 120 0>, + <5 &gic 0 121 0>, + <6 &gic 0 122 0>, + <7 &gic 0 123 0>, + <8 &gic 0 128 0>, + <9 &gic 0 129 0>, + <10 &gic 0 130 0>, + <11 &gic 0 131 0>; + }; + }; + + sysram@02020000 { + compatible = "mmio-sram"; + reg = <0x02020000 0x54000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x02020000 0x54000>; + + smp-sysram@0 { + compatible = "samsung,exynos4210-sysram"; + reg = <0x0 0x1000>; + }; + + smp-sysram@53000 { + compatible = "samsung,exynos4210-sysram-ns"; + reg = <0x53000 0x1000>; + }; + }; + + clock: clock-controller@10010000 { + compatible = "samsung,exynos5410-clock"; + reg = <0x10010000 0x30000>; + #clock-cells = <1>; + }; + + mmc_0: mmc@12200000 { + compatible = "samsung,exynos5250-dw-mshc"; + reg = <0x12200000 0x1000>; + interrupts = <0 75 0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>; + clock-names = "biu", "ciu"; + fifo-depth = <0x80>; + status = "disabled"; + }; + + mmc_1: mmc@12210000 { + compatible = "samsung,exynos5250-dw-mshc"; + reg = <0x12210000 0x1000>; + interrupts = <0 76 0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>; + clock-names = "biu", "ciu"; + fifo-depth = <0x80>; + status = "disabled"; + }; + + mmc_2: mmc@12220000 { + compatible = "samsung,exynos5250-dw-mshc"; + reg = <0x12220000 0x1000>; + interrupts = <0 77 0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>; + clock-names = "biu", "ciu"; + fifo-depth = <0x80>; + status = "disabled"; + }; + + uart0: serial@12C00000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x12C00000 0x100>; + interrupts = <0 51 0>; + clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; + clock-names = "uart", "clk_uart_baud0"; + status = "disabled"; + }; + + uart1: serial@12C10000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x12C10000 0x100>; + interrupts = <0 52 0>; + clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>; + clock-names = "uart", "clk_uart_baud0"; + status = "disabled"; + }; + + uart2: serial@12C20000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x12C20000 0x100>; + interrupts = <0 53 0>; + clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; + clock-names = "uart", "clk_uart_baud0"; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts b/arch/arm/boot/dts/exynos5420-arndale-octa.dts index 896a2a6619e0..434fd9d3e09d 100644 --- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts +++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts @@ -26,6 +26,11 @@ bootargs = "console=ttySAC3,115200"; }; + firmware@02073000 { + compatible = "samsung,secure-firmware"; + reg = <0x02073000 0x1000>; + }; + fixed-rate-clocks { oscclk { compatible = "samsung,exynos5420-oscclk"; @@ -37,6 +42,11 @@ status = "okay"; }; + codec@11000000 { + samsung,mfc-r = <0x43000000 0x800000>; + samsung,mfc-l = <0x51000000 0x800000>; + }; + mmc@12200000 { status = "okay"; broken-cd; diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts new file mode 100644 index 000000000000..1c5b8f9f4a36 --- /dev/null +++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts @@ -0,0 +1,287 @@ +/* + * Google Peach Pit Rev 6+ board device tree source + * + * Copyright (c) 2014 Google, Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; +#include <dt-bindings/input/input.h> +#include <dt-bindings/gpio/gpio.h> +#include "exynos5420.dtsi" + +/ { + model = "Google Peach Pit Rev 6+"; + + compatible = "google,pit-rev16", + "google,pit-rev15", "google,pit-rev14", + "google,pit-rev13", "google,pit-rev12", + "google,pit-rev11", "google,pit-rev10", + "google,pit-rev9", "google,pit-rev8", + "google,pit-rev7", "google,pit-rev6", + "google,pit", "google,peach","samsung,exynos5420", + "samsung,exynos5"; + + memory { + reg = <0x20000000 0x80000000>; + }; + + fixed-rate-clocks { + oscclk { + compatible = "samsung,exynos5420-oscclk"; + clock-frequency = <24000000>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&power_key_irq>; + + power { + label = "Power"; + gpios = <&gpx1 2 GPIO_ACTIVE_LOW>; + linux,code = <KEY_POWER>; + gpio-key,wakeup; + }; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm 0 1000000 0>; + brightness-levels = <0 100 500 1000 1500 2000 2500 2800>; + default-brightness-level = <7>; + pinctrl-0 = <&pwm0_out>; + pinctrl-names = "default"; + }; + + sound { + compatible = "google,snow-audio-max98090"; + + samsung,i2s-controller = <&i2s0>; + samsung,audio-codec = <&max98090>; + }; + + usb300_vbus_reg: regulator-usb300 { + compatible = "regulator-fixed"; + regulator-name = "P5.0V_USB3CON0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gph0 0 0>; + pinctrl-names = "default"; + pinctrl-0 = <&usb300_vbus_en>; + enable-active-high; + }; + + usb301_vbus_reg: regulator-usb301 { + compatible = "regulator-fixed"; + regulator-name = "P5.0V_USB3CON1"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gph0 1 0>; + pinctrl-names = "default"; + pinctrl-0 = <&usb301_vbus_en>; + enable-active-high; + }; +}; + +&pinctrl_0 { + max98090_irq: max98090-irq { + samsung,pins = "gpx0-2"; + samsung,pin-function = <0>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + tpm_irq: tpm-irq { + samsung,pins = "gpx1-0"; + samsung,pin-function = <0>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + power_key_irq: power-key-irq { + samsung,pins = "gpx1-2"; + samsung,pin-function = <0>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + hdmi_hpd_irq: hdmi-hpd-irq { + samsung,pins = "gpx3-7"; + samsung,pin-function = <0>; + samsung,pin-pud = <1>; + samsung,pin-drv = <0>; + }; + + dp_hpd_gpio: dp_hpd_gpio { + samsung,pins = "gpx2-6"; + samsung,pin-function = <0>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; +}; + +&pinctrl_3 { + usb300_vbus_en: usb300-vbus-en { + samsung,pins = "gph0-0"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + usb301_vbus_en: usb301-vbus-en { + samsung,pins = "gph0-1"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; +}; + +&rtc { + status = "okay"; +}; + +&uart_3 { + status = "okay"; +}; + +&mmc_0 { + status = "okay"; + num-slots = <1>; + broken-cd; + caps2-mmc-hs200-1_8v; + supports-highspeed; + non-removable; + card-detect-delay = <200>; + clock-frequency = <400000000>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <0 4>; + samsung,dw-mshc-ddr-timing = <0 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; + + slot@0 { + reg = <0>; + bus-width = <8>; + }; +}; + +&mmc_2 { + status = "okay"; + num-slots = <1>; + supports-highspeed; + card-detect-delay = <200>; + clock-frequency = <400000000>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <2 3>; + samsung,dw-mshc-ddr-timing = <1 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; + + slot@0 { + reg = <0>; + bus-width = <4>; + }; +}; + +&hsi2c_7 { + status = "okay"; + + max98090: codec@10 { + compatible = "maxim,max98090"; + reg = <0x10>; + interrupts = <2 0>; + interrupt-parent = <&gpx0>; + pinctrl-names = "default"; + pinctrl-0 = <&max98090_irq>; + }; +}; + +&hsi2c_9 { + status = "okay"; + clock-frequency = <400000>; + + tpm@20 { + compatible = "infineon,slb9645tt"; + reg = <0x20>; + + /* Unused irq; but still need to configure the pins */ + pinctrl-names = "default"; + pinctrl-0 = <&tpm_irq>; + }; +}; + +&i2c_2 { + status = "okay"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <66000>; + samsung,i2c-slave-addr = <0x50>; +}; + +&hdmi { + status = "okay"; + hpd-gpio = <&gpx3 7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_hpd_irq>; + ddc = <&i2c_2>; +}; + +&usbdrd_phy0 { + vbus-supply = <&usb300_vbus_reg>; +}; + +&usbdrd_phy1 { + vbus-supply = <&usb301_vbus_reg>; +}; + +/* + * Use longest HW watchdog in SoC (32 seconds) since the hardware + * watchdog provides no debugging information (compared to soft/hard + * lockup detectors) and so should be last resort. + */ +&watchdog { + timeout-sec = <32>; +}; + +&i2s0 { + status = "okay"; +}; + +&fimd { + status = "okay"; + samsung,invert-vclk; +}; + +&dp { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&dp_hpd_gpio>; + samsung,color-space = <0>; + samsung,dynamic-range = <0>; + samsung,ycbcr-coeff = <0>; + samsung,color-depth = <1>; + samsung,link-rate = <0x06>; + samsung,lane-count = <2>; + samsung,hpd-gpio = <&gpx2 6 0>; + + display-timings { + native-mode = <&timing1>; + + timing1: timing@1 { + clock-frequency = <70589280>; + hactive = <1366>; + vactive = <768>; + hfront-porch = <40>; + hback-porch = <40>; + hsync-len = <32>; + vback-porch = <10>; + vfront-porch = <12>; + vsync-len = <6>; + }; + }; +}; diff --git a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi index e62c8eb57438..ba686e40eac7 100644 --- a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi @@ -624,6 +624,34 @@ samsung,pin-drv = <0>; }; + pwm0_out: pwm0-out { + samsung,pins = "gpb2-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + pwm1_out: pwm1-out { + samsung,pins = "gpb2-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + pwm2_out: pwm2-out { + samsung,pins = "gpb2-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + pwm3_out: pwm3-out { + samsung,pins = "gpb2-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + i2c7_hs_bus: i2c7-hs-bus { samsung,pins = "gpb2-2", "gpb2-3"; samsung,pin-function = <3>; diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts index 69104850eb5e..6052aa9c5659 100644 --- a/arch/arm/boot/dts/exynos5420-smdk5420.dts +++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts @@ -68,6 +68,11 @@ status = "okay"; }; + codec@11000000 { + samsung,mfc-r = <0x43000000 0x800000>; + samsung,mfc-l = <0x51000000 0x800000>; + }; + mmc@12200000 { status = "okay"; broken-cd; @@ -140,6 +145,22 @@ }; }; + pinctrl@14000000 { + usb300_vbus_en: usb300-vbus-en { + samsung,pins = "gpg0-5"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + usb301_vbus_en: usb301-vbus-en { + samsung,pins = "gpg1-4"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + }; + hdmi@14530000 { status = "okay"; hpd-gpio = <&gpx3 7 0>; @@ -147,6 +168,36 @@ pinctrl-0 = <&hdmi_hpd_irq>; }; + usb300_vbus_reg: regulator-usb300 { + compatible = "regulator-fixed"; + regulator-name = "VBUS0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpg0 5 0>; + pinctrl-names = "default"; + pinctrl-0 = <&usb300_vbus_en>; + enable-active-high; + }; + + usb301_vbus_reg: regulator-usb301 { + compatible = "regulator-fixed"; + regulator-name = "VBUS1"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpg1 4 0>; + pinctrl-names = "default"; + pinctrl-0 = <&usb301_vbus_en>; + enable-active-high; + }; + + phy@12100000 { + vbus-supply = <&usb300_vbus_reg>; + }; + + phy@12500000 { + vbus-supply = <&usb301_vbus_reg>; + }; + i2c_2: i2c@12C80000 { samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <66000>; diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index b69fbcb7dcb8..e38532271ef9 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -47,6 +47,8 @@ spi0 = &spi_0; spi1 = &spi_1; spi2 = &spi_2; + usbdrdphy0 = &usbdrd_phy0; + usbdrdphy1 = &usbdrd_phy1; }; cpus { @@ -58,6 +60,7 @@ compatible = "arm,cortex-a15"; reg = <0x0>; clock-frequency = <1800000000>; + cci-control-port = <&cci_control1>; }; cpu1: cpu@1 { @@ -65,6 +68,7 @@ compatible = "arm,cortex-a15"; reg = <0x1>; clock-frequency = <1800000000>; + cci-control-port = <&cci_control1>; }; cpu2: cpu@2 { @@ -72,6 +76,7 @@ compatible = "arm,cortex-a15"; reg = <0x2>; clock-frequency = <1800000000>; + cci-control-port = <&cci_control1>; }; cpu3: cpu@3 { @@ -79,6 +84,7 @@ compatible = "arm,cortex-a15"; reg = <0x3>; clock-frequency = <1800000000>; + cci-control-port = <&cci_control1>; }; cpu4: cpu@100 { @@ -86,6 +92,7 @@ compatible = "arm,cortex-a7"; reg = <0x100>; clock-frequency = <1000000000>; + cci-control-port = <&cci_control0>; }; cpu5: cpu@101 { @@ -93,6 +100,7 @@ compatible = "arm,cortex-a7"; reg = <0x101>; clock-frequency = <1000000000>; + cci-control-port = <&cci_control0>; }; cpu6: cpu@102 { @@ -100,6 +108,7 @@ compatible = "arm,cortex-a7"; reg = <0x102>; clock-frequency = <1000000000>; + cci-control-port = <&cci_control0>; }; cpu7: cpu@103 { @@ -107,6 +116,44 @@ compatible = "arm,cortex-a7"; reg = <0x103>; clock-frequency = <1000000000>; + cci-control-port = <&cci_control0>; + }; + }; + + cci@10d20000 { + compatible = "arm,cci-400"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x10d20000 0x1000>; + ranges = <0x0 0x10d20000 0x6000>; + + cci_control0: slave-if@4000 { + compatible = "arm,cci-400-ctrl-if"; + interface-type = "ace"; + reg = <0x4000 0x1000>; + }; + cci_control1: slave-if@5000 { + compatible = "arm,cci-400-ctrl-if"; + interface-type = "ace"; + reg = <0x5000 0x1000>; + }; + }; + + sysram@02020000 { + compatible = "mmio-sram"; + reg = <0x02020000 0x54000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x02020000 0x54000>; + + smp-sysram@0 { + compatible = "samsung,exynos4210-sysram"; + reg = <0x0 0x1000>; + }; + + smp-sysram@53000 { + compatible = "samsung,exynos4210-sysram-ns"; + reg = <0x53000 0x1000>; }; }; @@ -125,12 +172,13 @@ clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in"; }; - codec@11000000 { + mfc: codec@11000000 { compatible = "samsung,mfc-v7"; reg = <0x11000000 0x10000>; interrupts = <0 96 0>; clocks = <&clock CLK_MFC>; clock-names = "mfc"; + samsung,power-domain = <&mfc_pd>; }; mmc_0: mmc@12200000 { @@ -169,7 +217,7 @@ status = "disabled"; }; - mct@101C0000 { + mct: mct@101C0000 { compatible = "samsung,exynos4210-mct"; reg = <0x101C0000 0x800>; interrupt-controller; @@ -260,7 +308,7 @@ interrupts = <0 47 0>; }; - rtc@101E0000 { + rtc: rtc@101E0000 { clocks = <&clock CLK_RTC>; clock-names = "rtc"; status = "disabled"; @@ -427,22 +475,22 @@ status = "disabled"; }; - serial@12C00000 { + uart_0: serial@12C00000 { clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; clock-names = "uart", "clk_uart_baud0"; }; - serial@12C10000 { + uart_1: serial@12C10000 { clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>; clock-names = "uart", "clk_uart_baud0"; }; - serial@12C20000 { + uart_2: serial@12C20000 { clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; clock-names = "uart", "clk_uart_baud0"; }; - serial@12C30000 { + uart_3: serial@12C30000 { clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>; clock-names = "uart", "clk_uart_baud0"; }; @@ -462,14 +510,14 @@ #phy-cells = <0>; }; - dp-controller@145B0000 { + dp: dp-controller@145B0000 { clocks = <&clock CLK_DP1>; clock-names = "dp"; phys = <&dp_phy>; phy-names = "dp"; }; - fimd@14400000 { + fimd: fimd@14400000 { samsung,power-domain = <&disp_pd>; clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>; clock-names = "sclk_fimd", "fimd"; @@ -546,7 +594,7 @@ #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&i2c4_hs_bus>; - clocks = <&clock CLK_I2C4>; + clocks = <&clock CLK_USI0>; clock-names = "hsi2c"; status = "disabled"; }; @@ -559,7 +607,7 @@ #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&i2c5_hs_bus>; - clocks = <&clock CLK_I2C5>; + clocks = <&clock CLK_USI1>; clock-names = "hsi2c"; status = "disabled"; }; @@ -572,7 +620,7 @@ #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&i2c6_hs_bus>; - clocks = <&clock CLK_I2C6>; + clocks = <&clock CLK_USI2>; clock-names = "hsi2c"; status = "disabled"; }; @@ -585,7 +633,7 @@ #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&i2c7_hs_bus>; - clocks = <&clock CLK_I2C7>; + clocks = <&clock CLK_USI3>; clock-names = "hsi2c"; status = "disabled"; }; @@ -598,7 +646,7 @@ #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&i2c8_hs_bus>; - clocks = <&clock CLK_I2C8>; + clocks = <&clock CLK_USI4>; clock-names = "hsi2c"; status = "disabled"; }; @@ -611,7 +659,7 @@ #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&i2c9_hs_bus>; - clocks = <&clock CLK_I2C9>; + clocks = <&clock CLK_USI5>; clock-names = "hsi2c"; status = "disabled"; }; @@ -624,13 +672,13 @@ #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&i2c10_hs_bus>; - clocks = <&clock CLK_I2C10>; + clocks = <&clock CLK_USI6>; clock-names = "hsi2c"; status = "disabled"; }; - hdmi@14530000 { - compatible = "samsung,exynos4212-hdmi"; + hdmi: hdmi@14530000 { + compatible = "samsung,exynos5420-hdmi"; reg = <0x14530000 0x70000>; interrupts = <0 95 0>; clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>, @@ -638,10 +686,16 @@ <&clock CLK_MOUT_HDMI>; clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", "sclk_hdmiphy", "mout_hdmi"; + phy = <&hdmiphy>; + samsung,syscon-phandle = <&pmu_system_controller>; status = "disabled"; }; - mixer@14450000 { + hdmiphy: hdmiphy@145D0000 { + reg = <0x145D0000 0x20>; + }; + + mixer: mixer@14450000 { compatible = "samsung,exynos5420-mixer"; reg = <0x14450000 0x10000>; interrupts = <0 94 0>; @@ -672,6 +726,11 @@ reg = <0x10040000 0x5000>; }; + sysreg_system_controller: syscon@10050000 { + compatible = "samsung,exynos5-sysreg", "syscon"; + reg = <0x10050000 0x5000>; + }; + tmu_cpu0: tmu@10060000 { compatible = "samsung,exynos5420-tmu"; reg = <0x10060000 0x100>; @@ -712,7 +771,7 @@ clock-names = "tmu_apbif", "tmu_triminfo_apbif"; }; - watchdog@101D0000 { + watchdog: watchdog@101D0000 { compatible = "samsung,exynos5420-wdt"; reg = <0x101D0000 0x100>; interrupts = <0 42 0>; @@ -721,11 +780,103 @@ samsung,syscon-phandle = <&pmu_system_controller>; }; - sss@10830000 { + sss: sss@10830000 { compatible = "samsung,exynos4210-secss"; reg = <0x10830000 0x10000>; interrupts = <0 112 0>; - clocks = <&clock 471>; + clocks = <&clock CLK_SSS>; clock-names = "secss"; }; + + usbdrd3_0: usb@12000000 { + compatible = "samsung,exynos5250-dwusb3"; + clocks = <&clock CLK_USBD300>; + clock-names = "usbdrd30"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + dwc3 { + compatible = "snps,dwc3"; + reg = <0x12000000 0x10000>; + interrupts = <0 72 0>; + phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>; + phy-names = "usb2-phy", "usb3-phy"; + }; + }; + + usbdrd_phy0: phy@12100000 { + compatible = "samsung,exynos5420-usbdrd-phy"; + reg = <0x12100000 0x100>; + clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>; + clock-names = "phy", "ref"; + samsung,pmu-syscon = <&pmu_system_controller>; + #phy-cells = <1>; + }; + + usbdrd3_1: usb@12400000 { + compatible = "samsung,exynos5250-dwusb3"; + clocks = <&clock CLK_USBD301>; + clock-names = "usbdrd30"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + dwc3 { + compatible = "snps,dwc3"; + reg = <0x12400000 0x10000>; + interrupts = <0 73 0>; + phys = <&usbdrd_phy1 0>, <&usbdrd_phy1 1>; + phy-names = "usb2-phy", "usb3-phy"; + }; + }; + + usbdrd_phy1: phy@12500000 { + compatible = "samsung,exynos5420-usbdrd-phy"; + reg = <0x12500000 0x100>; + clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>; + clock-names = "phy", "ref"; + samsung,pmu-syscon = <&pmu_system_controller>; + #phy-cells = <1>; + }; + + usbhost2: usb@12110000 { + compatible = "samsung,exynos4210-ehci"; + reg = <0x12110000 0x100>; + interrupts = <0 71 0>; + + clocks = <&clock CLK_USBH20>; + clock-names = "usbhost"; + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + phys = <&usb2_phy 1>; + }; + }; + + usbhost1: usb@12120000 { + compatible = "samsung,exynos4210-ohci"; + reg = <0x12120000 0x100>; + interrupts = <0 71 0>; + + clocks = <&clock CLK_USBH20>; + clock-names = "usbhost"; + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + phys = <&usb2_phy 1>; + }; + }; + + usb2_phy: phy@12130000 { + compatible = "samsung,exynos5250-usb2-phy"; + reg = <0x12130000 0x100>; + clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>; + clock-names = "phy", "ref"; + #phy-cells = <1>; + samsung,sysreg-phandle = <&sysreg_system_controller>; + samsung,pmureg-phandle = <&pmu_system_controller>; + }; }; diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi index 84f77c2fe4d4..ae3a17c791f6 100644 --- a/arch/arm/boot/dts/exynos5440.dtsi +++ b/arch/arm/boot/dts/exynos5440.dtsi @@ -176,7 +176,7 @@ clock-names = "i2c"; }; - watchdog { + watchdog@110000 { compatible = "samsung,s3c2410-wdt"; reg = <0x110000 0x1000>; interrupts = <0 1 0>; diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts new file mode 100644 index 000000000000..f3af2079a063 --- /dev/null +++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts @@ -0,0 +1,253 @@ +/* + * Google Peach Pi Rev 10+ board device tree source + * + * Copyright (c) 2014 Google, Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; +#include <dt-bindings/input/input.h> +#include <dt-bindings/gpio/gpio.h> +#include "exynos5800.dtsi" + +/ { + model = "Google Peach Pi Rev 10+"; + + compatible = "google,pi-rev16", + "google,pi-rev15", "google,pi-rev14", + "google,pi-rev13", "google,pi-rev12", + "google,pi-rev11", "google,pi-rev10", + "google,pi", "google,peach", "samsung,exynos5800", + "samsung,exynos5"; + + memory { + reg = <0x20000000 0x80000000>; + }; + + fixed-rate-clocks { + oscclk { + compatible = "samsung,exynos5420-oscclk"; + clock-frequency = <24000000>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&power_key_irq>; + + power { + label = "Power"; + gpios = <&gpx1 2 GPIO_ACTIVE_LOW>; + linux,code = <KEY_POWER>; + gpio-key,wakeup; + }; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm 0 1000000 0>; + brightness-levels = <0 100 500 1000 1500 2000 2500 2800>; + default-brightness-level = <7>; + pinctrl-0 = <&pwm0_out>; + pinctrl-names = "default"; + }; + + usb300_vbus_reg: regulator-usb300 { + compatible = "regulator-fixed"; + regulator-name = "P5.0V_USB3CON0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gph0 0 0>; + pinctrl-names = "default"; + pinctrl-0 = <&usb300_vbus_en>; + enable-active-high; + }; + + usb301_vbus_reg: regulator-usb301 { + compatible = "regulator-fixed"; + regulator-name = "P5.0V_USB3CON1"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gph0 1 0>; + pinctrl-names = "default"; + pinctrl-0 = <&usb301_vbus_en>; + enable-active-high; + }; +}; + +&pinctrl_0 { + tpm_irq: tpm-irq { + samsung,pins = "gpx1-0"; + samsung,pin-function = <0>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + power_key_irq: power-key-irq { + samsung,pins = "gpx1-2"; + samsung,pin-function = <0>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + dp_hpd_gpio: dp_hpd_gpio { + samsung,pins = "gpx2-6"; + samsung,pin-function = <0>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + hdmi_hpd_irq: hdmi-hpd-irq { + samsung,pins = "gpx3-7"; + samsung,pin-function = <0>; + samsung,pin-pud = <1>; + samsung,pin-drv = <0>; + }; +}; + +&pinctrl_3 { + usb300_vbus_en: usb300-vbus-en { + samsung,pins = "gph0-0"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + usb301_vbus_en: usb301-vbus-en { + samsung,pins = "gph0-1"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; +}; + +&rtc { + status = "okay"; +}; + +&uart_3 { + status = "okay"; +}; + +&mmc_0 { + status = "okay"; + num-slots = <1>; + broken-cd; + caps2-mmc-hs200-1_8v; + supports-highspeed; + non-removable; + card-detect-delay = <200>; + clock-frequency = <400000000>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <0 4>; + samsung,dw-mshc-ddr-timing = <0 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; + + slot@0 { + reg = <0>; + bus-width = <8>; + }; +}; + +&mmc_2 { + status = "okay"; + num-slots = <1>; + supports-highspeed; + card-detect-delay = <200>; + clock-frequency = <400000000>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <2 3>; + samsung,dw-mshc-ddr-timing = <1 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; + + slot@0 { + reg = <0>; + bus-width = <4>; + }; +}; + +&dp { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&dp_hpd_gpio>; + samsung,color-space = <0>; + samsung,dynamic-range = <0>; + samsung,ycbcr-coeff = <0>; + samsung,color-depth = <1>; + samsung,link-rate = <0x0a>; + samsung,lane-count = <2>; + samsung,hpd-gpio = <&gpx2 6 0>; + + display-timings { + native-mode = <&timing1>; + + timing1: timing@1 { + clock-frequency = <150660000>; + hactive = <1920>; + vactive = <1080>; + hfront-porch = <60>; + hback-porch = <172>; + hsync-len = <80>; + vback-porch = <25>; + vfront-porch = <10>; + vsync-len = <10>; + }; + }; +}; + +&fimd { + status = "okay"; + samsung,invert-vclk; +}; + +&hsi2c_9 { + status = "okay"; + clock-frequency = <400000>; + + tpm@20 { + compatible = "infineon,slb9645tt"; + reg = <0x20>; + /* Unused irq; but still need to configure the pins */ + pinctrl-names = "default"; + pinctrl-0 = <&tpm_irq>; + }; +}; + +&i2c_2 { + status = "okay"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <66000>; + samsung,i2c-slave-addr = <0x50>; +}; + +&hdmi { + status = "okay"; + hpd-gpio = <&gpx3 7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_hpd_irq>; + ddc = <&i2c_2>; +}; + +&usbdrd_phy0 { + vbus-supply = <&usb300_vbus_reg>; +}; + +&usbdrd_phy1 { + vbus-supply = <&usb301_vbus_reg>; +}; + +/* + * Use longest HW watchdog in SoC (32 seconds) since the hardware + * watchdog provides no debugging information (compared to soft/hard + * lockup detectors) and so should be last resort. + */ +&watchdog { + timeout-sec = <32>; +}; diff --git a/arch/arm/boot/dts/exynos5800.dtsi b/arch/arm/boot/dts/exynos5800.dtsi new file mode 100644 index 000000000000..c0bb3563cac1 --- /dev/null +++ b/arch/arm/boot/dts/exynos5800.dtsi @@ -0,0 +1,28 @@ +/* + * SAMSUNG EXYNOS5800 SoC device tree source + * + * Copyright (c) 2014 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * SAMSUNG EXYNOS5800 SoC device nodes are listed in this file. + * EXYNOS5800 based board files can include this file and provide + * values for board specfic bindings. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "exynos5420.dtsi" + +/ { + compatible = "samsung,exynos5800", "samsung,exynos5"; +}; + +&clock { + compatible = "samsung,exynos5800-clock"; +}; + +&mfc { + compatible = "samsung,mfc-v8"; +}; diff --git a/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts b/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts index 62fb3da50bdb..ad12da38fc92 100644 --- a/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts +++ b/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts @@ -172,3 +172,16 @@ fsl,uart-has-rtscts; status = "okay"; }; + +&usbhost1 { + phy_type = "serial"; + dr_mode = "host"; + status = "okay"; +}; + +&usbotg { + phy_type = "utmi"; + dr_mode = "otg"; + external-vbus-divider; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx25-karo-tx25.dts b/arch/arm/boot/dts/imx25-karo-tx25.dts index f8db366c46ff..9b31faa96377 100644 --- a/arch/arm/boot/dts/imx25-karo-tx25.dts +++ b/arch/arm/boot/dts/imx25-karo-tx25.dts @@ -16,21 +16,98 @@ model = "Ka-Ro TX25"; compatible = "karo,imx25-tx25", "fsl,imx25"; + chosen { + stdout-path = &uart1; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_fec_phy: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "fec-phy"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 9 0>; + enable-active-high; + }; + }; + memory { reg = <0x80000000 0x02000000 0x90000000 0x02000000>; }; }; +&iomuxc { + pinctrl_uart1: uart1grp { + fsl,pins = < + MX25_PAD_UART1_TXD__UART1_TXD 0x80000000 + MX25_PAD_UART1_RXD__UART1_RXD 0x80000000 + MX25_PAD_UART1_CTS__UART1_CTS 0x80000000 + MX25_PAD_UART1_RTS__UART1_RTS 0x80000000 + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX25_PAD_D11__GPIO_4_9 0x80000000 /* FEC PHY power on pin */ + MX25_PAD_D13__GPIO_4_7 0x80000000 /* FEC reset */ + MX25_PAD_FEC_MDC__FEC_MDC 0x80000000 + MX25_PAD_FEC_MDIO__FEC_MDIO 0x80000000 + MX25_PAD_FEC_TDATA0__FEC_TDATA0 0x80000000 + MX25_PAD_FEC_TDATA1__FEC_TDATA1 0x80000000 + MX25_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 + MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x80000000 + MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x80000000 + MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x80000000 + MX25_PAD_FEC_TX_CLK__FEC_TX_CLK 0x80000000 + >; + }; + + pinctrl_nfc: nfcgrp { + fsl,pins = < + MX25_PAD_NF_CE0__NF_CE0 0x80000000 + MX25_PAD_NFWE_B__NFWE_B 0x80000000 + MX25_PAD_NFRE_B__NFRE_B 0x80000000 + MX25_PAD_NFALE__NFALE 0x80000000 + MX25_PAD_NFCLE__NFCLE 0x80000000 + MX25_PAD_NFWP_B__NFWP_B 0x80000000 + MX25_PAD_NFRB__NFRB 0x80000000 + MX25_PAD_D7__D7 0x80000000 + MX25_PAD_D6__D6 0x80000000 + MX25_PAD_D5__D5 0x80000000 + MX25_PAD_D4__D4 0x80000000 + MX25_PAD_D3__D3 0x80000000 + MX25_PAD_D2__D2 0x80000000 + MX25_PAD_D1__D1 0x80000000 + MX25_PAD_D0__D0 0x80000000 + >; + }; +}; + &uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; status = "okay"; }; &fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-reset-gpios = <&gpio3 7 0>; phy-mode = "rmii"; + phy-supply = <®_fec_phy>; status = "okay"; }; &nfc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nfc>; nand-on-flash-bbt; + nand-ecc-mode = "hw"; + nand-bus-width = <8>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx25-pdk.dts b/arch/arm/boot/dts/imx25-pdk.dts index f607ce520eda..c608942b8a3b 100644 --- a/arch/arm/boot/dts/imx25-pdk.dts +++ b/arch/arm/boot/dts/imx25-pdk.dts @@ -10,6 +10,7 @@ */ /dts-v1/; +#include <dt-bindings/input/input.h> #include "imx25.dtsi" / { @@ -19,18 +20,232 @@ memory { reg = <0x80000000 0x4000000>; }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_fec_3v3: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "fec-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 3 0>; + enable-active-high; + }; + + reg_2p5v: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + }; + + reg_3p3v: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_can_3v3: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "can-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 6 0>; + }; + }; + + sound { + compatible = "fsl,imx25-pdk-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "imx25-pdk-sgtl5000"; + ssi-controller = <&ssi1>; + audio-codec = <&codec>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + mux-int-port = <1>; + mux-ext-port = <4>; + }; }; -&uart1 { +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1>; + xceiver-supply = <®_can_3v3>; + status = "okay"; +}; + +&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1>; + cd-gpios = <&gpio2 1 0>; + wp-gpios = <&gpio2 0 0>; status = "okay"; }; &fec { phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-supply = <®_fec_3v3>; + phy-reset-gpios = <&gpio4 8 0>; status = "okay"; }; +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + codec: sgtl5000@0a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + clocks = <&clks 129>; + VDDA-supply = <®_2p5v>; + VDDIO-supply = <®_3p3v>; + }; +}; + +&iomuxc { + imx25-pdk { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX25_PAD_RW__AUD4_TXFS 0xe0 + MX25_PAD_OE__AUD4_TXC 0xe0 + MX25_PAD_EB0__AUD4_TXD 0xe0 + MX25_PAD_EB1__AUD4_RXD 0xe0 + >; + }; + + pinctrl_can1: can1grp { + fsl,pins = < + MX25_PAD_GPIO_A__CAN1_TX 0x0 + MX25_PAD_GPIO_B__CAN1_RX 0x0 + MX25_PAD_D14__GPIO_4_6 0x80000000 + >; + }; + + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + MX25_PAD_SD1_CMD__SD1_CMD 0x80000000 + MX25_PAD_SD1_CLK__SD1_CLK 0x80000000 + MX25_PAD_SD1_DATA0__SD1_DATA0 0x80000000 + MX25_PAD_SD1_DATA1__SD1_DATA1 0x80000000 + MX25_PAD_SD1_DATA2__SD1_DATA2 0x80000000 + MX25_PAD_SD1_DATA3__SD1_DATA3 0x80000000 + MX25_PAD_A14__GPIO_2_0 0x80000000 + MX25_PAD_A15__GPIO_2_1 0x80000000 + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX25_PAD_FEC_MDC__FEC_MDC 0x80000000 + MX25_PAD_FEC_MDIO__FEC_MDIO 0x400001e0 + MX25_PAD_FEC_TDATA0__FEC_TDATA0 0x80000000 + MX25_PAD_FEC_TDATA1__FEC_TDATA1 0x80000000 + MX25_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 + MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x80000000 + MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x80000000 + MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x80000000 + MX25_PAD_FEC_TX_CLK__FEC_TX_CLK 0x1c0 + MX25_PAD_A17__GPIO_2_3 0x80000000 + MX25_PAD_D12__GPIO_4_8 0x80000000 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX25_PAD_I2C1_CLK__I2C1_CLK 0x80000000 + MX25_PAD_I2C1_DAT__I2C1_DAT 0x80000000 + >; + }; + + pinctrl_kpp: kppgrp { + fsl,pins = < + MX25_PAD_KPP_ROW0__KPP_ROW0 0x80000000 + MX25_PAD_KPP_ROW1__KPP_ROW1 0x80000000 + MX25_PAD_KPP_ROW2__KPP_ROW2 0x80000000 + MX25_PAD_KPP_ROW3__KPP_ROW3 0x80000000 + MX25_PAD_KPP_COL0__KPP_COL0 0x80000000 + MX25_PAD_KPP_COL1__KPP_COL1 0x80000000 + MX25_PAD_KPP_COL2__KPP_COL2 0x80000000 + MX25_PAD_KPP_COL3__KPP_COL3 0x80000000 + >; + }; + + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX25_PAD_UART1_RTS__UART1_RTS 0xe0 + MX25_PAD_UART1_CTS__UART1_CTS 0xe0 + MX25_PAD_UART1_TXD__UART1_TXD 0x80000000 + MX25_PAD_UART1_RXD__UART1_RXD 0xc0 + >; + }; + }; +}; + &nfc { nand-on-flash-bbt; status = "okay"; }; + +&kpp { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_kpp>; + linux,keymap = < + MATRIX_KEY(0x0, 0x0, KEY_UP) + MATRIX_KEY(0x0, 0x1, KEY_DOWN) + MATRIX_KEY(0x0, 0x2, KEY_VOLUMEDOWN) + MATRIX_KEY(0x0, 0x3, KEY_HOME) + MATRIX_KEY(0x1, 0x0, KEY_RIGHT) + MATRIX_KEY(0x1, 0x1, KEY_LEFT) + MATRIX_KEY(0x1, 0x2, KEY_ENTER) + MATRIX_KEY(0x1, 0x3, KEY_VOLUMEUP) + MATRIX_KEY(0x2, 0x0, KEY_F6) + MATRIX_KEY(0x2, 0x1, KEY_F8) + MATRIX_KEY(0x2, 0x2, KEY_F9) + MATRIX_KEY(0x2, 0x3, KEY_F10) + MATRIX_KEY(0x3, 0x0, KEY_F1) + MATRIX_KEY(0x3, 0x1, KEY_F2) + MATRIX_KEY(0x3, 0x2, KEY_F3) + MATRIX_KEY(0x3, 0x2, KEY_POWER) + >; + status = "okay"; +}; + +&ssi1 { + codec-handle = <&codec>; + fsl,mode = "i2s-slave"; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + fsl,uart-has-rtscts; + status = "okay"; +}; + +&usbhost1 { + phy_type = "serial"; + dr_mode = "host"; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi index ea323f09dc78..bb74d9582b7e 100644 --- a/arch/arm/boot/dts/imx25.dtsi +++ b/arch/arm/boot/dts/imx25.dtsi @@ -14,6 +14,7 @@ / { aliases { + ethernet0 = &fec; gpio0 = &gpio1; gpio1 = &gpio2; gpio2 = &gpio3; @@ -21,6 +22,8 @@ i2c0 = &i2c1; i2c1 = &i2c2; i2c2 = &i2c3; + mmc0 = &esdhc1; + mmc1 = &esdhc2; serial0 = &uart1; serial1 = &uart2; serial2 = &uart3; @@ -165,9 +168,10 @@ status = "disabled"; }; - kpp@43fa8000 { + kpp: kpp@43fa8000 { #address-cells = <1>; #size-cells = <0>; + compatible = "fsl,imx25-kpp", "fsl,imx21-kpp"; reg = <0x43fa8000 0x4000>; clocks = <&clks 102>; clock-names = ""; @@ -482,23 +486,13 @@ clocks = <&clks 99>; }; - usbphy1: usbphy@1 { - compatible = "nop-usbphy"; - status = "disabled"; - }; - - usbphy2: usbphy@2 { - compatible = "nop-usbphy"; - status = "disabled"; - }; - usbotg: usb@53ff4000 { compatible = "fsl,imx25-usb", "fsl,imx27-usb"; reg = <0x53ff4000 0x0200>; interrupts = <37>; - clocks = <&clks 9>, <&clks 70>, <&clks 8>; - clock-names = "ipg", "ahb", "per"; + clocks = <&clks 70>; fsl,usbmisc = <&usbmisc 0>; + fsl,usbphy = <&usbphy0>; status = "disabled"; }; @@ -506,9 +500,9 @@ compatible = "fsl,imx25-usb", "fsl,imx27-usb"; reg = <0x53ff4400 0x0200>; interrupts = <35>; - clocks = <&clks 9>, <&clks 70>, <&clks 8>; - clock-names = "ipg", "ahb", "per"; + clocks = <&clks 70>; fsl,usbmisc = <&usbmisc 1>; + fsl,usbphy = <&usbphy1>; status = "disabled"; }; @@ -518,7 +512,6 @@ clocks = <&clks 9>, <&clks 70>, <&clks 8>; clock-names = "ipg", "ahb", "per"; reg = <0x53ff4600 0x00f>; - status = "disabled"; }; dryice@53ffc000 { @@ -530,6 +523,11 @@ }; }; + iram: sram@78000000 { + compatible = "mmio-sram"; + reg = <0x78000000 0x20000>; + }; + emi@80000000 { compatible = "fsl,emi-bus", "simple-bus"; #address-cells = <1>; @@ -550,4 +548,20 @@ }; }; }; + + usbphy { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + usbphy0: usb-phy@0 { + reg = <0>; + compatible = "usb-nop-xceiv"; + }; + + usbphy1: usb-phy@1 { + reg = <1>; + compatible = "usb-nop-xceiv"; + }; + }; }; diff --git a/arch/arm/boot/dts/imx27-pdk.dts b/arch/arm/boot/dts/imx27-pdk.dts index 5ce89aa275df..4c317716b510 100644 --- a/arch/arm/boot/dts/imx27-pdk.dts +++ b/arch/arm/boot/dts/imx27-pdk.dts @@ -17,15 +17,181 @@ compatible = "fsl,imx27-pdk", "fsl,imx27"; memory { - reg = <0x0 0x0>; + reg = <0xa0000000 0x08000000>; }; + + usbphy { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + usbphy0: usbphy@0 { + compatible = "usb-nop-xceiv"; + reg = <0>; + clocks = <&clks 0>; + clock-names = "main_clk"; + }; + }; +}; + +&cspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_cspi2>; + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pmic: mc13783@0 { + compatible = "fsl,mc13783"; + reg = <0>; + spi-cs-high; + spi-max-frequency = <1000000>; + interrupt-parent = <&gpio3>; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; + + regulators { + vgen_reg: vgen { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + vmmc1_reg: vmmc1 { + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3000000>; + }; + + gpo1_reg: gpo1 { + regulator-always-on; + regulator-boot-on; + }; + + gpo3_reg: gpo3 { + regulator-always-on; + regulator-boot-on; + }; + }; + }; +}; + +&fec { + phy-mode = "mii"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + status = "okay"; +}; + +&kpp { + linux,keymap = < + MATRIX_KEY(0, 0, KEY_UP) + MATRIX_KEY(0, 1, KEY_DOWN) + MATRIX_KEY(1, 0, KEY_RIGHT) + MATRIX_KEY(1, 1, KEY_LEFT) + MATRIX_KEY(1, 2, KEY_ENTER) + MATRIX_KEY(2, 0, KEY_F6) + MATRIX_KEY(2, 1, KEY_F8) + MATRIX_KEY(2, 2, KEY_F9) + MATRIX_KEY(2, 3, KEY_F10) + >; + status = "okay"; +}; + +&nfc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nand>; + nand-ecc-mode = "hw"; + nand-on-flash-bbt; + status = "okay"; }; &uart1 { fsl,uart-has-rtscts; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; status = "okay"; }; -&fec { +&usbotg { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + dr_mode = "otg"; + fsl,usbphy = <&usbphy0>; + phy_type = "ulpi"; status = "okay"; }; + +&iomuxc { + imx27-pdk { + pinctrl_cspi2: cspi2grp { + fsl,pins = < + MX27_PAD_CSPI2_MISO__CSPI2_MISO 0x0 + MX27_PAD_CSPI2_MOSI__CSPI2_MOSI 0x0 + MX27_PAD_CSPI2_SCLK__CSPI2_SCLK 0x0 + MX27_PAD_CSPI2_SS0__GPIO4_21 0x0 /* SPI2 CS0 */ + MX27_PAD_TOUT__GPIO3_14 0x0 /* PMIC IRQ */ + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX27_PAD_SD3_CMD__FEC_TXD0 0x0 + MX27_PAD_SD3_CLK__FEC_TXD1 0x0 + MX27_PAD_ATA_DATA0__FEC_TXD2 0x0 + MX27_PAD_ATA_DATA1__FEC_TXD3 0x0 + MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0 + MX27_PAD_ATA_DATA3__FEC_RXD1 0x0 + MX27_PAD_ATA_DATA4__FEC_RXD2 0x0 + MX27_PAD_ATA_DATA5__FEC_RXD3 0x0 + MX27_PAD_ATA_DATA6__FEC_MDIO 0x0 + MX27_PAD_ATA_DATA7__FEC_MDC 0x0 + MX27_PAD_ATA_DATA8__FEC_CRS 0x0 + MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0 + MX27_PAD_ATA_DATA10__FEC_RXD0 0x0 + MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0 + MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0 + MX27_PAD_ATA_DATA13__FEC_COL 0x0 + MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0 + MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0 + >; + }; + + pinctrl_nand: nandgrp { + fsl,pins = < + MX27_PAD_NFRB__NFRB 0x0 + MX27_PAD_NFCLE__NFCLE 0x0 + MX27_PAD_NFWP_B__NFWP_B 0x0 + MX27_PAD_NFCE_B__NFCE_B 0x0 + MX27_PAD_NFALE__NFALE 0x0 + MX27_PAD_NFRE_B__NFRE_B 0x0 + MX27_PAD_NFWE_B__NFWE_B 0x0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX27_PAD_UART1_TXD__UART1_TXD 0x0 + MX27_PAD_UART1_RXD__UART1_RXD 0x0 + MX27_PAD_UART1_CTS__UART1_CTS 0x0 + MX27_PAD_UART1_RTS__UART1_RTS 0x0 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX27_PAD_USBOTG_NXT__USBOTG_NXT 0x0 + MX27_PAD_USBOTG_STP__USBOTG_STP 0x0 + MX27_PAD_USBOTG_DIR__USBOTG_DIR 0x0 + MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x0 + MX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x0 + MX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x0 + MX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x0 + MX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x0 + MX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x0 + MX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x0 + MX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x0 + MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x0 + >; + }; + }; +}; diff --git a/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts b/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts index 3c3964a99637..7c869fe3c30b 100644 --- a/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts +++ b/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts @@ -15,6 +15,10 @@ model = "Phytec pca100 rapid development kit"; compatible = "phytec,imx27-pca100-rdk", "phytec,imx27-pca100", "fsl,imx27"; + chosen { + stdout-path = &uart1; + }; + display: display { model = "Primeview-PD050VL1"; native-mode = <&timing0>; diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts index df3b2e731835..fe02bc7a24fd 100644 --- a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts +++ b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts @@ -12,14 +12,79 @@ / { model = "Phytec pcm970"; compatible = "phytec,imx27-pcm970", "phytec,imx27-pcm038", "fsl,imx27"; + + chosen { + stdout-path = &uart1; + }; + + display0: LQ035Q7 { + model = "Sharp-LQ035Q7"; + native-mode = <&timing0>; + bits-per-pixel = <16>; + fsl,pcr = <0xf00080c0>; + + display-timings { + timing0: 240x320 { + clock-frequency = <5500000>; + hactive = <240>; + vactive = <320>; + hback-porch = <5>; + hsync-len = <7>; + hfront-porch = <16>; + vback-porch = <7>; + vsync-len = <1>; + vfront-porch = <9>; + pixelclk-active = <1>; + hsync-active = <1>; + vsync-active = <1>; + de-active = <0>; + }; + }; + }; + + regulators { + regulator@2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csien>; + reg = <2>; + regulator-name = "CSI_EN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 24 GPIO_ACTIVE_LOW>; + regulator-always-on; + }; + }; + + usbphy { + usbphy2: usbphy@2 { + compatible = "usb-nop-xceiv"; + reg = <2>; + vcc-supply = <®_5v0>; + clocks = <&clks 0>; + clock-names = "main_clk"; + }; + }; }; &cspi1 { + pinctrl-0 = <&pinctrl_cspi1>, <&pinctrl_cspi1cs1>; fsl,spi-num-chipselects = <2>; cs-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>, <&gpio4 27 GPIO_ACTIVE_LOW>; }; +&fb { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_imxfb1>; + display = <&display0>; + lcd-supply = <®_5v0>; + fsl,dmacr = <0x00020010>; + fsl,lscr1 = <0x00120300>; + fsl,lpccr = <0x00a903ff>; + status = "okay"; +}; + &i2c1 { clock-frequency = <400000>; pinctrl-names = "default"; @@ -36,6 +101,50 @@ &iomuxc { imx27_phycore_rdk { + pinctrl_csien: csiengrp { + fsl,pins = < + MX27_PAD_USB_OC_B__GPIO2_24 0x0 + >; + }; + + pinctrl_cspi1cs1: cspi1cs1grp { + fsl,pins = < + MX27_PAD_CSPI1_SS1__GPIO4_27 0x0 + >; + }; + + pinctrl_imxfb1: imxfbgrp { + fsl,pins = < + MX27_PAD_LD0__LD0 0x0 + MX27_PAD_LD1__LD1 0x0 + MX27_PAD_LD2__LD2 0x0 + MX27_PAD_LD3__LD3 0x0 + MX27_PAD_LD4__LD4 0x0 + MX27_PAD_LD5__LD5 0x0 + MX27_PAD_LD6__LD6 0x0 + MX27_PAD_LD7__LD7 0x0 + MX27_PAD_LD8__LD8 0x0 + MX27_PAD_LD9__LD9 0x0 + MX27_PAD_LD10__LD10 0x0 + MX27_PAD_LD11__LD11 0x0 + MX27_PAD_LD12__LD12 0x0 + MX27_PAD_LD13__LD13 0x0 + MX27_PAD_LD14__LD14 0x0 + MX27_PAD_LD15__LD15 0x0 + MX27_PAD_LD16__LD16 0x0 + MX27_PAD_LD17__LD17 0x0 + MX27_PAD_CLS__CLS 0x0 + MX27_PAD_CONTRAST__CONTRAST 0x0 + MX27_PAD_LSCLK__LSCLK 0x0 + MX27_PAD_OE_ACD__OE_ACD 0x0 + MX27_PAD_PS__PS 0x0 + MX27_PAD_REV__REV 0x0 + MX27_PAD_SPL_SPR__SPL_SPR 0x0 + MX27_PAD_HSYNC__HSYNC 0x0 + MX27_PAD_VSYNC__VSYNC 0x0 + >; + }; + pinctrl_i2c1: i2c1grp { /* Add pullup to DATA line */ fsl,pins = < @@ -193,19 +302,16 @@ dr_mode = "host"; phy_type = "ulpi"; vbus-supply = <®_5v0>; + fsl,usbphy = <&usbphy2>; disable-over-current; status = "okay"; }; -&usbphy2 { - vcc-supply = <®_5v0>; -}; - &weim { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_weim>; - can@d4000000 { + can@4,0 { compatible = "nxp,sja1000"; reg = <4 0x00000000 0x00000100>; interrupt-parent = <&gpio5>; diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi index cefaa6994623..31e9f7049f73 100644 --- a/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi +++ b/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi @@ -41,6 +41,20 @@ regulator-max-microvolt = <5000000>; }; }; + + usbphy { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + usbphy0: usbphy@0 { + compatible = "usb-nop-xceiv"; + reg = <0>; + vcc-supply = <&sw3_reg>; + clocks = <&clks 0>; + clock-names = "main_clk"; + }; + }; }; &audmux { @@ -66,9 +80,9 @@ status = "okay"; pmic: mc13783@0 { - #address-cells = <1>; - #size-cells = <0>; compatible = "fsl,mc13783"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; reg = <0>; spi-cs-high; spi-max-frequency = <20000000>; @@ -166,7 +180,7 @@ &fec { phy-mode = "mii"; - phy-reset-gpios = <&gpio3 30 GPIO_ACTIVE_HIGH>; + phy-reset-gpios = <&gpio3 30 GPIO_ACTIVE_LOW>; phy-supply = <®_3v3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec1>; @@ -204,7 +218,6 @@ MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x0 MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x0 MX27_PAD_CSPI1_SS0__GPIO4_28 0x0 /* SPI1 CS0 */ - MX27_PAD_USB_PWR__GPIO2_23 0x0 /* PMIC IRQ */ >; }; @@ -251,6 +264,21 @@ >; }; + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX27_PAD_USB_PWR__GPIO2_23 0x0 /* PMIC IRQ */ + >; + }; + + pinctrl_ssi1: ssi1grp { + fsl,pins = < + MX27_PAD_SSI1_FS__SSI1_FS 0x0 + MX27_PAD_SSI1_RXDAT__SSI1_RXDAT 0x0 + MX27_PAD_SSI1_TXDAT__SSI1_TXDAT 0x0 + MX27_PAD_SSI1_CLK__SSI1_CLK 0x0 + >; + }; + pinctrl_usbotg: usbotggrp { fsl,pins = < MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x0 @@ -279,23 +307,28 @@ status = "okay"; }; +&ssi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ssi1>; + fsl,mode = "i2s-slave"; + status = "okay"; +}; + &usbotg { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usbotg>; dr_mode = "otg"; phy_type = "ulpi"; + fsl,usbphy = <&usbphy0>; vbus-supply = <&sw3_reg>; + disable-over-current; status = "okay"; }; -&usbphy0 { - vcc-supply = <&sw3_reg>; -}; - &weim { status = "okay"; - nor: nor@c0000000 { + nor: nor@0,0 { compatible = "cfi-flash"; reg = <0 0x00000000 0x02000000>; bank-width = <2>; @@ -305,7 +338,7 @@ #size-cells = <1>; }; - sram: sram@c8000000 { + sram: sram@1,0 { compatible = "mtd-ram"; reg = <1 0x00000000 0x00800000>; bank-width = <2>; diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi index 137e010eab35..a75555c39533 100644 --- a/arch/arm/boot/dts/imx27.dtsi +++ b/arch/arm/boot/dts/imx27.dtsi @@ -11,11 +11,13 @@ #include "skeleton.dtsi" #include "imx27-pinfunc.h" +#include <dt-bindings/input/input.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/gpio/gpio.h> / { aliases { + ethernet0 = &fec; gpio0 = &gpio1; gpio1 = &gpio2; gpio2 = &gpio3; @@ -71,26 +73,6 @@ }; }; - usbphy { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - usbphy0: usbphy@0 { - compatible = "usb-nop-xceiv"; - reg = <0>; - clocks = <&clks 75>; - clock-names = "main_clk"; - }; - - usbphy2: usbphy@2 { - compatible = "usb-nop-xceiv"; - reg = <2>; - clocks = <&clks 75>; - clock-names = "main_clk"; - }; - }; - soc { #address-cells = <1>; #size-cells = <1>; @@ -464,9 +446,8 @@ compatible = "fsl,imx27-usb"; reg = <0x10024000 0x200>; interrupts = <56>; - clocks = <&clks 15>; + clocks = <&clks 75>; fsl,usbmisc = <&usbmisc 0>; - fsl,usbphy = <&usbphy0>; status = "disabled"; }; @@ -474,7 +455,7 @@ compatible = "fsl,imx27-usb"; reg = <0x10024200 0x200>; interrupts = <54>; - clocks = <&clks 15>; + clocks = <&clks 75>; fsl,usbmisc = <&usbmisc 1>; status = "disabled"; }; @@ -483,9 +464,8 @@ compatible = "fsl,imx27-usb"; reg = <0x10024400 0x200>; interrupts = <55>; - clocks = <&clks 15>; + clocks = <&clks 75>; fsl,usbmisc = <&usbmisc 2>; - fsl,usbphy = <&usbphy2>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/imx28-duckbill.dts b/arch/arm/boot/dts/imx28-duckbill.dts index 5f326c1c1850..ce1a7effba37 100644 --- a/arch/arm/boot/dts/imx28-duckbill.dts +++ b/arch/arm/boot/dts/imx28-duckbill.dts @@ -25,9 +25,9 @@ ssp0: ssp@80010000 { compatible = "fsl,imx28-mmc"; pinctrl-names = "default"; - pinctrl-0 = <&mmc0_8bit_pins_a + pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_cd_cfg &mmc0_sck_cfg>; - bus-width = <8>; + bus-width = <4>; vmmc-supply = <®_3p3v>; status = "okay"; }; @@ -39,7 +39,7 @@ hog_pins_a: hog@0 { reg = <0>; fsl,pinmux-ids = < - MX28_PAD_ENET0_RX_CLK__GPIO_4_13 /* PHY Reset */ + MX28_PAD_SSP0_DATA7__GPIO_2_7 /* PHY Reset */ >; fsl,drive-strength = <MXS_DRIVE_4mA>; fsl,voltage = <MXS_VOLTAGE_HIGH>; @@ -82,7 +82,7 @@ pinctrl-names = "default"; pinctrl-0 = <&mac0_pins_a>; phy-supply = <®_3p3v>; - phy-reset-gpios = <&gpio4 13 0>; + phy-reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>; phy-reset-duration = <100>; status = "okay"; }; @@ -110,12 +110,12 @@ status { label = "duckbill:green:status"; - gpios = <&gpio3 5 0>; + gpios = <&gpio3 5 GPIO_ACTIVE_HIGH>; }; failure { label = "duckbill:red:status"; - gpios = <&gpio3 4 0>; + gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>; }; }; }; diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi index 90a579532b8b..a95cc5358ff4 100644 --- a/arch/arm/boot/dts/imx28.dtsi +++ b/arch/arm/boot/dts/imx28.dtsi @@ -9,6 +9,7 @@ * http://www.gnu.org/copyleft/gpl.html */ +#include <dt-bindings/gpio/gpio.h> #include "skeleton.dtsi" #include "imx28-pinfunc.h" diff --git a/arch/arm/boot/dts/imx35-eukrea-cpuimx35.dtsi b/arch/arm/boot/dts/imx35-eukrea-cpuimx35.dtsi index 906ae937b013..9c2b715ab8bf 100644 --- a/arch/arm/boot/dts/imx35-eukrea-cpuimx35.dtsi +++ b/arch/arm/boot/dts/imx35-eukrea-cpuimx35.dtsi @@ -37,6 +37,17 @@ compatible = "nxp,pcf8563"; reg = <0x51>; }; + + tsc2007: tsc2007@48 { + compatible = "ti,tsc2007"; + gpios = <&gpio3 2 0>; + interrupt-parent = <&gpio3>; + interrupts = <0x2 0x8>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tsc2007_1>; + reg = <0x48>; + ti,x-plate-ohms = <180>; + }; }; &iomuxc { @@ -70,6 +81,10 @@ MX35_PAD_I2C1_DAT__I2C1_SDA 0x80000000 >; }; + + pinctrl_tsc2007_1: tsc2007grp-1 { + fsl,pins = <MX35_PAD_ATA_DA2__GPIO3_2 0x80000000>; + }; }; }; diff --git a/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts b/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts index 1bdec21f4533..f04ae91eea89 100644 --- a/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts +++ b/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts @@ -46,6 +46,14 @@ linux,default-trigger = "heartbeat"; }; }; + + sound { + compatible = "eukrea,asoc-tlv320"; + eukrea,model = "imx35-eukrea-tlv320aic23"; + ssi-controller = <&ssi1>; + fsl,mux-int-port = <1>; + fsl,mux-ext-port = <4>; + }; }; &audmux { @@ -124,6 +132,7 @@ }; &ssi1 { + codec-handle = <&tlv320aic23>; fsl,mode = "i2s-slave"; status = "okay"; }; @@ -141,3 +150,16 @@ fsl,uart-has-rtscts; status = "okay"; }; + +&usbhost1 { + phy_type = "serial"; + dr_mode = "host"; + status = "okay"; +}; + +&usbotg { + phy_type = "utmi"; + dr_mode = "otg"; + external-vbus-divider; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx35-pdk.dts b/arch/arm/boot/dts/imx35-pdk.dts new file mode 100644 index 000000000000..8d715523708f --- /dev/null +++ b/arch/arm/boot/dts/imx35-pdk.dts @@ -0,0 +1,68 @@ +/* + * Copyright 2013 Eukréa Electromatique <denis@eukrea.com> + * Copyright 2014 Freescale Semiconductor, Inc. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include "imx35.dtsi" + +/ { + model = "Freescale i.MX35 Product Development Kit"; + compatible = "fsl,imx35-pdk", "fsl,imx35"; + + memory { + reg = <0x80000000 0x8000000>, + <0x90000000 0x8000000>; + }; +}; + +&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1>; + status = "okay"; +}; + +&iomuxc { + imx35-pdk { + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + MX35_PAD_SD1_CMD__ESDHC1_CMD 0x80000000 + MX35_PAD_SD1_CLK__ESDHC1_CLK 0x80000000 + MX35_PAD_SD1_DATA0__ESDHC1_DAT0 0x80000000 + MX35_PAD_SD1_DATA1__ESDHC1_DAT1 0x80000000 + MX35_PAD_SD1_DATA2__ESDHC1_DAT2 0x80000000 + MX35_PAD_SD1_DATA3__ESDHC1_DAT3 0x80000000 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX35_PAD_TXD1__UART1_TXD_MUX 0x1c5 + MX35_PAD_RXD1__UART1_RXD_MUX 0x1c5 + MX35_PAD_CTS1__UART1_CTS 0x1c5 + MX35_PAD_RTS1__UART1_RTS 0x1c5 + >; + }; + }; +}; + +&nfc { + nand-bus-width = <16>; + nand-ecc-mode = "hw"; + nand-on-flash-bbt; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + fsl,uart-has-rtscts; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx35.dtsi b/arch/arm/boot/dts/imx35.dtsi index 88b218f8f810..4759abb49436 100644 --- a/arch/arm/boot/dts/imx35.dtsi +++ b/arch/arm/boot/dts/imx35.dtsi @@ -13,6 +13,7 @@ / { aliases { + ethernet0 = &fec; gpio0 = &gpio1; gpio1 = &gpio2; gpio2 = &gpio3; @@ -295,9 +296,9 @@ compatible = "fsl,imx35-usb", "fsl,imx27-usb"; reg = <0x53ff4000 0x0200>; interrupts = <37>; - clocks = <&clks 9>, <&clks 73>, <&clks 28>; - clock-names = "ipg", "ahb", "per"; + clocks = <&clks 73>; fsl,usbmisc = <&usbmisc 0>; + fsl,usbphy = <&usbphy0>; status = "disabled"; }; @@ -305,9 +306,9 @@ compatible = "fsl,imx35-usb", "fsl,imx27-usb"; reg = <0x53ff4400 0x0200>; interrupts = <35>; - clocks = <&clks 9>, <&clks 73>, <&clks 28>; - clock-names = "ipg", "ahb", "per"; + clocks = <&clks 73>; fsl,usbmisc = <&usbmisc 1>; + fsl,usbphy = <&usbphy1>; status = "disabled"; }; @@ -356,4 +357,20 @@ }; }; }; + + usbphy { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + usbphy0: usb-phy@0 { + reg = <0>; + compatible = "usb-nop-xceiv"; + }; + + usbphy1: usb-phy@1 { + reg = <1>; + compatible = "usb-nop-xceiv"; + }; + }; }; diff --git a/arch/arm/boot/dts/imx50.dtsi b/arch/arm/boot/dts/imx50.dtsi index 9c89d1ca97c2..6a201cf54366 100644 --- a/arch/arm/boot/dts/imx50.dtsi +++ b/arch/arm/boot/dts/imx50.dtsi @@ -17,6 +17,7 @@ / { aliases { + ethernet0 = &fec; gpio0 = &gpio1; gpio1 = &gpio2; gpio2 = &gpio3; diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts index 9e9deb244b76..6bc3243a80d3 100644 --- a/arch/arm/boot/dts/imx51-babbage.dts +++ b/arch/arm/boot/dts/imx51-babbage.dts @@ -17,10 +17,28 @@ model = "Freescale i.MX51 Babbage Board"; compatible = "fsl,imx51-babbage", "fsl,imx51"; + chosen { + stdout-path = &uart1; + }; + memory { reg = <0x90000000 0x20000000>; }; + clocks { + ckih1 { + clock-frequency = <22579200>; + }; + + clk_26M: codec_clock { + compatible = "fixed-clock"; + reg=<0>; + #clock-cells = <0>; + clock-frequency = <26000000>; + gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; + }; + }; + display0: display@di0 { compatible = "fsl,imx-parallel-display"; interface-pix-fmt = "rgb24"; @@ -82,11 +100,13 @@ gpio-keys { compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; power { label = "Power Button"; gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>; - linux,code = <116>; /* KEY_POWER */ + linux,code = <KEY_POWER>; gpio-key,wakeup; }; }; @@ -102,6 +122,36 @@ }; }; + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usbh1_vbus: regulator@0 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1reg>; + reg = <0>; + regulator-name = "usbh1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio2 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usbotg_vbus: regulator@1 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotgreg>; + reg = <1>; + regulator-name = "usbotg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; + sound { compatible = "fsl,imx51-babbage-sgtl5000", "fsl,imx-audio-sgtl5000"; @@ -116,41 +166,23 @@ mux-ext-port = <3>; }; - clocks { - ckih1 { - clock-frequency = <22579200>; - }; + usbphy { + #address-cells = <1>; + #size-cells = <0>; + compatible = "simple-bus"; - clk_26M: codec_clock { - compatible = "fixed-clock"; - reg=<0>; - #clock-cells = <0>; - clock-frequency = <26000000>; - gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; + usbh1phy: usbh1phy@0 { + compatible = "usb-nop-xceiv"; + reg = <0>; + clocks = <&clks IMX5_CLK_DUMMY>; + clock-names = "main_clk"; }; }; }; -&esdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc1>; - fsl,cd-controller; - fsl,wp-controller; - status = "okay"; -}; - -&esdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_esdhc2>; - cd-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; - wp-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&uart3 { +&audmux { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - fsl,uart-has-rtscts; + pinctrl-0 = <&pinctrl_audmux>; status = "okay"; }; @@ -163,9 +195,9 @@ status = "okay"; pmic: mc13892@0 { - #address-cells = <1>; - #size-cells = <0>; compatible = "fsl,mc13892"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; spi-max-frequency = <6000000>; spi-cs-high; reg = <0>; @@ -280,6 +312,53 @@ }; }; +&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1>; + fsl,cd-controller; + fsl,wp-controller; + status = "okay"; +}; + +&esdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc2>; + cd-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; + wp-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "mii"; + phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>; + phy-reset-duration = <1>; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + sgtl5000: codec@0a { + compatible = "fsl,sgtl5000"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_clkcodec>; + reg = <0x0a>; + clocks = <&clk_26M>; + VDDA-supply = <&vdig_reg>; + VDDIO-supply = <&vvideo_reg>; + }; +}; + &ipu_di0_disp0 { remote-endpoint = <&display0_in>; }; @@ -288,29 +367,74 @@ remote-endpoint = <&display1_in>; }; +&kpp { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_kpp>; + linux,keymap = < + MATRIX_KEY(0, 0, KEY_UP) + MATRIX_KEY(0, 1, KEY_DOWN) + MATRIX_KEY(0, 2, KEY_VOLUMEDOWN) + MATRIX_KEY(0, 3, KEY_HOME) + MATRIX_KEY(1, 0, KEY_RIGHT) + MATRIX_KEY(1, 1, KEY_LEFT) + MATRIX_KEY(1, 2, KEY_ENTER) + MATRIX_KEY(1, 3, KEY_VOLUMEUP) + MATRIX_KEY(2, 0, KEY_F6) + MATRIX_KEY(2, 1, KEY_F8) + MATRIX_KEY(2, 2, KEY_F9) + MATRIX_KEY(2, 3, KEY_F10) + MATRIX_KEY(3, 0, KEY_F1) + MATRIX_KEY(3, 1, KEY_F2) + MATRIX_KEY(3, 2, KEY_F3) + MATRIX_KEY(3, 3, KEY_POWER) + >; + status = "okay"; +}; + &ssi2 { fsl,mode = "i2s-slave"; status = "okay"; }; -&iomuxc { +&uart1 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; + pinctrl-0 = <&pinctrl_uart1>; + fsl,uart-has-rtscts; + status = "okay"; +}; - imx51-babbage { - pinctrl_hog: hoggrp { - fsl,pins = < - MX51_PAD_GPIO1_0__SD1_CD 0x20d5 - MX51_PAD_GPIO1_1__SD1_WP 0x20d5 - MX51_PAD_GPIO1_5__GPIO1_5 0x100 - MX51_PAD_GPIO1_6__GPIO1_6 0x100 - MX51_PAD_EIM_A27__GPIO2_21 0x5 - MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 - MX51_PAD_CSPI1_SS1__GPIO4_25 0x85 - MX51_PAD_CSPI1_RDY__GPIO4_26 0x80000000 - >; - }; +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + fsl,uart-has-rtscts; + status = "okay"; +}; + +&usbh1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + vbus-supply = <®_usbh1_vbus>; + fsl,usbphy = <&usbh1phy>; + phy_type = "ulpi"; + status = "okay"; +}; +&usbotg { + dr_mode = "otg"; + disable-over-current; + phy_type = "utmi_wide"; + vbus-supply = <®_usbotg_vbus>; + status = "okay"; +}; + +&iomuxc { + imx51-babbage { pinctrl_audmux: audmuxgrp { fsl,pins = < MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000 @@ -320,11 +444,19 @@ >; }; + pinctrl_clkcodec: clkcodecgrp { + fsl,pins = < + MX51_PAD_CSPI1_RDY__GPIO4_26 0x80000000 + >; + }; + pinctrl_ecspi1: ecspi1grp { fsl,pins = < MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 + MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 /* CS0 */ + MX51_PAD_CSPI1_SS1__GPIO4_25 0x85 /* CS1 */ >; }; @@ -336,6 +468,8 @@ MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5 MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5 MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5 + MX51_PAD_GPIO1_0__SD1_CD 0x20d5 + MX51_PAD_GPIO1_1__SD1_WP 0x20d5 >; }; @@ -347,29 +481,38 @@ MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5 MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5 MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5 + MX51_PAD_GPIO1_5__GPIO1_5 0x100 /* WP */ + MX51_PAD_GPIO1_6__GPIO1_6 0x100 /* CD */ >; }; pinctrl_fec: fecgrp { fsl,pins = < - MX51_PAD_EIM_EB2__FEC_MDIO 0x80000000 - MX51_PAD_EIM_EB3__FEC_RDATA1 0x80000000 - MX51_PAD_EIM_CS2__FEC_RDATA2 0x80000000 - MX51_PAD_EIM_CS3__FEC_RDATA3 0x80000000 - MX51_PAD_EIM_CS4__FEC_RX_ER 0x80000000 - MX51_PAD_EIM_CS5__FEC_CRS 0x80000000 - MX51_PAD_NANDF_RB2__FEC_COL 0x80000000 - MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x80000000 - MX51_PAD_NANDF_D9__FEC_RDATA0 0x80000000 - MX51_PAD_NANDF_D8__FEC_TDATA0 0x80000000 - MX51_PAD_NANDF_CS2__FEC_TX_ER 0x80000000 - MX51_PAD_NANDF_CS3__FEC_MDC 0x80000000 - MX51_PAD_NANDF_CS4__FEC_TDATA1 0x80000000 - MX51_PAD_NANDF_CS5__FEC_TDATA2 0x80000000 - MX51_PAD_NANDF_CS6__FEC_TDATA3 0x80000000 - MX51_PAD_NANDF_CS7__FEC_TX_EN 0x80000000 - MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x80000000 - MX51_PAD_EIM_A20__GPIO2_14 0x85 /* Reset */ + MX51_PAD_EIM_EB2__FEC_MDIO 0x000001f5 + MX51_PAD_EIM_EB3__FEC_RDATA1 0x00000085 + MX51_PAD_EIM_CS2__FEC_RDATA2 0x00000085 + MX51_PAD_EIM_CS3__FEC_RDATA3 0x00000085 + MX51_PAD_EIM_CS4__FEC_RX_ER 0x00000180 + MX51_PAD_EIM_CS5__FEC_CRS 0x00000180 + MX51_PAD_NANDF_RB2__FEC_COL 0x00000180 + MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x00000180 + MX51_PAD_NANDF_D9__FEC_RDATA0 0x00002180 + MX51_PAD_NANDF_D8__FEC_TDATA0 0x00002004 + MX51_PAD_NANDF_CS2__FEC_TX_ER 0x00002004 + MX51_PAD_NANDF_CS3__FEC_MDC 0x00002004 + MX51_PAD_NANDF_CS4__FEC_TDATA1 0x00002004 + MX51_PAD_NANDF_CS5__FEC_TDATA2 0x00002004 + MX51_PAD_NANDF_CS6__FEC_TDATA3 0x00002004 + MX51_PAD_NANDF_CS7__FEC_TX_EN 0x00002004 + MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x00002180 + MX51_PAD_NANDF_D11__FEC_RX_DV 0x000020a4 + MX51_PAD_EIM_A20__GPIO2_14 0x00000085 /* Phy Reset */ + >; + }; + + pinctrl_gpio_keys: gpiokeysgrp { + fsl,pins = < + MX51_PAD_EIM_A27__GPIO2_21 0x5 >; }; @@ -379,6 +522,13 @@ >; }; + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX51_PAD_EIM_D19__I2C1_SCL 0x400001ed + MX51_PAD_EIM_D16__I2C1_SDA 0x400001ed + >; + }; + pinctrl_i2c2: i2c2grp { fsl,pins = < MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed @@ -455,6 +605,12 @@ >; }; + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX51_PAD_GPIO1_8__GPIO1_8 0xe5 /* IRQ */ + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX51_PAD_UART1_RXD__UART1_RXD 0x1c5 @@ -479,71 +635,33 @@ MX51_PAD_EIM_D24__UART3_CTS 0x1c5 >; }; - }; -}; -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - fsl,uart-has-rtscts; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; + pinctrl_usbh1: usbh1grp { + fsl,pins = < + MX51_PAD_USBH1_CLK__USBH1_CLK 0x80000000 + MX51_PAD_USBH1_DIR__USBH1_DIR 0x80000000 + MX51_PAD_USBH1_NXT__USBH1_NXT 0x80000000 + MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x80000000 + MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x80000000 + MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x80000000 + MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x80000000 + MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x80000000 + MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x80000000 + MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x80000000 + MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x80000000 + >; + }; -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; + pinctrl_usbh1reg: usbh1reggrp { + fsl,pins = < + MX51_PAD_EIM_D21__GPIO2_5 0x85 + >; + }; - sgtl5000: codec@0a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - clocks = <&clk_26M>; - VDDA-supply = <&vdig_reg>; - VDDIO-supply = <&vvideo_reg>; + pinctrl_usbotgreg: usbotgreggrp { + fsl,pins = < + MX51_PAD_GPIO1_7__GPIO1_7 0x85 + >; + }; }; }; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; - phy-mode = "mii"; - phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>; - phy-reset-duration = <1>; - status = "okay"; -}; - -&kpp { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_kpp>; - linux,keymap = < - MATRIX_KEY(0, 0, KEY_UP) - MATRIX_KEY(0, 1, KEY_DOWN) - MATRIX_KEY(0, 2, KEY_VOLUMEDOWN) - MATRIX_KEY(0, 3, KEY_HOME) - MATRIX_KEY(1, 0, KEY_RIGHT) - MATRIX_KEY(1, 1, KEY_LEFT) - MATRIX_KEY(1, 2, KEY_ENTER) - MATRIX_KEY(1, 3, KEY_VOLUMEUP) - MATRIX_KEY(2, 0, KEY_F6) - MATRIX_KEY(2, 1, KEY_F8) - MATRIX_KEY(2, 2, KEY_F9) - MATRIX_KEY(2, 3, KEY_F10) - MATRIX_KEY(3, 0, KEY_F1) - MATRIX_KEY(3, 1, KEY_F2) - MATRIX_KEY(3, 2, KEY_F3) - MATRIX_KEY(3, 3, KEY_POWER) - >; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx51-digi-connectcore-jsk.dts b/arch/arm/boot/dts/imx51-digi-connectcore-jsk.dts new file mode 100644 index 000000000000..1db517d3d497 --- /dev/null +++ b/arch/arm/boot/dts/imx51-digi-connectcore-jsk.dts @@ -0,0 +1,108 @@ +/* + * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru> + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include "imx51-digi-connectcore-som.dtsi" + +/ { + model = "Digi ConnectCore CC(W)-MX51 JSK"; + compatible = "digi,connectcore-ccxmx51-jsk", + "digi,connectcore-ccxmx51-som", "fsl,imx51"; + + chosen { + linux,stdout-path = &uart1; + }; +}; + +&owire { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_owire>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&usbotg { + dr_mode = "otg"; + status = "okay"; +}; + +&usbh1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + dr_mode = "host"; + phy_type = "ulpi"; + disable-over-current; + status = "okay"; +}; + +&iomuxc { + imx51-digi-connectcore-jsk { + pinctrl_owire: owiregrp { + fsl,pins = < + MX51_PAD_OWIRE_LINE__OWIRE_LINE 0x40000000 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX51_PAD_UART1_RXD__UART1_RXD 0x1c5 + MX51_PAD_UART1_TXD__UART1_TXD 0x1c5 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX51_PAD_UART2_RXD__UART2_RXD 0x1c5 + MX51_PAD_UART2_TXD__UART2_TXD 0x1c5 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX51_PAD_UART3_RXD__UART3_RXD 0x1c5 + MX51_PAD_UART3_TXD__UART3_TXD 0x1c5 + >; + }; + + pinctrl_usbh1: usbh1grp { + fsl,pins = < + MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x1e5 + MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x1e5 + MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x1e5 + MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x1e5 + MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x1e5 + MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x1e5 + MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x1e5 + MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x1e5 + MX51_PAD_USBH1_CLK__USBH1_CLK 0x1e5 + MX51_PAD_USBH1_DIR__USBH1_DIR 0x1e5 + MX51_PAD_USBH1_NXT__USBH1_NXT 0x1e5 + MX51_PAD_USBH1_STP__USBH1_STP 0x1e5 + >; + }; + }; +}; diff --git a/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi b/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi new file mode 100644 index 000000000000..321662f53e33 --- /dev/null +++ b/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi @@ -0,0 +1,377 @@ +/* + * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru> + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include "imx51.dtsi" + +/ { + model = "Digi ConnectCore CC(W)-MX51"; + compatible = "digi,connectcore-ccxmx51-som", "fsl,imx51"; + + memory { + reg = <0x90000000 0x08000000>; + }; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pmic: mc13892@0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mc13892>; + compatible = "fsl,mc13892"; + spi-max-frequency = <16000000>; + spi-cs-high; + reg = <0>; + interrupt-parent = <&gpio1>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; + fsl,mc13xxx-uses-rtc; + + regulators { + sw1_reg: sw1 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1100000>; + regulator-boot-on; + regulator-always-on; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3_reg: sw3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + regulator-always-on; + }; + + swbst_reg: swbst { }; + + viohi_reg: viohi { + regulator-always-on; + }; + + vpll_reg: vpll { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vdig_reg: vdig { + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1250000>; + regulator-always-on; + }; + + vsd_reg: vsd { + regulator-min-microvolt = <3150000>; + regulator-max-microvolt = <3150000>; + regulator-always-on; + }; + + vusb2_reg: vusb2 { + regulator-min-microvolt = <2600000>; + regulator-max-microvolt = <2600000>; + regulator-always-on; + }; + + vvideo_reg: vvideo { + regulator-min-microvolt = <2775000>; + regulator-max-microvolt = <2775000>; + regulator-always-on; + }; + + vaudio_reg: vaudio { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + vcam_reg: vcam { + regulator-min-microvolt = <2750000>; + regulator-max-microvolt = <2750000>; + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <3150000>; + regulator-max-microvolt = <3150000>; + regulator-always-on; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vusb_reg: vusb { + regulator-always-on; + }; + + gpo1_reg: gpo1 { }; + + gpo2_reg: gpo2 { }; + + gpo3_reg: gpo3 { }; + + gpo4_reg: gpo4 { }; + + pwgt2spi_reg: pwgt2spi { + regulator-always-on; + }; + + vcoincell_reg: vcoincell { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + }; + }; +}; + +&esdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc2>; + cap-sdio-irq; + enable-sdio-wakeup; + keep-power-in-suspend; + max-frequency = <50000000>; + no-1-8-v; + non-removable; + vmmc-supply = <&gpo4_reg>; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "mii"; + phy-supply = <&gpo3_reg>; + /* Pins shared with LCD2, keep status disabled */ +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clock-frequency = <400000>; + status = "okay"; + + mma7455l@1d { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mma7455l>; + compatible = "fsl,mma7455l"; + reg = <0x1d>; + interrupt-parent = <&gpio1>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH>, <6 IRQ_TYPE_LEVEL_HIGH>; + }; +}; + +&nfc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nfc>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-on-flash-bbt; + status = "okay"; +}; + +&usbotg { + phy_type = "utmi_wide"; + disable-over-current; + /* Device role is not known, keep status disabled */ +}; + +&weim { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_weim>; + status = "okay"; + + lan9221: lan9221@5,0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lan9221>; + compatible = "smsc,lan9221", "smsc,lan9115"; + reg = <5 0x00000000 0x1000>; + fsl,weim-cs-timing = < + 0x00420081 0x00000000 + 0x32260000 0x00000000 + 0x72080f00 0x00000000 + >; + clocks = <&clks IMX5_CLK_DUMMY>; + interrupt-parent = <&gpio1>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + phy-mode = "mii"; + reg-io-width = <2>; + smsc,irq-push-pull; + vdd33a-supply = <&gpo2_reg>; + vddvario-supply = <&gpo2_reg>; + }; +}; + +&iomuxc { + imx51-digi-connectcore-som { + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 + MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 + MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 + MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 /* CS0 */ + >; + }; + + pinctrl_esdhc2: esdhc2grp { + fsl,pins = < + MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5 + MX51_PAD_SD2_CLK__SD2_CLK 0x20d5 + MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5 + MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5 + MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5 + MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5 + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000 + MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000 + MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000 + MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000 + MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000 + MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000 + MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000 + MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000 + MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000 + MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000 + MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000 + MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000 + MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000 + MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000 + MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000 + MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000 + MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000 + MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX51_PAD_GPIO1_2__I2C2_SCL 0x400001ed + MX51_PAD_GPIO1_3__I2C2_SDA 0x400001ed + >; + }; + + pinctrl_nfc: nfcgrp { + fsl,pins = < + MX51_PAD_NANDF_D0__NANDF_D0 0x80000000 + MX51_PAD_NANDF_D1__NANDF_D1 0x80000000 + MX51_PAD_NANDF_D2__NANDF_D2 0x80000000 + MX51_PAD_NANDF_D3__NANDF_D3 0x80000000 + MX51_PAD_NANDF_D4__NANDF_D4 0x80000000 + MX51_PAD_NANDF_D5__NANDF_D5 0x80000000 + MX51_PAD_NANDF_D6__NANDF_D6 0x80000000 + MX51_PAD_NANDF_D7__NANDF_D7 0x80000000 + MX51_PAD_NANDF_ALE__NANDF_ALE 0x80000000 + MX51_PAD_NANDF_CLE__NANDF_CLE 0x80000000 + MX51_PAD_NANDF_RE_B__NANDF_RE_B 0x80000000 + MX51_PAD_NANDF_WE_B__NANDF_WE_B 0x80000000 + MX51_PAD_NANDF_WP_B__NANDF_WP_B 0x80000000 + MX51_PAD_NANDF_CS0__NANDF_CS0 0x80000000 + MX51_PAD_NANDF_RB0__NANDF_RB0 0x80000000 + >; + }; + + pinctrl_lan9221: lan9221grp { + fsl,pins = < + MX51_PAD_GPIO1_9__GPIO1_9 0xe5 /* IRQ */ + >; + }; + + pinctrl_mc13892: mc13892grp { + fsl,pins = < + MX51_PAD_GPIO1_5__GPIO1_5 0xe5 /* IRQ */ + >; + }; + + pinctrl_mma7455l: mma7455lgrp { + fsl,pins = < + MX51_PAD_GPIO1_7__GPIO1_7 0xe5 /* IRQ1 */ + MX51_PAD_GPIO1_6__GPIO1_6 0xe5 /* IRQ2 */ + >; + }; + + pinctrl_weim: weimgrp { + fsl,pins = < + MX51_PAD_EIM_DA0__EIM_DA0 0x80000000 + MX51_PAD_EIM_DA1__EIM_DA1 0x80000000 + MX51_PAD_EIM_DA2__EIM_DA2 0x80000000 + MX51_PAD_EIM_DA3__EIM_DA3 0x80000000 + MX51_PAD_EIM_DA4__EIM_DA4 0x80000000 + MX51_PAD_EIM_DA5__EIM_DA5 0x80000000 + MX51_PAD_EIM_DA6__EIM_DA6 0x80000000 + MX51_PAD_EIM_DA7__EIM_DA7 0x80000000 + MX51_PAD_EIM_DA8__EIM_DA8 0x80000000 + MX51_PAD_EIM_DA9__EIM_DA9 0x80000000 + MX51_PAD_EIM_DA10__EIM_DA10 0x80000000 + MX51_PAD_EIM_DA11__EIM_DA11 0x80000000 + MX51_PAD_EIM_DA12__EIM_DA12 0x80000000 + MX51_PAD_EIM_DA13__EIM_DA13 0x80000000 + MX51_PAD_EIM_DA14__EIM_DA14 0x80000000 + MX51_PAD_EIM_DA15__EIM_DA15 0x80000000 + MX51_PAD_EIM_A16__EIM_A16 0x80000000 + MX51_PAD_EIM_A17__EIM_A17 0x80000000 + MX51_PAD_EIM_A18__EIM_A18 0x80000000 + MX51_PAD_EIM_A19__EIM_A19 0x80000000 + MX51_PAD_EIM_A20__EIM_A20 0x80000000 + MX51_PAD_EIM_A21__EIM_A21 0x80000000 + MX51_PAD_EIM_A22__EIM_A22 0x80000000 + MX51_PAD_EIM_A23__EIM_A23 0x80000000 + MX51_PAD_EIM_A24__EIM_A24 0x80000000 + MX51_PAD_EIM_A25__EIM_A25 0x80000000 + MX51_PAD_EIM_A26__EIM_A26 0x80000000 + MX51_PAD_EIM_A27__EIM_A27 0x80000000 + MX51_PAD_EIM_D16__EIM_D16 0x80000000 + MX51_PAD_EIM_D17__EIM_D17 0x80000000 + MX51_PAD_EIM_D18__EIM_D18 0x80000000 + MX51_PAD_EIM_D19__EIM_D19 0x80000000 + MX51_PAD_EIM_D20__EIM_D20 0x80000000 + MX51_PAD_EIM_D21__EIM_D21 0x80000000 + MX51_PAD_EIM_D22__EIM_D22 0x80000000 + MX51_PAD_EIM_D23__EIM_D23 0x80000000 + MX51_PAD_EIM_D24__EIM_D24 0x80000000 + MX51_PAD_EIM_D25__EIM_D25 0x80000000 + MX51_PAD_EIM_D26__EIM_D26 0x80000000 + MX51_PAD_EIM_D27__EIM_D27 0x80000000 + MX51_PAD_EIM_D28__EIM_D28 0x80000000 + MX51_PAD_EIM_D29__EIM_D29 0x80000000 + MX51_PAD_EIM_D30__EIM_D30 0x80000000 + MX51_PAD_EIM_D31__EIM_D31 0x80000000 + MX51_PAD_EIM_OE__EIM_OE 0x80000000 + MX51_PAD_EIM_DTACK__EIM_DTACK 0x80000000 + MX51_PAD_EIM_LBA__EIM_LBA 0x80000000 + MX51_PAD_EIM_CS5__EIM_CS5 0x80000000 /* CS5 */ + >; + }; + }; +}; diff --git a/arch/arm/boot/dts/imx51-eukrea-cpuimx51.dtsi b/arch/arm/boot/dts/imx51-eukrea-cpuimx51.dtsi index 9b3acf6e4282..63164266af83 100644 --- a/arch/arm/boot/dts/imx51-eukrea-cpuimx51.dtsi +++ b/arch/arm/boot/dts/imx51-eukrea-cpuimx51.dtsi @@ -42,6 +42,17 @@ compatible = "nxp,pcf8563"; reg = <0x51>; }; + + tsc2007: tsc2007@49 { + compatible = "ti,tsc2007"; + gpios = <&gpio4 0 1>; + interrupt-parent = <&gpio4>; + interrupts = <0x0 0x8>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tsc2007_1>; + reg = <0x49>; + ti,x-plate-ohms = <180>; + }; }; &iomuxc { diff --git a/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts b/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts index 5cec4f322096..75e66c9c6144 100644 --- a/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts +++ b/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts @@ -24,6 +24,14 @@ model = "Eukrea CPUIMX51"; compatible = "eukrea,mbimxsd51","eukrea,cpuimx51", "fsl,imx51"; + clocks { + clk24M: can_clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + }; + gpio_keys { compatible = "gpio-keys"; pinctrl-names = "default"; @@ -50,6 +58,23 @@ }; }; + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_can: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "CAN_RST"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; + startup-delay-us = <20000>; + enable-active-high; + }; + }; + sound { compatible = "eukrea,asoc-tlv320"; eukrea,model = "imx51-eukrea-tlv320aic23"; @@ -57,6 +82,20 @@ fsl,mux-int-port = <2>; fsl,mux-ext-port = <3>; }; + + usbphy { + #address-cells = <1>; + #size-cells = <0>; + compatible = "simple-bus"; + + usbh1phy: usbh1phy@0 { + compatible = "usb-nop-xceiv"; + reg = <0>; + clocks = <&clks IMX5_CLK_USB_PHY_GATE>; + clock-names = "main_clk"; + clock-frequency = <19200000>; + }; + }; }; &audmux { @@ -72,6 +111,26 @@ status = "okay"; }; +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; + status = "okay"; + + can0: can@0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can>; + compatible = "microchip,mcp2515"; + reg = <0>; + clocks = <&clk24M>; + spi-max-frequency = <10000000>; + interrupt-parent = <&gpio1>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + vdd-supply = <®_can>; + }; +}; + &i2c1 { tlv320aic23: codec@1a { compatible = "ti,tlv320aic23"; @@ -90,6 +149,23 @@ >; }; + + pinctrl_can: cangrp { + fsl,pins = < + MX51_PAD_CSI2_PIXCLK__GPIO4_15 0x80000000 /* nReset */ + MX51_PAD_GPIO1_1__GPIO1_1 0x80000000 /* IRQ */ + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 + MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 + MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 + MX51_PAD_CSPI1_SS0__GPIO4_24 0x80000000 /* CS0 */ + >; + }; + pinctrl_esdhc1: esdhc1grp { fsl,pins = < MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 @@ -151,6 +227,29 @@ MX51_PAD_CSI1_D9__GPIO3_13 0x1f5 >; }; + + pinctrl_usbh1: usbh1grp { + fsl,pins = < + MX51_PAD_USBH1_CLK__USBH1_CLK 0x1e5 + MX51_PAD_USBH1_DIR__USBH1_DIR 0x1e5 + MX51_PAD_USBH1_NXT__USBH1_NXT 0x1e5 + MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x1e5 + MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x1e5 + MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x1e5 + MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x1e5 + MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x1e5 + MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x1e5 + MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x1e5 + MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x1e5 + MX51_PAD_USBH1_STP__USBH1_STP 0x1e5 + >; + }; + + pinctrl_usbh1_vbus: usbh1-vbusgrp { + fsl,pins = < + MX51_PAD_EIM_CS3__GPIO2_28 0x1f5 + >; + }; }; }; @@ -173,3 +272,24 @@ fsl,uart-has-rtscts; status = "okay"; }; + +&usbh1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + fsl,usbphy = <&usbh1phy>; + dr_mode = "host"; + phy_type = "ulpi"; + status = "okay"; +}; + +&usbotg { + dr_mode = "otg"; + phy_type = "utmi_wide"; + status = "okay"; +}; + +&usbphy0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1_vbus>; + reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; +}; diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index 150bb4e2f744..bebbf3ba0d5e 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi @@ -19,6 +19,7 @@ / { aliases { + ethernet0 = &fec; gpio0 = &gpio1; gpio1 = &gpio2; gpio2 = &gpio3; @@ -537,6 +538,8 @@ }; nfc: nand@83fdb000 { + #address-cells = <1>; + #size-cells = <1>; compatible = "fsl,imx51-nand"; reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>; interrupts = <8>; diff --git a/arch/arm/boot/dts/imx53-mba53.dts b/arch/arm/boot/dts/imx53-mba53.dts index a3431d784870..3e3f17aa93a1 100644 --- a/arch/arm/boot/dts/imx53-mba53.dts +++ b/arch/arm/boot/dts/imx53-mba53.dts @@ -17,6 +17,10 @@ model = "TQ MBa53 starter kit"; compatible = "tq,mba53", "tq,tqma53", "fsl,imx53"; + chosen { + stdout-path = &uart2; + }; + backlight { compatible = "pwm-backlight"; pwms = <&pwm2 0 50000>; diff --git a/arch/arm/boot/dts/imx53-qsb-common.dtsi b/arch/arm/boot/dts/imx53-qsb-common.dtsi index ede04fa4161f..fd8c60dde7de 100644 --- a/arch/arm/boot/dts/imx53-qsb-common.dtsi +++ b/arch/arm/boot/dts/imx53-qsb-common.dtsi @@ -13,6 +13,10 @@ #include "imx53.dtsi" / { + chosen { + stdout-path = &uart1; + }; + memory { reg = <0x70000000 0x20000000>, <0xb0000000 0x20000000>; @@ -272,6 +276,14 @@ >; }; + pinctrl_vga_sync: vgasync-grp { + fsl,pins = < + /* VGA_HSYNC, VSYNC with max drive strength */ + MX53_PAD_EIM_OE__IPU_DI1_PIN7 0xe6 + MX53_PAD_EIM_RW__IPU_DI1_PIN8 0xe6 + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1e4 @@ -281,6 +293,15 @@ }; }; +&tve { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_vga_sync>; + fsl,tve-mode = "vga"; + fsl,hsync-pin = <4>; + fsl,vsync-pin = <6>; + status = "okay"; +}; + &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index 6a1bf4ff83d5..6456a0084388 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi @@ -18,6 +18,7 @@ / { aliases { + ethernet0 = &fec; gpio0 = &gpio1; gpio1 = &gpio2; gpio2 = &gpio3; @@ -726,8 +727,8 @@ clocks = <&clks IMX5_CLK_VPU_GATE>, <&clks IMX5_CLK_VPU_GATE>; clock-names = "per", "ahb"; + resets = <&src 1>; iram = <&ocram>; - status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/imx6dl-hummingboard.dts b/arch/arm/boot/dts/imx6dl-hummingboard.dts index 5bfae54fb780..5373a5f2782b 100644 --- a/arch/arm/boot/dts/imx6dl-hummingboard.dts +++ b/arch/arm/boot/dts/imx6dl-hummingboard.dts @@ -11,6 +11,10 @@ model = "SolidRun HummingBoard DL/Solo"; compatible = "solidrun,hummingboard", "fsl,imx6dl"; + chosen { + stdout-path = &uart1; + }; + ir_recv: ir-receiver { compatible = "gpio-ir-receiver"; gpios = <&gpio1 2 1>; @@ -67,6 +71,13 @@ status = "okay"; }; +&hdmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard_hdmi>; + ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + &i2c1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hummingboard_i2c1>; @@ -82,6 +93,13 @@ */ }; +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard_i2c2>; + status = "okay"; +}; + &iomuxc { hummingboard { pinctrl_hummingboard_flexcan1: hummingboard-flexcan1 { @@ -97,6 +115,12 @@ >; }; + pinctrl_hummingboard_hdmi: hummingboard-hdmi { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 + >; + }; + pinctrl_hummingboard_i2c1: hummingboard-i2c1 { fsl,pins = < MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 @@ -104,6 +128,13 @@ >; }; + pinctrl_hummingboard_i2c2: hummingboard-i2c2 { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + pinctrl_hummingboard_spdif: hummingboard-spdif { fsl,pins = <MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x13091>; }; diff --git a/arch/arm/boot/dts/imx6dl-phytec-pbab01.dts b/arch/arm/boot/dts/imx6dl-phytec-pbab01.dts new file mode 100644 index 000000000000..08e97801494e --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-phytec-pbab01.dts @@ -0,0 +1,19 @@ +/* + * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include "imx6dl-phytec-pfla02.dtsi" +#include "imx6qdl-phytec-pbab01.dtsi" + +/ { + model = "Phytec phyFLEX-i.MX6 DualLite/Solo Carrier-Board"; + compatible = "phytec,imx6dl-pbab01", "phytec,imx6dl-pfla02", "fsl,imx6dl"; +}; diff --git a/arch/arm/boot/dts/imx6dl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6dl-phytec-pfla02.dtsi new file mode 100644 index 000000000000..964bc2ad3c5d --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-phytec-pfla02.dtsi @@ -0,0 +1,22 @@ +/* + * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include "imx6dl.dtsi" +#include "imx6qdl-phytec-pfla02.dtsi" + +/ { + model = "Phytec phyFLEX-i.MX6 DualLite/Solo"; + compatible = "phytec,imx6dl-pfla02", "fsl,imx6dl"; + + memory { + reg = <0x10000000 0x20000000>; + }; +}; diff --git a/arch/arm/boot/dts/imx6dl-riotboard.dts b/arch/arm/boot/dts/imx6dl-riotboard.dts new file mode 100644 index 000000000000..909fafc0b650 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-riotboard.dts @@ -0,0 +1,539 @@ +/* + * Copyright 2014 Iain Paton <ipaton0@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +/dts-v1/; +#include "imx6dl.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "RIoTboard i.MX6S"; + compatible = "riot,imx6s-riotboard", "fsl,imx6dl"; + + memory { + reg = <0x10000000 0x40000000>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_2p5v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + }; + + reg_3p3v: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_usb_otg_vbus: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 0>; + enable-active-high; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_led>; + + led0: user1 { + label = "user1"; + gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + + led1: user2 { + label = "user2"; + gpios = <&gpio3 28 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; + + sound { + compatible = "fsl,imx-audio-sgtl5000"; + model = "imx6-riotboard-sgtl5000"; + ssi-controller = <&ssi1>; + audio-codec = <&codec>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + mux-int-port = <1>; + mux-ext-port = <3>; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii"; + phy-reset-gpios = <&gpio3 31 0>; + interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, + <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + codec: sgtl5000@0a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + clocks = <&clks 201>; + VDDA-supply = <®_2p5v>; + VDDIO-supply = <®_3p3v>; + }; + + pmic: pf0100@08 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + interrupt-parent = <&gpio5>; + interrupts = <16 8>; + + regulators { + reg_vddcore: sw1ab { /* VDDARM_IN */ + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + }; + + reg_vddsoc: sw1c { /* VDDSOC_IN */ + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + }; + + reg_gen_3v3: sw2 { /* VDDHIGH_IN */ + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_ddr_1v5a: sw3a { /* NVCC_DRAM, NVCC_RGMII */ + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-always-on; + }; + + reg_ddr_1v5b: sw3b { /* NVCC_DRAM, NVCC_RGMII */ + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-always-on; + }; + + reg_ddr_vtt: sw4 { /* MIPI conn */ + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-always-on; + }; + + reg_5v_600mA: swbst { /* not used */ + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + reg_snvs_3v: vsnvs { /* VDD_SNVS_IN */ + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + vref_reg: vrefddr { /* VREF_DDR */ + regulator-boot-on; + regulator-always-on; + }; + + reg_vgen1_1v5: vgen1 { /* not used */ + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + reg_vgen2_1v2_eth: vgen2 { /* pcie ? */ + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + reg_vgen3_2v8: vgen3 { /* not used */ + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + reg_vgen4_1v8: vgen4 { /* NVCC_SD3 */ + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_vgen5_2v5_sgtl: vgen5 { /* Pwr LED & 5V0_delayed enable */ + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_vgen6_3v3: vgen6 { /* #V#_DELAYED enable, MIPI */ + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c4 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + clocks = <&clks 116>; + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&ssi1 { + fsl,mode = "i2s-slave"; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbh1 { + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + dr_mode = "otg"; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + cd-gpios = <&gpio1 4 0>; + wp-gpios = <&gpio1 2 0>; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + cd-gpios = <&gpio7 0 0>; + wp-gpios = <&gpio7 1 0>; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + vmmc-supply = <®_3p3v>; + non-removable; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + + imx6-riotboard { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x8000000 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x8000000 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x8000000 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x8000000 + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* CAM_MCLK */ + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x000b1 /* CS0 */ + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x000b1 /* CS1 */ + MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI 0x100b1 + MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO 0x100b1 + MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x000b1 /* CS0 */ + MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x100b1 + >; + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 + MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 + MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 + MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x000b1 /* CS0 */ + MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x000b1 /* CS1 */ + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x80000000 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x0a0b1 /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */ + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 /* AR8035 pin strapping: IO voltage: pull up */ + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x130b0 /* AR8035 pin strapping: PHYADDR#0: pull down */ + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x130b0 /* AR8035 pin strapping: PHYADDR#1: pull down */ + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 /* AR8035 pin strapping: MODE#1: pull up */ + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 /* AR8035 pin strapping: MODE#3: pull up */ + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x130b0 /* AR8035 pin strapping: MODE#0: pull down */ + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0xc0000000 /* GPIO16 -> AR8035 25MHz */ + MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x130b0 /* RGMII_nRST */ + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x80000000 /* AR8035 interrupt */ + MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX6QDL_PAD_GPIO_7__I2C4_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_8__I2C4_SDA 0x4001b8b1 + >; + }; + + pinctrl_led: ledgrp { + fsl,pins = < + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x80000000 /* user led0 */ + MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x80000000 /* user led1 */ + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* MX6QDL_PAD_EIM_D22__USB_OTG_PWR */ + MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x80000000 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000 /* SD2 CD */ + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* SD2 WP */ + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x80000000 /* SD3 CD */ + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x80000000 /* SD3 WP */ + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 + MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x80000000 /* SD4 RST (eMMC) */ + >; + }; + }; +}; diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi index 5c5f574330f9..0a9c49d69d41 100644 --- a/arch/arm/boot/dts/imx6dl.dtsi +++ b/arch/arm/boot/dts/imx6dl.dtsi @@ -84,9 +84,10 @@ i2c4: i2c@021f8000 { #address-cells = <1>; #size-cells = <0>; - compatible = "fsl,imx1-i2c"; + compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; reg = <0x021f8000 0x4000>; interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks 116>; status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts index e4ae38fd0269..e0302636aff5 100644 --- a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts +++ b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts @@ -18,6 +18,10 @@ model = "Data Modul eDM-QMX6 Board"; compatible = "dmo,imx6q-edmqmx6", "fsl,imx6q"; + chosen { + stdout-path = &uart2; + }; + aliases { gpio7 = &stmpe_gpio1; gpio8 = &stmpe_gpio2; @@ -91,6 +95,20 @@ }; }; +&ecspi5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi5>; + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio1 12 0>; + status = "okay"; + + flash: m25p80@0 { + compatible = "m25p80"; + spi-max-frequency = <40000000>; + reg = <0>; + }; +}; + &fec { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; @@ -105,7 +123,8 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2 &pinctrl_stmpe1 - &pinctrl_stmpe2>; + &pinctrl_stmpe2 + &pinctrl_pfuze>; status = "okay"; pmic: pfuze100@08 { @@ -216,6 +235,8 @@ reg = <0x40>; interrupts = <30 0>; interrupt-parent = <&gpio3>; + vcc-supply = <&sw2_reg>; + vio-supply = <&sw2_reg>; stmpe_gpio1: stmpe_gpio { #gpio-cells = <2>; @@ -228,6 +249,8 @@ reg = <0x44>; interrupts = <2 0>; interrupt-parent = <&gpio5>; + vcc-supply = <&sw2_reg>; + vio-supply = <&sw2_reg>; stmpe_gpio2: stmpe_gpio { #gpio-cells = <2>; @@ -263,6 +286,15 @@ >; }; + pinctrl_ecspi5: ecspi5rp-1 { + fsl,pins = < + MX6QDL_PAD_SD1_DAT0__ECSPI5_MISO 0x80000000 + MX6QDL_PAD_SD1_CMD__ECSPI5_MOSI 0x80000000 + MX6QDL_PAD_SD1_CLK__ECSPI5_SCLK 0x80000000 + MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x80000000 + >; + }; + pinctrl_enet: enetgrp { fsl,pins = < MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 @@ -291,6 +323,12 @@ >; }; + pinctrl_pfuze: pfuze100grp1 { + fsl,pins = < + MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x80000000 + >; + }; + pinctrl_stmpe1: stmpe1grp { fsl,pins = <MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x80000000>; }; diff --git a/arch/arm/boot/dts/imx6q-gk802.dts b/arch/arm/boot/dts/imx6q-gk802.dts index 4a9b4dc9afc0..703539cf36d3 100644 --- a/arch/arm/boot/dts/imx6q-gk802.dts +++ b/arch/arm/boot/dts/imx6q-gk802.dts @@ -14,7 +14,7 @@ compatible = "zealz,imx6q-gk802", "fsl,imx6q"; chosen { - linux,stdout-path = &uart4; + stdout-path = &uart4; }; memory { @@ -48,6 +48,11 @@ }; }; +&hdmi { + ddc-i2c-bus = <&i2c3>; + status = "okay"; +}; + /* Internal I2C */ &i2c2 { pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/imx6q-gw5400-a.dts b/arch/arm/boot/dts/imx6q-gw5400-a.dts index e51bb3f0fd56..3689eaa58826 100644 --- a/arch/arm/boot/dts/imx6q-gw5400-a.dts +++ b/arch/arm/boot/dts/imx6q-gw5400-a.dts @@ -157,6 +157,11 @@ status = "okay"; }; +&hdmi { + ddc-i2c-bus = <&i2c3>; + status = "okay"; +}; + &i2c1 { clock-frequency = <100000>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/imx6q-phytec-pbab01.dts b/arch/arm/boot/dts/imx6q-phytec-pbab01.dts index 5607c331fca8..c139ac0ebe15 100644 --- a/arch/arm/boot/dts/imx6q-phytec-pbab01.dts +++ b/arch/arm/boot/dts/imx6q-phytec-pbab01.dts @@ -11,40 +11,17 @@ /dts-v1/; #include "imx6q-phytec-pfla02.dtsi" +#include "imx6qdl-phytec-pbab01.dtsi" / { model = "Phytec phyFLEX-i.MX6 Quad Carrier-Board"; compatible = "phytec,imx6q-pbab01", "phytec,imx6q-pfla02", "fsl,imx6q"; -}; - -&fec { - status = "okay"; -}; -&gpmi { - status = "okay"; + chosen { + stdout-path = &uart4; + }; }; &sata { - status = "okay"; -}; - -&uart4 { - status = "okay"; -}; - -&usbh1 { - status = "okay"; -}; - -&usbotg { - status = "okay"; -}; - -&usdhc2 { - status = "okay"; -}; - -&usdhc3 { - status = "okay"; + status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi index 324f1550976b..cd20d0a948de 100644 --- a/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi +++ b/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi @@ -10,316 +10,13 @@ */ #include "imx6q.dtsi" +#include "imx6qdl-phytec-pfla02.dtsi" / { - model = "Phytec phyFLEX-i.MX6 Ouad"; + model = "Phytec phyFLEX-i.MX6 Quad"; compatible = "phytec,imx6q-pfla02", "fsl,imx6q"; memory { reg = <0x10000000 0x80000000>; }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_usb_otg_vbus: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio4 15 0>; - }; - - reg_usb_h1_vbus: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 0 0>; - }; - }; -}; - -&ecspi3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi3>; - status = "okay"; - fsl,spi-num-chipselects = <1>; - cs-gpios = <&gpio4 24 0>; - - flash@0 { - compatible = "m25p80"; - spi-max-frequency = <20000000>; - reg = <0>; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - eeprom@50 { - compatible = "atmel,24c32"; - reg = <0x50>; - }; - - pmic@58 { - compatible = "dialog,da9063"; - reg = <0x58>; - interrupt-parent = <&gpio4>; - interrupts = <17 0x8>; /* active-low GPIO4_17 */ - - regulators { - vddcore_reg: bcore1 { - regulator-min-microvolt = <730000>; - regulator-max-microvolt = <1380000>; - regulator-always-on; - }; - - vddsoc_reg: bcore2 { - regulator-min-microvolt = <730000>; - regulator-max-microvolt = <1380000>; - regulator-always-on; - }; - - vdd_ddr3_reg: bpro { - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - }; - - vdd_3v3_reg: bperi { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_buckmem_reg: bmem { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_eth_reg: bio { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - vdd_eth_io_reg: ldo4 { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - vdd_mx6_snvs_reg: ldo5 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - }; - - vdd_3v3_pmic_io_reg: ldo6 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_sd0_reg: ldo9 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vdd_sd1_reg: ldo10 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vdd_mx6_high_reg: ldo11 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - }; - }; - }; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - imx6q-phytec-pfla02 { - pinctrl_hog: hoggrp { - fsl,pins = < - MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000 - MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* SPI NOR chipselect */ - MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x80000000 /* PMIC interrupt */ - >; - }; - - pinctrl_ecspi3: ecspi3grp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 - MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 - MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 - MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 - >; - }; - - pinctrl_gpmi_nand: gpminandgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 - MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbh1: usbh1grp { - fsl,pins = < - MX6QDL_PAD_GPIO_0__USB_H1_PWR 0x80000000 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - >; - }; - - pinctrl_usdhc3_cdwp: usdhc3cdwp { - fsl,pins = < - MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000 - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 - >; - }; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii"; - phy-reset-gpios = <&gpio3 23 0>; - status = "disabled"; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - nand-on-flash-bbt; - status = "disabled"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "disabled"; -}; - -&usbh1 { - vbus-supply = <®_usb_h1_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1>; - status = "disabled"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "disabled"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - cd-gpios = <&gpio1 4 0>; - wp-gpios = <&gpio1 2 0>; - status = "disabled"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3 - &pinctrl_usdhc3_cdwp>; - cd-gpios = <&gpio1 27 0>; - wp-gpios = <&gpio1 29 0>; - status = "disabled"; }; diff --git a/arch/arm/boot/dts/imx6q-udoo.dts b/arch/arm/boot/dts/imx6q-udoo.dts index ed397d149ab6..6c561060bf5c 100644 --- a/arch/arm/boot/dts/imx6q-udoo.dts +++ b/arch/arm/boot/dts/imx6q-udoo.dts @@ -16,6 +16,10 @@ model = "Udoo i.MX6 Quad Board"; compatible = "udoo,imx6q-udoo", "fsl,imx6q"; + chosen { + stdout-path = &uart2; + }; + memory { reg = <0x10000000 0x40000000>; }; @@ -28,6 +32,18 @@ status = "okay"; }; +&hdmi { + ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + &iomuxc { imx6q-udoo { pinctrl_enet: enetgrp { @@ -51,6 +67,13 @@ >; }; + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + pinctrl_uart2: uart2grp { fsl,pins = < MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 diff --git a/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi b/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi index c2a24888a276..25da82a03110 100644 --- a/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi +++ b/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi @@ -55,6 +55,20 @@ }; }; +&hdmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_cubox_i_hdmi>; + ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_cubox_i_i2c2>; + status = "okay"; +}; + &i2c3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_cubox_i_i2c3>; @@ -69,6 +83,19 @@ &iomuxc { cubox_i { + pinctrl_cubox_i_hdmi: cubox-i-hdmi { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 + >; + }; + + pinctrl_cubox_i_i2c2: cubox-i-i2c2 { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + pinctrl_cubox_i_i2c3: cubox-i-i2c3 { fsl,pins = < MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 diff --git a/arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi b/arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi index 25cf035dd36e..2c253d6d20bd 100644 --- a/arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi +++ b/arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi @@ -22,7 +22,7 @@ }; chosen { - linux,stdout-path = &uart1; + stdout-path = &uart1; }; }; diff --git a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi index 98a422153ce7..31665adcbf39 100644 --- a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi @@ -101,6 +101,11 @@ status = "okay"; }; +&hdmi { + ddc-i2c-bus = <&i2c3>; + status = "okay"; +}; + &i2c1 { clock-frequency = <100000>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi index 035d3a85c318..367af3ec9435 100644 --- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi @@ -27,6 +27,13 @@ bootargs = "console=ttymxc1,115200"; }; + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm4 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + }; + leds { compatible = "gpio-leds"; @@ -148,6 +155,11 @@ status = "okay"; }; +&hdmi { + ddc-i2c-bus = <&i2c3>; + status = "okay"; +}; + &i2c1 { clock-frequency = <100000>; pinctrl-names = "default"; @@ -394,6 +406,12 @@ >; }; + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 @@ -436,6 +454,27 @@ &ldb { status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + status = "okay"; + + display-timings { + native-mode = <&timing0>; + timing0: hsd100pxn1 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <21>; + vfront-porch = <7>; + hsync-len = <60>; + vsync-len = <10>; + }; + }; + }; }; &pcie { @@ -443,6 +482,12 @@ status = "okay"; }; +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + &ssi1 { fsl,mode = "i2s-slave"; status = "okay"; diff --git a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi index c8e5ae06deaf..c91b5a6c769b 100644 --- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi @@ -30,6 +30,13 @@ bootargs = "console=ttymxc1,115200"; }; + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm4 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + }; + leds { compatible = "gpio-leds"; @@ -157,6 +164,11 @@ status = "okay"; }; +&hdmi { + ddc-i2c-bus = <&i2c3>; + status = "okay"; +}; + &i2c1 { clock-frequency = <100000>; pinctrl-names = "default"; @@ -434,6 +446,12 @@ >; }; + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 @@ -508,6 +526,12 @@ }; }; +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + &ssi1 { fsl,mode = "i2s-slave"; status = "okay"; diff --git a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi index 2795dfc8c926..698d3063b295 100644 --- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi @@ -30,6 +30,13 @@ bootargs = "console=ttymxc1,115200"; }; + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm4 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + }; + leds { compatible = "gpio-leds"; @@ -147,6 +154,11 @@ status = "okay"; }; +&hdmi { + ddc-i2c-bus = <&i2c3>; + status = "okay"; +}; + &i2c1 { clock-frequency = <100000>; pinctrl-names = "default"; @@ -456,6 +468,12 @@ >; }; + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 @@ -530,6 +548,12 @@ }; }; +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + &ssi1 { fsl,mode = "i2s-slave"; status = "okay"; diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi index 99be301b5232..4c4b17596c8b 100644 --- a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi +++ b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi @@ -14,6 +14,10 @@ #include <dt-bindings/input/input.h> / { + chosen { + stdout-path = &uart2; + }; + memory { reg = <0x10000000 0x40000000>; }; diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi new file mode 100644 index 000000000000..584721264121 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi @@ -0,0 +1,102 @@ +/* + * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/ { + chosen { + linux,stdout-path = &uart4; + }; +}; + +&fec { + status = "okay"; +}; + +&gpmi { + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clock-frequency = <100000>; + status = "okay"; + + tlv320@18 { + compatible = "ti,tlv320aic3x"; + reg = <0x18>; + }; + + stmpe@41 { + compatible = "st,stmpe811"; + reg = <0x41>; + }; + + rtc@51 { + compatible = "nxp,rtc8564"; + reg = <0x51>; + }; + + adc@64 { + compatible = "maxim,max1037"; + reg = <0x64>; + }; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + clock-frequency = <100000>; + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&uart4 { + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&usbotg { + status = "okay"; +}; + +&usdhc2 { + status = "okay"; +}; + +&usdhc3 { + status = "okay"; +}; + +&iomuxc { + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi new file mode 100644 index 000000000000..faa3494a69d4 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi @@ -0,0 +1,356 @@ +/* + * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "Phytec phyFLEX-i.MX6 Ouad"; + compatible = "phytec,imx6q-pfla02", "fsl,imx6q"; + + memory { + reg = <0x10000000 0x80000000>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usb_otg_vbus: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 15 0>; + }; + + reg_usb_h1_vbus: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 0 0>; + }; + }; + + gpio_leds: leds { + compatible = "gpio-leds"; + + green { + label = "phyflex:green"; + gpios = <&gpio1 30 0>; + }; + + red { + label = "phyflex:red"; + gpios = <&gpio2 31 0>; + }; + }; +}; + +&ecspi3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>; + status = "okay"; + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio4 24 0>; + + flash@0 { + compatible = "m25p80"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + }; + + pmic@58 { + compatible = "dialog,da9063"; + reg = <0x58>; + interrupt-parent = <&gpio4>; + interrupts = <17 0x8>; /* active-low GPIO4_17 */ + + regulators { + vddcore_reg: bcore1 { + regulator-min-microvolt = <730000>; + regulator-max-microvolt = <1380000>; + regulator-always-on; + }; + + vddsoc_reg: bcore2 { + regulator-min-microvolt = <730000>; + regulator-max-microvolt = <1380000>; + regulator-always-on; + }; + + vdd_ddr3_reg: bpro { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + }; + + vdd_3v3_reg: bperi { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_buckmem_reg: bmem { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_eth_reg: bio { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + vdd_eth_io_reg: ldo4 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + vdd_mx6_snvs_reg: ldo5 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + vdd_3v3_pmic_io_reg: ldo6 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_sd0_reg: ldo9 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vdd_sd1_reg: ldo10 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vdd_mx6_high_reg: ldo11 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + }; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx6q-phytec-pfla02 { + pinctrl_hog: hoggrp { + fsl,pins = < + MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000 + MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* SPI NOR chipselect */ + MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x80000000 /* PMIC interrupt */ + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* Green LED */ + MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x80000000 /* Red LED */ + >; + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 + MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 + MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 + >; + }; + + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 + MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D30__UART3_RTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D31__UART3_CTS_B 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbh1: usbh1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_0__USB_H1_PWR 0x80000000 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + >; + }; + + pinctrl_usdhc3_cdwp: usdhc3cdwp { + fsl,pins = < + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000 + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 + >; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii"; + phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; + status = "disabled"; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + nand-on-flash-bbt; + status = "disabled"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "disabled"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "disabled"; +}; + +&usbh1 { + vbus-supply = <®_usb_h1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + status = "disabled"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "disabled"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + cd-gpios = <&gpio1 4 0>; + wp-gpios = <&gpio1 2 0>; + status = "disabled"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3 + &pinctrl_usdhc3_cdwp>; + cd-gpios = <&gpio1 27 0>; + wp-gpios = <&gpio1 29 0>; + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi index 3bec128c7971..6df6127bf835 100644 --- a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi @@ -13,6 +13,10 @@ #include <dt-bindings/input/input.h> / { + chosen { + stdout-path = &uart2; + }; + memory { reg = <0x10000000 0x40000000>; }; diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi index 0d816d3be4b6..40ea36534643 100644 --- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi @@ -14,6 +14,10 @@ #include <dt-bindings/input/input.h> / { + chosen { + stdout-path = &uart1; + }; + memory { reg = <0x10000000 0x40000000>; }; @@ -105,6 +109,17 @@ default-brightness-level = <7>; status = "okay"; }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + red { + gpios = <&gpio1 2 0>; + default-state = "on"; + }; + }; }; &audmux { @@ -137,6 +152,11 @@ status = "okay"; }; +&hdmi { + ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + &i2c1 { clock-frequency = <100000>; pinctrl-names = "default"; @@ -373,6 +393,12 @@ >; }; + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 + >; + }; + pinctrl_pwm1: pwm1grp { fsl,pins = < MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 @@ -421,6 +447,29 @@ MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 >; }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 + >; + }; + }; + + gpio_leds { + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 + >; + }; }; }; @@ -449,6 +498,13 @@ }; }; +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio7 12 0>; + status = "okay"; +}; + &pwm1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm1>; @@ -496,3 +552,12 @@ wp-gpios = <&gpio2 1 0>; status = "okay"; }; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + bus-width = <8>; + non-removable; + no-1-8-v; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi index bdfdf89d405f..5c6f10c43f65 100644 --- a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi +++ b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi @@ -62,6 +62,18 @@ status = "okay"; }; +&hdmi { + ddc-i2c-bus = <&i2c1>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; +}; + &i2c2 { clock-frequency = <100000>; pinctrl-names = "default"; @@ -127,6 +139,13 @@ >; }; + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + pinctrl_i2c2: i2c2grp { fsl,pins = < MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index eca0971d4db1..ce0599134a69 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -16,6 +16,7 @@ / { aliases { + ethernet0 = &fec; can0 = &can1; can1 = &can2; gpio0 = &gpio1; @@ -140,15 +141,16 @@ 0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */ 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */ num-lanes = <1>; - interrupts = <0 123 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 2 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 3 &intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 4 &intc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks 189>, <&clks 187>, <&clks 206>, <&clks 144>; - clock-names = "pcie_ref_125m", "sata_ref_100m", "lvds_gate", "pcie_axi"; + clocks = <&clks 144>, <&clks 206>, <&clks 189>; + clock-names = "pcie", "pcie_bus", "pcie_phy"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index d26b099260a3..2d4e5285f3f3 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -14,6 +14,7 @@ / { aliases { + ethernet0 = &fec; gpio0 = &gpio1; gpio1 = &gpio2; gpio2 = &gpio3; diff --git a/arch/arm/boot/dts/k2e-evm.dts b/arch/arm/boot/dts/k2e-evm.dts index 74b3b63e94cf..c568f067604d 100644 --- a/arch/arm/boot/dts/k2e-evm.dts +++ b/arch/arm/boot/dts/k2e-evm.dts @@ -58,3 +58,84 @@ &usb1 { status = "okay"; }; + +&i2c0 { + dtt@50 { + compatible = "at,24c1024"; + reg = <0x50>; + }; +}; + +&aemif { + cs0 { + #address-cells = <2>; + #size-cells = <1>; + clock-ranges; + ranges; + + ti,cs-chipselect = <0>; + /* all timings in nanoseconds */ + ti,cs-min-turnaround-ns = <12>; + ti,cs-read-hold-ns = <6>; + ti,cs-read-strobe-ns = <23>; + ti,cs-read-setup-ns = <9>; + ti,cs-write-hold-ns = <8>; + ti,cs-write-strobe-ns = <23>; + ti,cs-write-setup-ns = <8>; + + nand@0,0 { + compatible = "ti,keystone-nand","ti,davinci-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0 0 0x4000000 + 1 0 0x0000100>; + + ti,davinci-chipselect = <0>; + ti,davinci-mask-ale = <0x2000>; + ti,davinci-mask-cle = <0x4000>; + ti,davinci-mask-chipsel = <0>; + nand-ecc-mode = "hw"; + ti,davinci-ecc-bits = <4>; + nand-on-flash-bbt; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x100000>; + read-only; + }; + + partition@100000 { + label = "params"; + reg = <0x100000 0x80000>; + read-only; + }; + + partition@180000 { + label = "ubifs"; + reg = <0x180000 0x1FE80000>; + }; + }; + }; +}; + +&spi0 { + nor_flash: n25q128a11@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "Micron,n25q128a11"; + spi-max-frequency = <54000000>; + m25p,fast-read; + reg = <0>; + + partition@0 { + label = "u-boot-spl"; + reg = <0x0 0x80000>; + read-only; + }; + + partition@1 { + label = "misc"; + reg = <0x80000 0xf80000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/k2hk-evm.dts b/arch/arm/boot/dts/k2hk-evm.dts index c93d06f9f2a8..1f90cbf27fd7 100644 --- a/arch/arm/boot/dts/k2hk-evm.dts +++ b/arch/arm/boot/dts/k2hk-evm.dts @@ -138,3 +138,32 @@ }; }; }; + +&i2c0 { + dtt@50 { + compatible = "at,24c1024"; + reg = <0x50>; + }; +}; + +&spi0 { + nor_flash: n25q128a11@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "Micron,n25q128a11"; + spi-max-frequency = <54000000>; + m25p,fast-read; + reg = <0>; + + partition@0 { + label = "u-boot-spl"; + reg = <0x0 0x80000>; + read-only; + }; + + partition@1 { + label = "misc"; + reg = <0x80000 0xf80000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/k2l-evm.dts b/arch/arm/boot/dts/k2l-evm.dts index 50a70132ac9e..fec43128a2e0 100644 --- a/arch/arm/boot/dts/k2l-evm.dts +++ b/arch/arm/boot/dts/k2l-evm.dts @@ -35,3 +35,84 @@ &usb { status = "okay"; }; + +&i2c0 { + dtt@50 { + compatible = "at,24c1024"; + reg = <0x50>; + }; +}; + +&aemif { + cs0 { + #address-cells = <2>; + #size-cells = <1>; + clock-ranges; + ranges; + + ti,cs-chipselect = <0>; + /* all timings in nanoseconds */ + ti,cs-min-turnaround-ns = <12>; + ti,cs-read-hold-ns = <6>; + ti,cs-read-strobe-ns = <23>; + ti,cs-read-setup-ns = <9>; + ti,cs-write-hold-ns = <8>; + ti,cs-write-strobe-ns = <23>; + ti,cs-write-setup-ns = <8>; + + nand@0,0 { + compatible = "ti,keystone-nand","ti,davinci-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0 0 0x4000000 + 1 0 0x0000100>; + + ti,davinci-chipselect = <0>; + ti,davinci-mask-ale = <0x2000>; + ti,davinci-mask-cle = <0x4000>; + ti,davinci-mask-chipsel = <0>; + nand-ecc-mode = "hw"; + ti,davinci-ecc-bits = <4>; + nand-on-flash-bbt; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x100000>; + read-only; + }; + + partition@100000 { + label = "params"; + reg = <0x100000 0x80000>; + read-only; + }; + + partition@180000 { + label = "ubifs"; + reg = <0x180000 0x7FE80000>; + }; + }; + }; +}; + +&spi0 { + nor_flash: n25q128a11@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "Micron,n25q128a11"; + spi-max-frequency = <54000000>; + m25p,fast-read; + reg = <0>; + + partition@0 { + label = "u-boot-spl"; + reg = <0x0 0x80000>; + read-only; + }; + + partition@1 { + label = "misc"; + reg = <0x80000 0xf80000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/keystone.dtsi b/arch/arm/boot/dts/keystone.dtsi index 90823eb90c1b..d9f99e7deb83 100644 --- a/arch/arm/boot/dts/keystone.dtsi +++ b/arch/arm/boot/dts/keystone.dtsi @@ -28,8 +28,6 @@ gic: interrupt-controller { compatible = "arm,cortex-a15-gic"; #interrupt-cells = <3>; - #size-cells = <0>; - #address-cells = <1>; interrupt-controller; reg = <0x0 0x02561000 0x0 0x1000>, <0x0 0x02562000 0x0 0x2000>, @@ -66,6 +64,7 @@ compatible = "ti,keystone","simple-bus"; interrupt-parent = <&gic>; ranges = <0x0 0x0 0x0 0xc0000000>; + dma-ranges = <0x80000000 0x8 0x00000000 0x80000000>; rstctrl: reset-controller { compatible = "ti,keystone-reset"; @@ -102,11 +101,6 @@ interrupts = <GIC_SPI 283 IRQ_TYPE_EDGE_RISING>; #address-cells = <1>; #size-cells = <0>; - - dtt@50 { - compatible = "at,24c1024"; - reg = <0x50>; - }; }; i2c1: i2c@2530400 { @@ -115,6 +109,8 @@ clock-frequency = <100000>; clocks = <&clki2c>; interrupts = <GIC_SPI 286 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; }; i2c2: i2c@2530800 { @@ -123,6 +119,8 @@ clock-frequency = <100000>; clocks = <&clki2c>; interrupts = <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; }; spi0: spi@21000400 { @@ -132,6 +130,8 @@ ti,davinci-spi-intr-line = <0>; interrupts = <GIC_SPI 292 IRQ_TYPE_EDGE_RISING>; clocks = <&clkspi>; + #address-cells = <1>; + #size-cells = <0>; }; spi1: spi@21000600 { @@ -141,6 +141,8 @@ ti,davinci-spi-intr-line = <0>; interrupts = <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>; clocks = <&clkspi>; + #address-cells = <1>; + #size-cells = <0>; }; spi2: spi@21000800 { @@ -150,6 +152,8 @@ ti,davinci-spi-intr-line = <0>; interrupts = <GIC_SPI 300 IRQ_TYPE_EDGE_RISING>; clocks = <&clkspi>; + #address-cells = <1>; + #size-cells = <0>; }; usb_phy: usb_phy@2620738 { @@ -169,6 +173,8 @@ clock-names = "usb"; interrupts = <GIC_SPI 393 IRQ_TYPE_EDGE_RISING>; ranges; + dma-coherent; + dma-ranges; status = "disabled"; dwc3@2690000 { diff --git a/arch/arm/boot/dts/kirkwood-6192.dtsi b/arch/arm/boot/dts/kirkwood-6192.dtsi index 3916937d6818..dd81508b919b 100644 --- a/arch/arm/boot/dts/kirkwood-6192.dtsi +++ b/arch/arm/boot/dts/kirkwood-6192.dtsi @@ -1,6 +1,6 @@ / { mbus { - pcie-controller { + pciec: pcie-controller { compatible = "marvell,kirkwood-pcie"; status = "disabled"; device_type = "pci"; @@ -15,7 +15,7 @@ 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>; - pcie@1,0 { + pcie0: pcie@1,0 { device_type = "pci"; assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; reg = <0x0800 0 0 0 0>; @@ -35,16 +35,9 @@ }; ocp@f1000000 { - pinctrl: pinctrl@10000 { + pinctrl: pin-controller@10000 { compatible = "marvell,88f6192-pinctrl"; - reg = <0x10000 0x20>; - pmx_nand: pmx-nand { - marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3", - "mpp4", "mpp5", "mpp18", - "mpp19"; - marvell,function = "nand"; - }; pmx_sata0: pmx-sata0 { marvell,pins = "mpp5", "mpp21", "mpp23"; marvell,function = "sata0"; @@ -53,22 +46,6 @@ marvell,pins = "mpp4", "mpp20", "mpp22"; marvell,function = "sata1"; }; - pmx_spi: pmx-spi { - marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3"; - marvell,function = "spi"; - }; - pmx_twsi0: pmx-twsi0 { - marvell,pins = "mpp8", "mpp9"; - marvell,function = "twsi0"; - }; - pmx_uart0: pmx-uart0 { - marvell,pins = "mpp10", "mpp11"; - marvell,function = "uart0"; - }; - pmx_uart1: pmx-uart1 { - marvell,pins = "mpp13", "mpp14"; - marvell,function = "uart1"; - }; pmx_sdio: pmx-sdio { marvell,pins = "mpp12", "mpp13", "mpp14", "mpp15", "mpp16", "mpp17"; @@ -76,14 +53,14 @@ }; }; - rtc@10300 { + rtc: rtc@10300 { compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc"; reg = <0x10300 0x20>; interrupts = <53>; clocks = <&gate_clk 7>; }; - sata@80000 { + sata: sata@80000 { compatible = "marvell,orion-sata"; reg = <0x80000 0x5000>; interrupts = <21>; @@ -92,7 +69,7 @@ status = "disabled"; }; - mvsdio@90000 { + sdio: mvsdio@90000 { compatible = "marvell,orion-sdio"; reg = <0x90000 0x200>; interrupts = <28>; diff --git a/arch/arm/boot/dts/kirkwood-6281.dtsi b/arch/arm/boot/dts/kirkwood-6281.dtsi index 416d96e1302f..7dc7d6782e83 100644 --- a/arch/arm/boot/dts/kirkwood-6281.dtsi +++ b/arch/arm/boot/dts/kirkwood-6281.dtsi @@ -1,6 +1,6 @@ / { mbus { - pcie-controller { + pciec: pcie-controller { compatible = "marvell,kirkwood-pcie"; status = "disabled"; device_type = "pci"; @@ -15,7 +15,7 @@ 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>; - pcie@1,0 { + pcie0: pcie@1,0 { device_type = "pci"; assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; reg = <0x0800 0 0 0 0>; @@ -35,16 +35,9 @@ }; ocp@f1000000 { - pinctrl: pinctrl@10000 { + pinctrl: pin-controller@10000 { compatible = "marvell,88f6281-pinctrl"; - reg = <0x10000 0x20>; - pmx_nand: pmx-nand { - marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3", - "mpp4", "mpp5", "mpp18", - "mpp19"; - marvell,function = "nand"; - }; pmx_sata0: pmx-sata0 { marvell,pins = "mpp5", "mpp21", "mpp23"; marvell,function = "sata0"; @@ -53,22 +46,6 @@ marvell,pins = "mpp4", "mpp20", "mpp22"; marvell,function = "sata1"; }; - pmx_spi: pmx-spi { - marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3"; - marvell,function = "spi"; - }; - pmx_twsi0: pmx-twsi0 { - marvell,pins = "mpp8", "mpp9"; - marvell,function = "twsi0"; - }; - pmx_uart0: pmx-uart0 { - marvell,pins = "mpp10", "mpp11"; - marvell,function = "uart0"; - }; - pmx_uart1: pmx-uart1 { - marvell,pins = "mpp13", "mpp14"; - marvell,function = "uart1"; - }; pmx_sdio: pmx-sdio { marvell,pins = "mpp12", "mpp13", "mpp14", "mpp15", "mpp16", "mpp17"; @@ -76,14 +53,14 @@ }; }; - rtc@10300 { + rtc: rtc@10300 { compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc"; reg = <0x10300 0x20>; interrupts = <53>; clocks = <&gate_clk 7>; }; - sata@80000 { + sata: sata@80000 { compatible = "marvell,orion-sata"; reg = <0x80000 0x5000>; interrupts = <21>; @@ -94,7 +71,7 @@ status = "disabled"; }; - mvsdio@90000 { + sdio: mvsdio@90000 { compatible = "marvell,orion-sdio"; reg = <0x90000 0x200>; interrupts = <28>; diff --git a/arch/arm/boot/dts/kirkwood-6282.dtsi b/arch/arm/boot/dts/kirkwood-6282.dtsi index 2902e0d7971d..4680eec990f0 100644 --- a/arch/arm/boot/dts/kirkwood-6282.dtsi +++ b/arch/arm/boot/dts/kirkwood-6282.dtsi @@ -1,6 +1,6 @@ / { mbus { - pcie-controller { + pciec: pcie-controller { compatible = "marvell,kirkwood-pcie"; status = "disabled"; device_type = "pci"; @@ -19,7 +19,7 @@ 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1.0 MEM */ 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1.0 IO */>; - pcie@1,0 { + pcie0: pcie@1,0 { device_type = "pci"; assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; reg = <0x0800 0 0 0 0>; @@ -36,7 +36,7 @@ status = "disabled"; }; - pcie@2,0 { + pcie1: pcie@2,0 { device_type = "pci"; assigned-addresses = <0x82001000 0 0x00044000 0 0x2000>; reg = <0x1000 0 0 0 0>; @@ -56,15 +56,8 @@ }; ocp@f1000000 { - pinctrl: pinctrl@10000 { + pinctrl: pin-controller@10000 { compatible = "marvell,88f6282-pinctrl"; - reg = <0x10000 0x20>; - - pmx_nand: pmx-nand { - marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3", - "mpp4", "mpp5", "mpp18", "mpp19"; - marvell,function = "nand"; - }; pmx_sata0: pmx-sata0 { marvell,pins = "mpp5", "mpp21", "mpp23"; @@ -74,29 +67,16 @@ marvell,pins = "mpp4", "mpp20", "mpp22"; marvell,function = "sata1"; }; - pmx_spi: pmx-spi { - marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3"; - marvell,function = "spi"; - }; - pmx_twsi0: pmx-twsi0 { - marvell,pins = "mpp8", "mpp9"; - marvell,function = "twsi0"; - }; + /* + * Default I2C1 pinctrl setting on mpp36/mpp37, + * overwrite marvell,pins on board level if required. + */ pmx_twsi1: pmx-twsi1 { marvell,pins = "mpp36", "mpp37"; marvell,function = "twsi1"; }; - pmx_uart0: pmx-uart0 { - marvell,pins = "mpp10", "mpp11"; - marvell,function = "uart0"; - }; - - pmx_uart1: pmx-uart1 { - marvell,pins = "mpp13", "mpp14"; - marvell,function = "uart1"; - }; pmx_sdio: pmx-sdio { marvell,pins = "mpp12", "mpp13", "mpp14", "mpp15", "mpp16", "mpp17"; @@ -104,20 +84,20 @@ }; }; - thermal@10078 { + thermal: thermal@10078 { compatible = "marvell,kirkwood-thermal"; reg = <0x10078 0x4>; status = "okay"; }; - rtc@10300 { + rtc: rtc@10300 { compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc"; reg = <0x10300 0x20>; interrupts = <53>; clocks = <&gate_clk 7>; }; - i2c@11100 { + i2c1: i2c@11100 { compatible = "marvell,mv64xxx-i2c"; reg = <0x11100 0x20>; #address-cells = <1>; @@ -125,10 +105,12 @@ interrupts = <32>; clock-frequency = <100000>; clocks = <&gate_clk 7>; + pinctrl-0 = <&pmx_twsi1>; + pinctrl-names = "default"; status = "disabled"; }; - sata@80000 { + sata: sata@80000 { compatible = "marvell,orion-sata"; reg = <0x80000 0x5000>; interrupts = <21>; @@ -139,7 +121,7 @@ status = "disabled"; }; - mvsdio@90000 { + sdio: mvsdio@90000 { compatible = "marvell,orion-sdio"; reg = <0x90000 0x200>; interrupts = <28>; diff --git a/arch/arm/boot/dts/kirkwood-98dx4122.dtsi b/arch/arm/boot/dts/kirkwood-98dx4122.dtsi index 3271e4c8ea07..9e1f741d74ff 100644 --- a/arch/arm/boot/dts/kirkwood-98dx4122.dtsi +++ b/arch/arm/boot/dts/kirkwood-98dx4122.dtsi @@ -1,31 +1,51 @@ / { + mbus { + pciec: pcie-controller { + compatible = "marvell,kirkwood-pcie"; + status = "disabled"; + device_type = "pci"; + + #address-cells = <3>; + #size-cells = <2>; + + bus-range = <0x00 0xff>; + + ranges = + <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 + 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ + 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>; + + pcie0: pcie@1,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 + 0x81000000 0 0 0x81000000 0x1 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &intc 9>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <0>; + clocks = <&gate_clk 2>; + status = "disabled"; + }; + }; + }; + ocp@f1000000 { - pinctrl: pinctrl@10000 { + pinctrl: pin-controller@10000 { compatible = "marvell,98dx4122-pinctrl"; - reg = <0x10000 0x20>; - pmx_nand: pmx-nand { - marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3", - "mpp4", "mpp5", "mpp18", - "mpp19"; - marvell,function = "nand"; - }; - pmx_spi: pmx-spi { - marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3"; - marvell,function = "spi"; - }; - pmx_twsi0: pmx-twsi0 { - marvell,pins = "mpp8", "mpp9"; - marvell,function = "twsi0"; - }; - pmx_uart0: pmx-uart0 { - marvell,pins = "mpp10", "mpp11"; - marvell,function = "uart0"; - }; - pmx_uart1: pmx-uart1 { - marvell,pins = "mpp13", "mpp14"; - marvell,function = "uart1"; - }; }; }; }; + +&sata_phy0 { + status = "disabled"; +}; + +&sata_phy1 { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/kirkwood-b3.dts b/arch/arm/boot/dts/kirkwood-b3.dts index 6becedebaa4e..c9247f8672ae 100644 --- a/arch/arm/boot/dts/kirkwood-b3.dts +++ b/arch/arm/boot/dts/kirkwood-b3.dts @@ -30,6 +30,7 @@ chosen { bootargs = "console=ttyS0,115200n8 earlyprintk"; + stdout-path = &uart0; }; mbus { @@ -44,7 +45,7 @@ }; ocp@f1000000 { - pinctrl: pinctrl@10000 { + pinctrl: pin-controller@10000 { pmx_button_power: pmx-button-power { marvell,pins = "mpp39"; marvell,function = "gpio"; @@ -69,8 +70,6 @@ spi@10600 { status = "okay"; - pinctrl-0 = <&pmx_spi>; - pinctrl-names = "default"; m25p16@0 { #address-cells = <1>; @@ -113,8 +112,6 @@ * UART0_TX = Testpoint 66 * See the Excito Wiki for more details. */ - pinctrl-0 = <&pmx_uart0>; - pinctrl-names = "default"; status = "okay"; }; diff --git a/arch/arm/boot/dts/kirkwood-cloudbox.dts b/arch/arm/boot/dts/kirkwood-cloudbox.dts index 3b62aeeaa3a2..ab6ab4933e6b 100644 --- a/arch/arm/boot/dts/kirkwood-cloudbox.dts +++ b/arch/arm/boot/dts/kirkwood-cloudbox.dts @@ -14,10 +14,11 @@ chosen { bootargs = "console=ttyS0,115200n8"; + stdout-path = &uart0; }; ocp@f1000000 { - pinctrl: pinctrl@10000 { + pinctrl: pin-controller@10000 { pmx_cloudbox_sata0: pmx-cloudbox-sata0 { marvell,pins = "mpp15"; marvell,function = "sata0"; @@ -25,9 +26,6 @@ }; serial@12000 { - pinctrl-0 = <&pmx_uart0>; - pinctrl-names = "default"; - clock-frequency = <166666667>; status = "okay"; }; @@ -39,8 +37,6 @@ }; spi@10600 { - pinctrl-0 = <&pmx_spi>; - pinctrl-names = "default"; status = "okay"; flash@0 { diff --git a/arch/arm/boot/dts/kirkwood-db.dtsi b/arch/arm/boot/dts/kirkwood-db.dtsi index 02d1225ef99f..812df691ae3d 100644 --- a/arch/arm/boot/dts/kirkwood-db.dtsi +++ b/arch/arm/boot/dts/kirkwood-db.dtsi @@ -22,10 +22,11 @@ chosen { bootargs = "console=ttyS0,115200n8 earlyprintk"; + stdout-path = &uart0; }; ocp@f1000000 { - pinctrl@10000 { + pin-controller@10000 { pmx_sdio_gpios: pmx-sdio-gpios { marvell,pins = "mpp37", "mpp38"; marvell,function = "gpio"; @@ -33,10 +34,7 @@ }; serial@12000 { - pinctrl-0 = <&pmx_uart0>; - pinctrl-names = "default"; - clock-frequency = <200000000>; - status = "ok"; + status = "okay"; }; sata@80000 { @@ -59,8 +57,6 @@ }; &nand { - pinctrl-0 = <&pmx_nand>; - pinctrl-names = "default"; chip-delay = <25>; status = "okay"; diff --git a/arch/arm/boot/dts/kirkwood-dns320.dts b/arch/arm/boot/dts/kirkwood-dns320.dts index bf7fe8ab88f4..d85ef0a91b50 100644 --- a/arch/arm/boot/dts/kirkwood-dns320.dts +++ b/arch/arm/boot/dts/kirkwood-dns320.dts @@ -13,6 +13,7 @@ chosen { bootargs = "console=ttyS0,115200n8 earlyprintk"; + stdout-path = &uart0; }; gpio-leds { @@ -51,8 +52,6 @@ }; serial@12100 { - pinctrl-0 = <&pmx_uart1>; - pinctrl-names = "default"; status = "okay"; }; }; diff --git a/arch/arm/boot/dts/kirkwood-dns325.dts b/arch/arm/boot/dts/kirkwood-dns325.dts index cb9978c652f2..5e586ed04c58 100644 --- a/arch/arm/boot/dts/kirkwood-dns325.dts +++ b/arch/arm/boot/dts/kirkwood-dns325.dts @@ -13,6 +13,7 @@ chosen { bootargs = "console=ttyS0,115200n8 earlyprintk"; + stdout-path = &uart0; }; gpio-leds { diff --git a/arch/arm/boot/dts/kirkwood-dnskw.dtsi b/arch/arm/boot/dts/kirkwood-dnskw.dtsi index d5aa9564a287..113dcf056dcf 100644 --- a/arch/arm/boot/dts/kirkwood-dnskw.dtsi +++ b/arch/arm/boot/dts/kirkwood-dnskw.dtsi @@ -50,7 +50,7 @@ }; ocp@f1000000 { - pinctrl: pinctrl@10000 { + pinctrl: pin-controller@10000 { pinctrl-0 = <&pmx_power_back_on &pmx_present_sata0 &pmx_present_sata1 &pmx_fan_tacho @@ -183,8 +183,6 @@ }; &nand { - pinctrl-0 = <&pmx_nand>; - pinctrl-names = "default"; status = "okay"; chip-delay = <35>; diff --git a/arch/arm/boot/dts/kirkwood-dockstar.dts b/arch/arm/boot/dts/kirkwood-dockstar.dts index f31312ebd0d6..849736349511 100644 --- a/arch/arm/boot/dts/kirkwood-dockstar.dts +++ b/arch/arm/boot/dts/kirkwood-dockstar.dts @@ -14,10 +14,11 @@ chosen { bootargs = "console=ttyS0,115200n8 earlyprintk root=/dev/sda1 rootdelay=10"; + stdout-path = &uart0; }; ocp@f1000000 { - pinctrl: pinctrl@10000 { + pinctrl: pin-controller@10000 { pmx_usb_power_enable: pmx-usb-power-enable { marvell,pins = "mpp29"; marvell,function = "gpio"; diff --git a/arch/arm/boot/dts/kirkwood-dreamplug.dts b/arch/arm/boot/dts/kirkwood-dreamplug.dts index 28b3ee369778..6467c7924195 100644 --- a/arch/arm/boot/dts/kirkwood-dreamplug.dts +++ b/arch/arm/boot/dts/kirkwood-dreamplug.dts @@ -14,10 +14,11 @@ chosen { bootargs = "console=ttyS0,115200n8 earlyprintk"; + stdout-path = &uart0; }; ocp@f1000000 { - pinctrl: pinctrl@10000 { + pinctrl: pin-controller@10000 { pmx_led_bluetooth: pmx-led-bluetooth { marvell,pins = "mpp47"; marvell,function = "gpio"; @@ -37,8 +38,6 @@ spi@10600 { status = "okay"; - pinctrl-0 = <&pmx_spi>; - pinctrl-names = "default"; m25p40@0 { #address-cells = <1>; diff --git a/arch/arm/boot/dts/kirkwood-ds109.dts b/arch/arm/boot/dts/kirkwood-ds109.dts index 772092c94ca3..d4bcc1c7f6b3 100644 --- a/arch/arm/boot/dts/kirkwood-ds109.dts +++ b/arch/arm/boot/dts/kirkwood-ds109.dts @@ -25,6 +25,7 @@ chosen { bootargs = "console=ttyS0,115200n8"; + stdout-path = &uart0; }; gpio-fan-150-32-35 { diff --git a/arch/arm/boot/dts/kirkwood-ds110jv10.dts b/arch/arm/boot/dts/kirkwood-ds110jv10.dts index aabafbe0da4c..95bf83b91b4a 100644 --- a/arch/arm/boot/dts/kirkwood-ds110jv10.dts +++ b/arch/arm/boot/dts/kirkwood-ds110jv10.dts @@ -25,6 +25,7 @@ chosen { bootargs = "console=ttyS0,115200n8"; + stdout-path = &uart0; }; gpio-fan-150-32-35 { diff --git a/arch/arm/boot/dts/kirkwood-ds111.dts b/arch/arm/boot/dts/kirkwood-ds111.dts index 16ec7fbab573..61f47fbe44d0 100644 --- a/arch/arm/boot/dts/kirkwood-ds111.dts +++ b/arch/arm/boot/dts/kirkwood-ds111.dts @@ -24,6 +24,7 @@ chosen { bootargs = "console=ttyS0,115200n8"; + stdout-path = &uart0; }; gpio-fan-100-15-35-1 { diff --git a/arch/arm/boot/dts/kirkwood-ds112.dts b/arch/arm/boot/dts/kirkwood-ds112.dts index cff1b2388765..bf4143c6cb8f 100644 --- a/arch/arm/boot/dts/kirkwood-ds112.dts +++ b/arch/arm/boot/dts/kirkwood-ds112.dts @@ -24,6 +24,7 @@ chosen { bootargs = "console=ttyS0,115200n8"; + stdout-path = &uart0; }; gpio-fan-100-15-35-1 { diff --git a/arch/arm/boot/dts/kirkwood-ds209.dts b/arch/arm/boot/dts/kirkwood-ds209.dts index 330411993d38..6d25093a9ac4 100644 --- a/arch/arm/boot/dts/kirkwood-ds209.dts +++ b/arch/arm/boot/dts/kirkwood-ds209.dts @@ -24,6 +24,7 @@ chosen { bootargs = "console=ttyS0,115200n8"; + stdout-path = &uart0; }; gpio-fan-150-32-35 { diff --git a/arch/arm/boot/dts/kirkwood-ds210.dts b/arch/arm/boot/dts/kirkwood-ds210.dts index 6052eaa37d4f..2f1933efcac1 100644 --- a/arch/arm/boot/dts/kirkwood-ds210.dts +++ b/arch/arm/boot/dts/kirkwood-ds210.dts @@ -26,6 +26,7 @@ chosen { bootargs = "console=ttyS0,115200n8"; + stdout-path = &uart0; }; gpio-fan-150-32-35 { diff --git a/arch/arm/boot/dts/kirkwood-ds212.dts b/arch/arm/boot/dts/kirkwood-ds212.dts index 7f76cd30e84e..99afd462f956 100644 --- a/arch/arm/boot/dts/kirkwood-ds212.dts +++ b/arch/arm/boot/dts/kirkwood-ds212.dts @@ -27,6 +27,7 @@ chosen { bootargs = "console=ttyS0,115200n8"; + stdout-path = &uart0; }; gpio-fan-100-15-35-1 { diff --git a/arch/arm/boot/dts/kirkwood-ds212j.dts b/arch/arm/boot/dts/kirkwood-ds212j.dts index 1f83a00f1f74..f5c4213fc67c 100644 --- a/arch/arm/boot/dts/kirkwood-ds212j.dts +++ b/arch/arm/boot/dts/kirkwood-ds212j.dts @@ -25,6 +25,7 @@ chosen { bootargs = "console=ttyS0,115200n8"; + stdout-path = &uart0; }; gpio-fan-100-32-35 { diff --git a/arch/arm/boot/dts/kirkwood-ds409.dts b/arch/arm/boot/dts/kirkwood-ds409.dts index 0a573add44a2..e80a962ebba0 100644 --- a/arch/arm/boot/dts/kirkwood-ds409.dts +++ b/arch/arm/boot/dts/kirkwood-ds409.dts @@ -24,6 +24,7 @@ chosen { bootargs = "console=ttyS0,115200n8"; + stdout-path = &uart0; }; gpio-fan-150-15-18 { diff --git a/arch/arm/boot/dts/kirkwood-ds409slim.dts b/arch/arm/boot/dts/kirkwood-ds409slim.dts index 1848a6245fd3..cae5af4b88b5 100644 --- a/arch/arm/boot/dts/kirkwood-ds409slim.dts +++ b/arch/arm/boot/dts/kirkwood-ds409slim.dts @@ -24,6 +24,7 @@ chosen { bootargs = "console=ttyS0,115200n8"; + stdout-path = &uart0; }; gpio-fan-150-32-35 { diff --git a/arch/arm/boot/dts/kirkwood-ds411.dts b/arch/arm/boot/dts/kirkwood-ds411.dts index a1737b4311c6..623cd4a37d71 100644 --- a/arch/arm/boot/dts/kirkwood-ds411.dts +++ b/arch/arm/boot/dts/kirkwood-ds411.dts @@ -24,6 +24,7 @@ chosen { bootargs = "console=ttyS0,115200n8"; + stdout-path = &uart0; }; gpio-fan-100-15-35-1 { diff --git a/arch/arm/boot/dts/kirkwood-ds411j.dts b/arch/arm/boot/dts/kirkwood-ds411j.dts index 0cde914eceae..3348e330f074 100644 --- a/arch/arm/boot/dts/kirkwood-ds411j.dts +++ b/arch/arm/boot/dts/kirkwood-ds411j.dts @@ -24,6 +24,7 @@ chosen { bootargs = "console=ttyS0,115200n8"; + stdout-path = &uart0; }; gpio-fan-150-15-18 { diff --git a/arch/arm/boot/dts/kirkwood-ds411slim.dts b/arch/arm/boot/dts/kirkwood-ds411slim.dts index aef0cadc2c78..a0a1fad8b4de 100644 --- a/arch/arm/boot/dts/kirkwood-ds411slim.dts +++ b/arch/arm/boot/dts/kirkwood-ds411slim.dts @@ -24,6 +24,7 @@ chosen { bootargs = "console=ttyS0,115200n8"; + stdout-path = &uart0; }; gpio-fan-100-15-35-1 { diff --git a/arch/arm/boot/dts/kirkwood-goflexnet.dts b/arch/arm/boot/dts/kirkwood-goflexnet.dts index eb9329420107..aa60a0b049a7 100644 --- a/arch/arm/boot/dts/kirkwood-goflexnet.dts +++ b/arch/arm/boot/dts/kirkwood-goflexnet.dts @@ -14,10 +14,11 @@ chosen { bootargs = "console=ttyS0,115200n8 earlyprintk root=/dev/sda1 rootdelay=10"; + stdout-path = &uart0; }; ocp@f1000000 { - pinctrl: pinctrl@10000 { + pinctrl: pin-controller@10000 { pmx_usb_power_enable: pmx-usb-power-enable { marvell,pins = "mpp29"; marvell,function = "gpio"; diff --git a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts index 2d51fce74a5a..c5a1fc75c7a3 100644 --- a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts +++ b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts @@ -14,10 +14,11 @@ chosen { bootargs = "console=ttyS0,115200n8 earlyprintk"; + stdout-path = &uart0; }; ocp@f1000000 { - pinctrl: pinctrl@10000 { + pinctrl: pin-controller@10000 { pmx_led_health_r: pmx-led-health-r { marvell,pins = "mpp46"; marvell,function = "gpio"; @@ -36,7 +37,6 @@ }; }; serial@12000 { - clock-frequency = <200000000>; status = "ok"; }; @@ -101,13 +101,19 @@ status = "okay"; ethphy0: ethernet-phy@0 { - compatible = "marvell,88e1121"; + /* Marvell 88E1121R */ + compatible = "ethernet-phy-id0141.0cb0", + "ethernet-phy-ieee802.3-c22"; reg = <0>; + phy-connection-type = "rgmii-id"; }; ethphy1: ethernet-phy@1 { - compatible = "marvell,88e1121"; + /* Marvell 88E1121R */ + compatible = "ethernet-phy-id0141.0cb0", + "ethernet-phy-ieee802.3-c22"; reg = <1>; + phy-connection-type = "rgmii-id"; }; }; diff --git a/arch/arm/boot/dts/kirkwood-ib62x0.dts b/arch/arm/boot/dts/kirkwood-ib62x0.dts index a1add3f215e3..bfa5edde179c 100644 --- a/arch/arm/boot/dts/kirkwood-ib62x0.dts +++ b/arch/arm/boot/dts/kirkwood-ib62x0.dts @@ -14,10 +14,11 @@ chosen { bootargs = "console=ttyS0,115200n8 earlyprintk"; + stdout-path = &uart0; }; ocp@f1000000 { - pinctrl: pinctrl@10000 { + pinctrl: pin-controller@10000 { pmx_led_os_red: pmx-led-os-red { marvell,pins = "mpp22"; marvell,function = "gpio"; @@ -104,8 +105,6 @@ &nand { status = "okay"; - pinctrl-0 = <&pmx_nand>; - pinctrl-names = "default"; partition@0 { label = "u-boot"; diff --git a/arch/arm/boot/dts/kirkwood-iconnect.dts b/arch/arm/boot/dts/kirkwood-iconnect.dts index 8d8c80e3656d..38e31d15a62d 100644 --- a/arch/arm/boot/dts/kirkwood-iconnect.dts +++ b/arch/arm/boot/dts/kirkwood-iconnect.dts @@ -14,6 +14,7 @@ chosen { bootargs = "console=ttyS0,115200n8 earlyprintk"; + stdout-path = &uart0; linux,initrd-start = <0x4500040>; linux,initrd-end = <0x4800000>; }; @@ -29,7 +30,7 @@ }; ocp@f1000000 { - pinctrl: pinctrl@10000 { + pinctrl: pin-controller@10000 { pmx_button_reset: pmx-button-reset { marvell,pins = "mpp12"; marvell,function = "gpio"; diff --git a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts index 59e7a5adeedb..05291f3990d0 100644 --- a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts +++ b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts @@ -14,10 +14,11 @@ chosen { bootargs = "console=ttyS0,115200n8 earlyprintk"; + stdout-path = &uart0; }; ocp@f1000000 { - pinctrl: pinctrl@10000 { + pinctrl: pin-controller@10000 { pinctrl-0 = < &pmx_led_sata_brt_ctrl_1 &pmx_led_sata_brt_ctrl_2 &pmx_led_backup_brt_ctrl_1 diff --git a/arch/arm/boot/dts/kirkwood-km_common.dtsi b/arch/arm/boot/dts/kirkwood-km_common.dtsi new file mode 100644 index 000000000000..8367c772c764 --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-km_common.dtsi @@ -0,0 +1,48 @@ +/ { + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk"; + stdout-path = &uart0; + }; + + mbus { + pcie-controller { + status = "okay"; + + pcie@1,0 { + status = "okay"; + }; + }; + }; + + ocp@f1000000 { + pinctrl: pin-controller@10000 { + pinctrl-0 = < &pmx_i2c_gpio_sda &pmx_i2c_gpio_scl >; + pinctrl-names = "default"; + + pmx_i2c_gpio_sda: pmx-gpio-sda { + marvell,pins = "mpp8"; + marvell,function = "gpio"; + }; + pmx_i2c_gpio_scl: pmx-gpio-scl { + marvell,pins = "mpp9"; + marvell,function = "gpio"; + }; + }; + + serial@12000 { + status = "okay"; + }; + }; + + i2c@0 { + compatible = "i2c-gpio"; + gpios = < &gpio0 8 GPIO_ACTIVE_HIGH /* sda */ + &gpio0 9 GPIO_ACTIVE_HIGH>; /* scl */ + i2c-gpio,delay-us = <2>; /* ~100 kHz */ + }; +}; + +&nand { + status = "okay"; + chip-delay = <25>; +}; diff --git a/arch/arm/boot/dts/kirkwood-km_fixedeth.dts b/arch/arm/boot/dts/kirkwood-km_fixedeth.dts new file mode 100644 index 000000000000..9895f2b10f8a --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-km_fixedeth.dts @@ -0,0 +1,23 @@ +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-98dx4122.dtsi" +#include "kirkwood-km_common.dtsi" + +/ { + model = "Keymile Kirkwood Fixed Eth"; + compatible = "keymile,km_fixedeth", "marvell,kirkwood-98DX4122", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x10000000>; + }; +}; + +ð0 { + status = "okay"; + ethernet0-port@0 { + speed = <1000>; /* <SPEED_1000> */ + duplex = <1>; /* <DUPLEX_FULL> */ + }; +}; diff --git a/arch/arm/boot/dts/kirkwood-km_kirkwood.dts b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts index 04a1e44541b3..235bf382fff9 100644 --- a/arch/arm/boot/dts/kirkwood-km_kirkwood.dts +++ b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts @@ -2,6 +2,7 @@ #include "kirkwood.dtsi" #include "kirkwood-98dx4122.dtsi" +#include "kirkwood-km_common.dtsi" / { model = "Keymile Kirkwood Reference Design"; @@ -11,44 +12,6 @@ device_type = "memory"; reg = <0x00000000 0x08000000>; }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - }; - - ocp@f1000000 { - pinctrl: pinctrl@10000 { - pinctrl-0 = < &pmx_i2c_gpio_sda &pmx_i2c_gpio_scl >; - pinctrl-names = "default"; - - pmx_i2c_gpio_sda: pmx-gpio-sda { - marvell,pins = "mpp8"; - marvell,function = "gpio"; - }; - pmx_i2c_gpio_scl: pmx-gpio-scl { - marvell,pins = "mpp9"; - marvell,function = "gpio"; - }; - }; - - serial@12000 { - status = "ok"; - }; - }; - - i2c@0 { - compatible = "i2c-gpio"; - gpios = < &gpio0 8 GPIO_ACTIVE_HIGH /* sda */ - &gpio0 9 GPIO_ACTIVE_HIGH>; /* scl */ - i2c-gpio,delay-us = <2>; /* ~100 kHz */ - }; -}; - -&nand { - pinctrl-0 = <&pmx_nand>; - pinctrl-names = "default"; - status = "ok"; - chip-delay = <25>; }; &mdio { diff --git a/arch/arm/boot/dts/kirkwood-laplug.dts b/arch/arm/boot/dts/kirkwood-laplug.dts index 6761ffa2c4ab..24425660e973 100644 --- a/arch/arm/boot/dts/kirkwood-laplug.dts +++ b/arch/arm/boot/dts/kirkwood-laplug.dts @@ -24,6 +24,7 @@ chosen { bootargs = "console=ttyS0,115200n8 earlyprintk"; + stdout-path = &uart0; }; mbus { @@ -37,14 +38,10 @@ ocp@f1000000 { serial@12000 { - pinctrl-0 = <&pmx_uart0>; - pinctrl-names = "default"; status = "okay"; }; i2c@11000 { - pinctrl-0 = <&pmx_twsi0>; - pinctrl-names = "default"; status = "okay"; eeprom@50 { @@ -54,7 +51,7 @@ }; }; - pinctrl: pinctrl@10000 { + pinctrl: pin-controller@10000 { pmx_usb_power_enable: pmx-usb-power-enable { marvell,pins = "mpp14"; marvell,function = "gpio"; @@ -139,7 +136,6 @@ &nand { /* Total size : 512MB */ status = "okay"; - pinctrl-0 = <&pmx_nand>; partition@0 { label = "u-boot"; diff --git a/arch/arm/boot/dts/kirkwood-lsxl.dtsi b/arch/arm/boot/dts/kirkwood-lsxl.dtsi index 1656653d339b..53484474df1f 100644 --- a/arch/arm/boot/dts/kirkwood-lsxl.dtsi +++ b/arch/arm/boot/dts/kirkwood-lsxl.dtsi @@ -4,10 +4,11 @@ / { chosen { bootargs = "console=ttyS0,115200n8 earlyprintk"; + stdout-path = &uart0; }; ocp@f1000000 { - pinctrl: pinctrl@10000 { + pinctrl: pin-controller@10000 { pmx_power_hdd: pmx-power-hdd { marvell,pins = "mpp10"; marvell,function = "gpo"; diff --git a/arch/arm/boot/dts/kirkwood-mplcec4.dts b/arch/arm/boot/dts/kirkwood-mplcec4.dts index 73722c067501..f3a991837515 100644 --- a/arch/arm/boot/dts/kirkwood-mplcec4.dts +++ b/arch/arm/boot/dts/kirkwood-mplcec4.dts @@ -12,9 +12,10 @@ reg = <0x00000000 0x20000000>; }; - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - }; + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk"; + stdout-path = &uart0; + }; mbus { pcie-controller { @@ -27,7 +28,7 @@ }; ocp@f1000000 { - pinctrl: pinctrl@10000 { + pinctrl: pin-controller@10000 { pmx_led_health: pmx-led-health { marvell,pins = "mpp7"; marvell,function = "gpo"; @@ -89,11 +90,9 @@ }; - serial@12000 { - status = "ok"; - pinctrl-0 = <&pmx_uart0>; - pinctrl-names = "default"; - }; + serial@12000 { + status = "okay"; + }; rtc@10300 { status = "disabled"; @@ -163,8 +162,6 @@ }; &nand { - pinctrl-0 = <&pmx_nand>; - pinctrl-names = "default"; status = "okay"; partition@0 { diff --git a/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts b/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts index b939f4f52d16..8f76d28759a3 100644 --- a/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts +++ b/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts @@ -28,6 +28,7 @@ chosen { bootargs = "console=ttyS0,115200n8 earlyprintk"; + stdout-path = &uart0; }; mbus { @@ -41,7 +42,7 @@ }; ocp@f1000000 { - pinctrl@10000 { + pin-controller@10000 { pmx_usb_led: pmx-usb-led { marvell,pins = "mpp12"; marvell,function = "gpo"; @@ -59,8 +60,6 @@ }; spi@10600 { - pinctrl-0 = <&pmx_spi>; - pinctrl-names = "default"; status = "okay"; flash@0 { @@ -74,10 +73,7 @@ }; serial@12000 { - pinctrl-0 = <&pmx_uart0>; - pinctrl-names = "default"; - clock-frequency = <200000000>; - status = "ok"; + status = "okay"; }; ehci@50000 { diff --git a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts index 4838478019cc..fd733c63bc27 100644 --- a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts +++ b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts @@ -25,6 +25,7 @@ chosen { bootargs = "console=ttyS0,115200n8 earlyprintk"; + stdout-path = &uart0; }; mbus { @@ -38,7 +39,7 @@ }; ocp@f1000000 { - pinctrl: pinctrl@10000 { + pinctrl: pin-controller@10000 { pmx_button_power: pmx-button-power { marvell,pins = "mpp47"; marvell,function = "gpio"; @@ -112,8 +113,6 @@ }; serial@12000 { - pinctrl-0 = <&pmx_uart0>; - pinctrl-names = "default"; status = "okay"; }; diff --git a/arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts b/arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts index 7c8a0d9d8d1f..b514d643fb6c 100644 --- a/arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts +++ b/arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts @@ -25,6 +25,7 @@ chosen { bootargs = "console=ttyS0,115200n8 earlyprintk"; + stdout-path = &uart0; }; mbus { @@ -40,7 +41,7 @@ }; ocp@f1000000 { - pinctrl: pinctrl@10000 { + pinctrl: pin-controller@10000 { pmx_button_power: pmx-button-power { marvell,pins = "mpp47"; marvell,function = "gpio"; @@ -119,8 +120,6 @@ }; serial@12000 { - pinctrl-0 = <&pmx_uart0>; - pinctrl-names = "default"; status = "okay"; }; diff --git a/arch/arm/boot/dts/kirkwood-ns2-common.dtsi b/arch/arm/boot/dts/kirkwood-ns2-common.dtsi index e6e5ec4fe6b9..fe6c0246db1a 100644 --- a/arch/arm/boot/dts/kirkwood-ns2-common.dtsi +++ b/arch/arm/boot/dts/kirkwood-ns2-common.dtsi @@ -4,10 +4,11 @@ / { chosen { bootargs = "console=ttyS0,115200n8"; + stdout-path = &uart0; }; ocp@f1000000 { - pinctrl: pinctrl@10000 { + pinctrl: pin-controller@10000 { pmx_ns2_sata0: pmx-ns2-sata0 { marvell,pins = "mpp21"; marvell,function = "sata0"; @@ -19,14 +20,10 @@ }; serial@12000 { - pinctrl-0 = <&pmx_uart0>; - pinctrl-names = "default"; status = "okay"; }; spi@10600 { - pinctrl-0 = <&pmx_spi>; - pinctrl-names = "default"; status = "okay"; flash@0 { @@ -45,8 +42,6 @@ }; i2c@11000 { - pinctrl-0 = <&pmx_twsi0>; - pinctrl-names = "default"; status = "okay"; eeprom@50 { diff --git a/arch/arm/boot/dts/kirkwood-nsa310.dts b/arch/arm/boot/dts/kirkwood-nsa310.dts index 0a07af9d8e58..6139df0f376c 100644 --- a/arch/arm/boot/dts/kirkwood-nsa310.dts +++ b/arch/arm/boot/dts/kirkwood-nsa310.dts @@ -1,6 +1,6 @@ /dts-v1/; -#include "kirkwood-nsa310-common.dtsi" +#include "kirkwood-nsa3x0-common.dtsi" / { compatible = "zyxel,nsa310", "marvell,kirkwood-88f6281", "marvell,kirkwood"; @@ -12,6 +12,7 @@ chosen { bootargs = "console=ttyS0,115200"; + stdout-path = &uart0; }; mbus { @@ -25,7 +26,7 @@ }; ocp@f1000000 { - pinctrl: pinctrl@10000 { + pinctrl: pin-controller@10000 { pinctrl-0 = <&pmx_unknown>; pinctrl-names = "default"; @@ -59,26 +60,6 @@ marvell,function = "gpio"; }; - pmx_btn_reset: pmx-btn-reset { - marvell,pins = "mpp36"; - marvell,function = "gpio"; - }; - - pmx_btn_copy: pmx-btn-copy { - marvell,pins = "mpp37"; - marvell,function = "gpio"; - }; - - pmx_led_copy_green: pmx-led-copy-green { - marvell,pins = "mpp39"; - marvell,function = "gpio"; - }; - - pmx_led_copy_red: pmx-led-copy-red { - marvell,pins = "mpp40"; - marvell,function = "gpio"; - }; - pmx_led_hdd_green: pmx-led-hdd-green { marvell,pins = "mpp41"; marvell,function = "gpio"; @@ -94,10 +75,6 @@ marvell,function = "gpio"; }; - pmx_btn_power: pmx-btn-power { - marvell,pins = "mpp46"; - marvell,function = "gpio"; - }; }; i2c@11000 { @@ -110,30 +87,6 @@ }; }; - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_btn_reset &pmx_btn_copy &pmx_btn_power>; - pinctrl-names = "default"; - - button@1 { - label = "Power Button"; - linux,code = <KEY_POWER>; - gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; - }; - button@2 { - label = "Copy Button"; - linux,code = <KEY_COPY>; - gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; - }; - button@3 { - label = "Reset Button"; - linux,code = <KEY_RESTART>; - gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - }; - }; - gpio-leds { compatible = "gpio-leds"; pinctrl-0 = <&pmx_led_esata_green &pmx_led_esata_red diff --git a/arch/arm/boot/dts/kirkwood-nsa310a.dts b/arch/arm/boot/dts/kirkwood-nsa310a.dts index 27ca6a79c48a..3d2b3d494c19 100644 --- a/arch/arm/boot/dts/kirkwood-nsa310a.dts +++ b/arch/arm/boot/dts/kirkwood-nsa310a.dts @@ -1,6 +1,6 @@ /dts-v1/; -#include "kirkwood-nsa310-common.dtsi" +#include "kirkwood-nsa3x0-common.dtsi" /* * There are at least two different NSA310 designs. This variant does @@ -17,10 +17,11 @@ chosen { bootargs = "console=ttyS0,115200"; + stdout-path = &uart0; }; ocp@f1000000 { - pinctrl: pinctrl@10000 { + pinctrl: pin-controller@10000 { pinctrl-names = "default"; pmx_led_esata_green: pmx-led-esata-green { @@ -38,11 +39,6 @@ marvell,function = "gpio"; }; - pmx_usb_power_off: pmx-usb-power-off { - marvell,pins = "mpp21"; - marvell,function = "gpio"; - }; - pmx_led_sys_green: pmx-led-sys-green { marvell,pins = "mpp28"; marvell,function = "gpio"; @@ -53,26 +49,6 @@ marvell,function = "gpio"; }; - pmx_btn_reset: pmx-btn-reset { - marvell,pins = "mpp36"; - marvell,function = "gpio"; - }; - - pmx_btn_copy: pmx-btn-copy { - marvell,pins = "mpp37"; - marvell,function = "gpio"; - }; - - pmx_led_copy_green: pmx-led-copy-green { - marvell,pins = "mpp39"; - marvell,function = "gpio"; - }; - - pmx_led_copy_red: pmx-led-copy-red { - marvell,pins = "mpp40"; - marvell,function = "gpio"; - }; - pmx_led_hdd_green: pmx-led-hdd-green { marvell,pins = "mpp41"; marvell,function = "gpio"; @@ -83,11 +59,6 @@ marvell,function = "gpio"; }; - pmx_btn_power: pmx-btn-power { - marvell,pins = "mpp46"; - marvell,function = "gpio"; - }; - }; i2c@11000 { @@ -100,28 +71,6 @@ }; }; - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - button@1 { - label = "Power Button"; - linux,code = <KEY_POWER>; - gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; - }; - button@2 { - label = "Copy Button"; - linux,code = <KEY_COPY>; - gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; - }; - button@3 { - label = "Reset Button"; - linux,code = <KEY_RESTART>; - gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - }; - }; - gpio-leds { compatible = "gpio-leds"; diff --git a/arch/arm/boot/dts/kirkwood-nsa320.dts b/arch/arm/boot/dts/kirkwood-nsa320.dts new file mode 100644 index 000000000000..24f686d1044d --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-nsa320.dts @@ -0,0 +1,215 @@ +/* Device tree file for the Zyxel NSA 320 NAS box. + * + * Copyright (c) 2014, Adam Baker <linux@baker-net.org.uk> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + * Based upon the board setup file created by Peter Schildmann */ + +/dts-v1/; + +#include "kirkwood-nsa3x0-common.dtsi" + +/ { + model = "Zyxel NSA320"; + compatible = "zyxel,nsa320", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x20000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200"; + stdout-path = &uart0; + }; + + mbus { + pcie-controller { + status = "okay"; + + pcie@1,0 { + status = "okay"; + }; + }; + }; + + ocp@f1000000 { + pinctrl: pin-controller@10000 { + pinctrl-names = "default"; + + /* SATA Activity and Present pins are not connected */ + pmx_sata0: pmx-sata0 { + marvell,pins ; + marvell,function = "sata0"; + }; + + pmx_sata1: pmx-sata1 { + marvell,pins ; + marvell,function = "sata1"; + }; + + pmx_led_hdd2_green: pmx-led-hdd2-green { + marvell,pins = "mpp12"; + marvell,function = "gpio"; + }; + + pmx_led_hdd2_red: pmx-led-hdd2-red { + marvell,pins = "mpp13"; + marvell,function = "gpio"; + }; + + pmx_mcu_data: pmx-mcu-data { + marvell,pins = "mpp14"; + marvell,function = "gpio"; + }; + + pmx_led_usb_green: pmx-led-usb-green { + marvell,pins = "mpp15"; + marvell,function = "gpio"; + }; + + pmx_mcu_clk: pmx-mcu-clk { + marvell,pins = "mpp16"; + marvell,function = "gpio"; + }; + + pmx_mcu_act: pmx-mcu-act { + marvell,pins = "mpp17"; + marvell,function = "gpio"; + }; + + pmx_led_sys_green: pmx-led-sys-green { + marvell,pins = "mpp28"; + marvell,function = "gpio"; + }; + + pmx_led_sys_orange: pmx-led-sys-orange { + marvell,pins = "mpp29"; + marvell,function = "gpio"; + }; + + pmx_led_hdd1_green: pmx-led-hdd1-green { + marvell,pins = "mpp41"; + marvell,function = "gpio"; + }; + + pmx_led_hdd1_red: pmx-led-hdd1-red { + marvell,pins = "mpp42"; + marvell,function = "gpio"; + }; + + pmx_htp: pmx-htp { + marvell,pins = "mpp43"; + marvell,function = "gpio"; + }; + + /* Buzzer needs to be switched at around 1kHz so is + not compatible with the gpio-beeper driver. */ + pmx_buzzer: pmx-buzzer { + marvell,pins = "mpp44"; + marvell,function = "gpio"; + }; + + pmx_vid_b1: pmx-vid-b1 { + marvell,pins = "mpp45"; + marvell,function = "gpio"; + }; + + pmx_power_resume_data: pmx-power-resume-data { + marvell,pins = "mpp47"; + marvell,function = "gpio"; + }; + + pmx_power_resume_clk: pmx-power-resume-clk { + marvell,pins = "mpp49"; + marvell,function = "gpio"; + }; + }; + + i2c@11000 { + status = "okay"; + + pcf8563: pcf8563@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; + }; + }; + + regulators { + usb0_power: regulator@1 { + enable-active-high; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = <&pmx_led_hdd2_green &pmx_led_hdd2_red + &pmx_led_usb_green + &pmx_led_sys_green &pmx_led_sys_orange + &pmx_led_copy_green &pmx_led_copy_red + &pmx_led_hdd1_green &pmx_led_hdd1_red>; + pinctrl-names = "default"; + + green-sys { + label = "nsa320:green:sys"; + gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; + }; + orange-sys { + label = "nsa320:orange:sys"; + gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; + }; + green-hdd1 { + label = "nsa320:green:hdd1"; + gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; + }; + red-hdd1 { + label = "nsa320:red:hdd1"; + gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; + }; + green-hdd2 { + label = "nsa320:green:hdd2"; + gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; + }; + red-hdd2 { + label = "nsa320:red:hdd2"; + gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; + }; + green-usb { + label = "nsa320:green:usb"; + gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; + }; + green-copy { + label = "nsa320:green:copy"; + gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + }; + red-copy { + label = "nsa320:red:copy"; + gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; + }; + }; + + /* The following pins are currently not assigned to a driver, + some of them should be configured as inputs. + pinctrl-0 = <&pmx_mcu_data &pmx_mcu_clk &pmx_mcu_act + &pmx_htp &pmx_vid_b1 + &pmx_power_resume_data &pmx_power_resume_clk>; */ +}; + +&mdio { + status = "okay"; + ethphy0: ethernet-phy@1 { + reg = <1>; + }; +}; + +ð0 { + status = "okay"; + ethernet0-port@0 { + phy-handle = <ðphy0>; + }; +}; diff --git a/arch/arm/boot/dts/kirkwood-nsa310-common.dtsi b/arch/arm/boot/dts/kirkwood-nsa3x0-common.dtsi index e2cc85cc3b87..2075a2e828f1 100644 --- a/arch/arm/boot/dts/kirkwood-nsa310-common.dtsi +++ b/arch/arm/boot/dts/kirkwood-nsa3x0-common.dtsi @@ -15,17 +15,42 @@ }; ocp@f1000000 { - pinctrl: pinctrl@10000 { + pinctrl: pin-controller@10000 { - pmx_usb_power_off: pmx-usb-power-off { + pmx_usb_power: pmx-usb-power { marvell,pins = "mpp21"; marvell,function = "gpio"; }; + pmx_pwr_off: pmx-pwr-off { marvell,pins = "mpp48"; marvell,function = "gpio"; }; + pmx_btn_reset: pmx-btn-reset { + marvell,pins = "mpp36"; + marvell,function = "gpio"; + }; + + pmx_btn_copy: pmx-btn-copy { + marvell,pins = "mpp37"; + marvell,function = "gpio"; + }; + + pmx_btn_power: pmx-btn-power { + marvell,pins = "mpp46"; + marvell,function = "gpio"; + }; + + pmx_led_copy_green: pmx-led-copy-green { + marvell,pins = "mpp39"; + marvell,function = "gpio"; + }; + + pmx_led_copy_red: pmx-led-copy-red { + marvell,pins = "mpp40"; + marvell,function = "gpio"; + }; }; serial@12000 { @@ -45,17 +70,42 @@ gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>; }; + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pmx_btn_reset &pmx_btn_copy &pmx_btn_power>; + pinctrl-names = "default"; + + button@1 { + label = "Power Button"; + linux,code = <KEY_POWER>; + gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; + }; + button@2 { + label = "Copy Button"; + linux,code = <KEY_COPY>; + gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; + }; + button@3 { + label = "Reset Button"; + linux,code = <KEY_RESTART>; + gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + }; + }; + + regulators { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <0>; - pinctrl-0 = <&pmx_usb_power_off>; + pinctrl-0 = <&pmx_usb_power>; pinctrl-names = "default"; - usb0_power_off: regulator@1 { + usb0_power: regulator@1 { compatible = "regulator-fixed"; reg = <1>; - regulator-name = "USB Power Off"; + regulator-name = "USB Power"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; regulator-always-on; diff --git a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts index 0650beafc1de..fb9dc227255d 100644 --- a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts +++ b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts @@ -14,19 +14,16 @@ chosen { bootargs = "console=ttyS0,115200n8 earlyprintk"; + stdout-path = &uart0; }; ocp@f1000000 { serial@12000 { - status = "ok"; - pinctrl-0 = <&pmx_uart0>; - pinctrl-names = "default"; + status = "okay"; }; serial@12100 { - status = "ok"; - pinctrl-0 = <&pmx_uart1>; - pinctrl-names = "default"; + status = "okay"; }; sata@80000 { @@ -36,8 +33,6 @@ i2c@11100 { status = "okay"; - pinctrl-0 = <&pmx_twsi1>; - pinctrl-names = "default"; s35390a: s35390a@30 { compatible = "sii,s35390a"; @@ -45,7 +40,7 @@ }; }; - pinctrl: pinctrl@10000 { + pinctrl: pin-controller@10000 { pinctrl-0 = <&pmx_dip_switches &pmx_gpio_header>; pinctrl-names = "default"; @@ -133,8 +128,6 @@ &nand { chip-delay = <25>; status = "okay"; - pinctrl-0 = <&pmx_nand>; - pinctrl-names = "default"; partition@0 { label = "uboot"; diff --git a/arch/arm/boot/dts/kirkwood-openblocks_a7.dts b/arch/arm/boot/dts/kirkwood-openblocks_a7.dts index 38520a287514..d5e3bc518968 100644 --- a/arch/arm/boot/dts/kirkwood-openblocks_a7.dts +++ b/arch/arm/boot/dts/kirkwood-openblocks_a7.dts @@ -26,19 +26,16 @@ chosen { bootargs = "console=ttyS0,115200n8 earlyprintk"; + stdout-path = &uart0; }; ocp@f1000000 { serial@12000 { - status = "ok"; - pinctrl-0 = <&pmx_uart0>; - pinctrl-names = "default"; + status = "okay"; }; serial@12100 { - status = "ok"; - pinctrl-0 = <&pmx_uart1>; - pinctrl-names = "default"; + status = "okay"; }; sata@80000 { @@ -48,8 +45,6 @@ i2c@11100 { status = "okay"; - pinctrl-0 = <&pmx_twsi1>; - pinctrl-names = "default"; s24c02: s24c02@50 { compatible = "atmel,24c02"; @@ -57,7 +52,7 @@ }; }; - pinctrl: pinctrl@10000 { + pinctrl: pin-controller@10000 { pinctrl-0 = <&pmx_dip_switches &pmx_gpio_header>; pinctrl-names = "default"; @@ -109,13 +104,6 @@ marvell,pins = "mpp41", "mpp42", "mpp43"; marvell,function = "gpio"; }; - - pmx_ge1: pmx-ge1 { - marvell,pins = "mpp20", "mpp21", "mpp22", "mpp23", - "mpp24", "mpp25", "mpp26", "mpp27", - "mpp30", "mpp31", "mpp32", "mpp33"; - marvell,function = "ge1"; - }; }; }; @@ -158,8 +146,6 @@ &nand { chip-delay = <25>; status = "okay"; - pinctrl-0 = <&pmx_nand>; - pinctrl-names = "default"; partition@0 { label = "uboot"; @@ -213,8 +199,6 @@ ð1 { status = "okay"; - pinctrl-0 = <&pmx_ge1>; - pinctrl-names = "default"; ethernet1-port@0 { phy-handle = <ðphy1>; }; diff --git a/arch/arm/boot/dts/kirkwood-openrd-base.dts b/arch/arm/boot/dts/kirkwood-openrd-base.dts new file mode 100644 index 000000000000..8af58999606d --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-openrd-base.dts @@ -0,0 +1,42 @@ +/* + * Marvell OpenRD Base Board Description + * + * Andrew Lunn <andrew@lunn.ch> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + * + * This file contains the definitions that are specific to OpenRD + * base variant of the Marvell Kirkwood Development Board. + */ + +/dts-v1/; + +#include "kirkwood-openrd.dtsi" + +/ { + model = "OpenRD Base"; + compatible = "marvell,openrd-base", "marvell,openrd", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + + ocp@f1000000 { + serial@12100 { + status = "okay"; + }; + }; +}; + +&mdio { + status = "okay"; + + ethphy0: ethernet-phy@8 { + reg = <8>; + }; +}; + +ð0 { + status = "okay"; + ethernet0-port@0 { + phy-handle = <ðphy0>; + }; +}; diff --git a/arch/arm/boot/dts/kirkwood-openrd-client.dts b/arch/arm/boot/dts/kirkwood-openrd-client.dts new file mode 100644 index 000000000000..887b9c1fee43 --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-openrd-client.dts @@ -0,0 +1,73 @@ +/* + * Marvell OpenRD Client Board Description + * + * Andrew Lunn <andrew@lunn.ch> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + * + * This file contains the definitions that are specific to OpenRD + * client variant of the Marvell Kirkwood Development Board. + */ + +/dts-v1/; + +#include "kirkwood-openrd.dtsi" + +/ { + model = "OpenRD Client"; + compatible = "marvell,openrd-client", "marvell,openrd", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + + ocp@f1000000 { + i2c@11000 { + status = "okay"; + clock-frequency = <400000>; + + cs42l51: cs42l51@4a { + compatible = "cirrus,cs42l51"; + reg = <0x4a>; + }; + }; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + + simple-audio-card,cpu { + sound-dai = <&audio0>; + }; + + simple-audio-card,codec { + sound-dai = <&cs42l51>; + }; + }; +}; + +&mdio { + status = "okay"; + + ethphy0: ethernet-phy@8 { + reg = <8>; + }; + ethphy1: ethernet-phy@24 { + reg = <24>; + }; +}; + +ð0 { + status = "okay"; + ethernet0-port@0 { + phy-handle = <ðphy0>; + }; +}; + +ð1 { + status = "okay"; + ethernet1-port@0 { + phy-handle = <ðphy1>; + }; +}; + diff --git a/arch/arm/boot/dts/kirkwood-openrd-ultimate.dts b/arch/arm/boot/dts/kirkwood-openrd-ultimate.dts new file mode 100644 index 000000000000..9f12f8b53e24 --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-openrd-ultimate.dts @@ -0,0 +1,58 @@ +/* + * Marvell OpenRD Ultimate Board Description + * + * Andrew Lunn <andrew@lunn.ch> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + * + * This file contains the definitions that are specific to OpenRD + * ultimate variant of the Marvell Kirkwood Development Board. + */ + +/dts-v1/; + +#include "kirkwood-openrd.dtsi" + +/ { + model = "OpenRD Ultimate"; + compatible = "marvell,openrd-ultimate", "marvell,openrd", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + + ocp@f1000000 { + i2c@11000 { + status = "okay"; + clock-frequency = <400000>; + + cs42l51: cs42l51@4a { + compatible = "cirrus,cs42l51"; + reg = <0x4a>; + }; + }; + }; +}; + +&mdio { + status = "okay"; + + ethphy0: ethernet-phy@0 { + reg = <0>; + }; + ethphy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +ð0 { + status = "okay"; + ethernet0-port@0 { + phy-handle = <ðphy0>; + }; +}; + +ð1 { + status = "okay"; + ethernet1-port@0 { + phy-handle = <ðphy1>; + }; +}; diff --git a/arch/arm/boot/dts/kirkwood-openrd.dtsi b/arch/arm/boot/dts/kirkwood-openrd.dtsi new file mode 100644 index 000000000000..d3330dadf7ed --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-openrd.dtsi @@ -0,0 +1,90 @@ +/* + * Marvell OpenRD (Base|Client|Ultimate) Board Description + * + * Andrew Lunn <andrew@lunn.ch> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + * + * This file contains the definitions that are common between the three + * variants of the Marvell Kirkwood Development Board. + */ + +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" + +/ { + memory { + device_type = "memory"; + reg = <0x00000000 0x20000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + stdout-path = &uart0; + }; + + mbus { + pcie-controller { + status = "okay"; + + pcie@1,0 { + status = "okay"; + }; + }; + }; + + ocp@f1000000 { + pinctrl: pin-controller@10000 { + pinctrl-0 = <&pmx_select28 &pmx_sdio_cd &pmx_select34>; + pinctrl-names = "default"; + + pmx_select28: pmx-select-uart-sd { + marvell,pins = "mpp28"; + marvell,function = "gpio"; + }; + pmx_sdio_cd: pmx-sdio-cd { + marvell,pins = "mpp29"; + marvell,function = "gpio"; + }; + pmx_select34: pmx-select-rs232-rs484 { + marvell,pins = "mpp34"; + marvell,function = "gpio"; + }; + }; + serial@12000 { + status = "okay"; + + }; + sata@80000 { + status = "okay"; + nr-ports = <2>; + }; + mvsdio@90000 { + status = "okay"; + cd-gpios = <&gpio0 29 9>; + }; + }; +}; + +&nand { + status = "okay"; + pinctrl-0 = <&pmx_nand>; + pinctrl-names = "default"; + + partition@0 { + label = "u-boot"; + reg = <0x0000000 0x100000>; + }; + + partition@100000 { + label = "uImage"; + reg = <0x0100000 0x400000>; + }; + + partition@600000 { + label = "root"; + reg = <0x0600000 0x1FA00000>; + }; +}; diff --git a/arch/arm/boot/dts/kirkwood-rd88f6192.dts b/arch/arm/boot/dts/kirkwood-rd88f6192.dts index e9dd85049297..35a29dee8dd8 100644 --- a/arch/arm/boot/dts/kirkwood-rd88f6192.dts +++ b/arch/arm/boot/dts/kirkwood-rd88f6192.dts @@ -26,6 +26,7 @@ chosen { bootargs = "console=ttyS0,115200n8"; + stdout-path = &uart0; }; mbus { @@ -39,7 +40,7 @@ }; ocp@f1000000 { - pinctrl: pinctrl@10000 { + pinctrl: pin-controller@10000 { pinctrl-0 = <&pmx_usb_power>; pinctrl-names = "default"; @@ -56,8 +57,6 @@ spi@10600 { status = "okay"; - pinctrl-0 = <&pmx_spi>; - pinctrl-names = "default"; m25p128@0 { #address-cells = <1>; diff --git a/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi b/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi index d6368c39102e..26cf0e0ccefd 100644 --- a/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi +++ b/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi @@ -22,6 +22,7 @@ chosen { bootargs = "console=ttyS0,115200n8"; + stdout-path = &uart0; }; mbus { @@ -35,7 +36,7 @@ }; ocp@f1000000 { - pinctrl: pinctrl@10000 { + pinctrl: pin-controller@10000 { pinctrl-0 = <&pmx_sdio_cd>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/kirkwood-rs212.dts b/arch/arm/boot/dts/kirkwood-rs212.dts index 93ec3d00c6ab..3b19f1fd4cac 100644 --- a/arch/arm/boot/dts/kirkwood-rs212.dts +++ b/arch/arm/boot/dts/kirkwood-rs212.dts @@ -24,6 +24,7 @@ chosen { bootargs = "console=ttyS0,115200n8"; + stdout-path = &uart0; }; gpio-fan-100-15-35-3 { diff --git a/arch/arm/boot/dts/kirkwood-rs409.dts b/arch/arm/boot/dts/kirkwood-rs409.dts index 311df4e5aa28..921ca49e85a4 100644 --- a/arch/arm/boot/dts/kirkwood-rs409.dts +++ b/arch/arm/boot/dts/kirkwood-rs409.dts @@ -24,6 +24,7 @@ chosen { bootargs = "console=ttyS0,115200n8"; + stdout-path = &uart0; }; gpio-fan-150-15-18 { diff --git a/arch/arm/boot/dts/kirkwood-rs411.dts b/arch/arm/boot/dts/kirkwood-rs411.dts index f90da850bb31..02852b0c809f 100644 --- a/arch/arm/boot/dts/kirkwood-rs411.dts +++ b/arch/arm/boot/dts/kirkwood-rs411.dts @@ -24,6 +24,7 @@ chosen { bootargs = "console=ttyS0,115200n8"; + stdout-path = &uart0; }; gpio-fan-100-15-35-3 { diff --git a/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi b/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi index 1ff848d570a9..7196c7f3e109 100644 --- a/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi +++ b/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi @@ -17,10 +17,11 @@ chosen { bootargs = "console=ttyS0,115200n8 earlyprintk"; + stdout-path = &uart0; }; ocp@f1000000 { - pinctrl: pinctrl@10000 { + pinctrl: pin-controller@10000 { pmx_usb_power_enable: pmx-usb-power-enable { marvell,pins = "mpp29"; @@ -44,8 +45,6 @@ }; }; serial@12000 { - pinctrl-0 = <&pmx_uart0>; - pinctrl-names = "default"; status = "okay"; }; }; @@ -72,8 +71,6 @@ }; &nand { - pinctrl-0 = <&pmx_nand>; - pinctrl-names = "default"; status = "okay"; partition@0 { diff --git a/arch/arm/boot/dts/kirkwood-synology.dtsi b/arch/arm/boot/dts/kirkwood-synology.dtsi index 4227c974729d..811e0971fc58 100644 --- a/arch/arm/boot/dts/kirkwood-synology.dtsi +++ b/arch/arm/boot/dts/kirkwood-synology.dtsi @@ -25,7 +25,7 @@ }; ocp@f1000000 { - pinctrl: pinctrl@10000 { + pinctrl: pin-controller@10000 { pmx_alarmled_12: pmx-alarmled-12 { marvell,pins = "mpp12"; marvell,function = "gpio"; @@ -213,8 +213,6 @@ spi@10600 { status = "okay"; - pinctrl-0 = <&pmx_spi>; - pinctrl-names = "default"; m25p80@0 { #address-cells = <1>; @@ -259,8 +257,6 @@ i2c@11000 { status = "okay"; clock-frequency = <400000>; - pinctrl-0 = <&pmx_twsi0>; - pinctrl-names = "default"; rs5c372: rs5c372@32 { status = "disabled"; @@ -277,14 +273,10 @@ serial@12000 { status = "okay"; - pinctrl-0 = <&pmx_uart0>; - pinctrl-names = "default"; }; serial@12100 { status = "okay"; - pinctrl-0 = <&pmx_uart1>; - pinctrl-names = "default"; }; poweroff@12100 { diff --git a/arch/arm/boot/dts/kirkwood-t5325.dts b/arch/arm/boot/dts/kirkwood-t5325.dts index 0bd70d928c69..610ec0f95858 100644 --- a/arch/arm/boot/dts/kirkwood-t5325.dts +++ b/arch/arm/boot/dts/kirkwood-t5325.dts @@ -27,6 +27,7 @@ chosen { bootargs = "console=ttyS0,115200n8"; + stdout-path = &uart0; }; mbus { @@ -40,7 +41,7 @@ }; ocp@f1000000 { - pinctrl: pinctrl@10000 { + pinctrl: pin-controller@10000 { pinctrl-0 = <&pmx_i2s &pmx_sysrst>; pinctrl-names = "default"; @@ -64,10 +65,6 @@ marvell,function = "gpio"; }; - /* - * Redefined from kirkwood-6281.dtsi, because - * we don't use SPI CS on MPP0, but on MPP7. - */ pmx_spi: pmx-spi { marvell,pins = "mpp1", "mpp2", "mpp3", "mpp7"; marvell,function = "spi"; @@ -86,8 +83,6 @@ }; spi@10600 { - pinctrl-0 = <&pmx_spi>; - pinctrl-names = "default"; status = "okay"; flash@0 { @@ -127,6 +122,14 @@ i2c@11000 { status = "okay"; + + alc5621: alc5621@1a { + compatible = "realtek,alc5621"; + reg = <0x1a>; + #sound-dai-cells = <0>; + add-ctrl = <0x3700>; + jack-det-ctrl = <0x4810>; + }; }; serial@12000 { @@ -184,6 +187,31 @@ gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; }; + sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,routing = + "Headphone Jack", "HPL", + "Headphone Jack", "HPR", + "Speaker", "SPKOUT", + "Speaker", "SPKOUTN", + "MIC1", "Mic Jack", + "MIC2", "Mic Jack"; + simple-audio-card,widgets = + "Headphone", "Headphone Jack", + "Speaker", "Speaker", + "Microphone", "Mic Jack"; + + simple-audio-card,mclk-fs = <256>; + + simple-audio-card,cpu { + sound-dai = <&audio>; + }; + + simple-audio-card,codec { + sound-dai = <&alc5621>; + }; + }; }; &mdio { diff --git a/arch/arm/boot/dts/kirkwood-topkick.dts b/arch/arm/boot/dts/kirkwood-topkick.dts index 5fc817c2cb87..f5c8c0dd41dc 100644 --- a/arch/arm/boot/dts/kirkwood-topkick.dts +++ b/arch/arm/boot/dts/kirkwood-topkick.dts @@ -14,10 +14,11 @@ chosen { bootargs = "console=ttyS0,115200n8 earlyprintk"; + stdout-path = &uart0; }; ocp@f1000000 { - pinctrl: pinctrl@10000 { + pinctrl: pin-controller@10000 { /* * Switch positions * @@ -85,9 +86,7 @@ }; serial@12000 { - status = "ok"; - pinctrl-0 = <&pmx_uart0>; - pinctrl-names = "default"; + status = "okay"; }; sata@80000 { @@ -96,9 +95,7 @@ }; i2c@11000 { - status = "ok"; - pinctrl-0 = <&pmx_twsi0>; - pinctrl-names = "default"; + status = "okay"; }; mvsdio@90000 { @@ -175,8 +172,6 @@ &nand { status = "okay"; - pinctrl-0 = <&pmx_nand>; - pinctrl-names = "default"; partition@0 { label = "u-boot"; diff --git a/arch/arm/boot/dts/kirkwood-ts219-6281.dts b/arch/arm/boot/dts/kirkwood-ts219-6281.dts index c17ae45e19be..9767d73f3857 100644 --- a/arch/arm/boot/dts/kirkwood-ts219-6281.dts +++ b/arch/arm/boot/dts/kirkwood-ts219-6281.dts @@ -6,7 +6,7 @@ / { ocp@f1000000 { - pinctrl: pinctrl@10000 { + pinctrl: pin-controller@10000 { pinctrl-0 = <&pmx_ram_size &pmx_board_id>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/kirkwood-ts219-6282.dts b/arch/arm/boot/dts/kirkwood-ts219-6282.dts index 0713d072758a..bfc1a32d4e42 100644 --- a/arch/arm/boot/dts/kirkwood-ts219-6282.dts +++ b/arch/arm/boot/dts/kirkwood-ts219-6282.dts @@ -16,7 +16,7 @@ }; ocp@f1000000 { - pinctrl: pinctrl@10000 { + pinctrl: pin-controller@10000 { pinctrl-0 = <&pmx_ram_size &pmx_board_id>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/kirkwood-ts219.dtsi b/arch/arm/boot/dts/kirkwood-ts219.dtsi index 911f3a8cee23..df7f15276575 100644 --- a/arch/arm/boot/dts/kirkwood-ts219.dtsi +++ b/arch/arm/boot/dts/kirkwood-ts219.dtsi @@ -9,6 +9,7 @@ chosen { bootargs = "console=ttyS0,115200n8"; + stdout-path = &uart0; }; mbus { @@ -25,8 +26,6 @@ i2c@11000 { status = "okay"; clock-frequency = <400000>; - pinctrl-0 = <&pmx_twsi0>; - pinctrl-names = "default"; s35390a: s35390a@30 { compatible = "s35390a"; @@ -34,16 +33,10 @@ }; }; serial@12000 { - clock-frequency = <200000000>; status = "okay"; - pinctrl-0 = <&pmx_uart0>; - pinctrl-names = "default"; }; serial@12100 { - clock-frequency = <200000000>; status = "okay"; - pinctrl-0 = <&pmx_uart1>; - pinctrl-names = "default"; }; poweroff@12100 { compatible = "qnap,power-off"; @@ -52,8 +45,6 @@ }; spi@10600 { status = "okay"; - pinctrl-0 = <&pmx_spi>; - pinctrl-names = "default"; m25p128@0 { #address-cells = <1>; diff --git a/arch/arm/boot/dts/kirkwood-ts419.dtsi b/arch/arm/boot/dts/kirkwood-ts419.dtsi index 1a9c624c7a92..30ab93bfb1e4 100644 --- a/arch/arm/boot/dts/kirkwood-ts419.dtsi +++ b/arch/arm/boot/dts/kirkwood-ts419.dtsi @@ -14,7 +14,7 @@ compatible = "qnap,ts419", "marvell,kirkwood"; ocp@f1000000 { - pinctrl: pinctrl@10000 { + pinctrl: pin-controller@10000 { pinctrl-names = "default"; pmx_USB_copy_button: pmx-USB-copy-button { diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi index 90384587c278..afc640cd80c5 100644 --- a/arch/arm/boot/dts/kirkwood.dtsi +++ b/arch/arm/boot/dts/kirkwood.dtsi @@ -40,7 +40,7 @@ pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256 MiB memory space */ pcie-io-aperture = <0xf2000000 0x100000>; /* 1 MiB I/O space */ - crypto@0301 { + cesa: crypto@0301 { compatible = "marvell,orion-crypto"; reg = <MBUS_ID(0xf0, 0x01) 0x30000 0x10000>, <MBUS_ID(0x03, 0x01) 0 0x800>; @@ -61,6 +61,8 @@ chip-delay = <25>; /* set partition map and/or chip-delay in board dts */ clocks = <&gate_clk 7>; + pinctrl-0 = <&pmx_nand>; + pinctrl-names = "default"; status = "disabled"; }; }; @@ -71,13 +73,59 @@ #address-cells = <1>; #size-cells = <1>; + pinctrl: pin-controller@10000 { + /* set compatible property in SoC file */ + reg = <0x10000 0x20>; + + pmx_ge1: pmx-ge1 { + marvell,pins = "mpp20", "mpp21", "mpp22", "mpp23", + "mpp24", "mpp25", "mpp26", "mpp27", + "mpp30", "mpp31", "mpp32", "mpp33"; + marvell,function = "ge1"; + }; + + pmx_nand: pmx-nand { + marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3", + "mpp4", "mpp5", "mpp18", "mpp19"; + marvell,function = "nand"; + }; + + /* + * Default SPI0 pinctrl setting with CSn on mpp0, + * overwrite marvell,pins on board level if required. + */ + pmx_spi: pmx-spi { + marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3"; + marvell,function = "spi"; + }; + + pmx_twsi0: pmx-twsi0 { + marvell,pins = "mpp8", "mpp9"; + marvell,function = "twsi0"; + }; + + /* + * Default UART pinctrl setting without RTS/CTS, + * overwrite marvell,pins on board level if required. + */ + pmx_uart0: pmx-uart0 { + marvell,pins = "mpp10", "mpp11"; + marvell,function = "uart0"; + }; + + pmx_uart1: pmx-uart1 { + marvell,pins = "mpp13", "mpp14"; + marvell,function = "uart1"; + }; + }; + core_clk: core-clocks@10030 { compatible = "marvell,kirkwood-core-clock"; reg = <0x10030 0x4>; #clock-cells = <1>; }; - spi@10600 { + spi0: spi@10600 { compatible = "marvell,orion-spi"; #address-cells = <1>; #size-cells = <0>; @@ -85,6 +133,8 @@ interrupts = <23>; reg = <0x10600 0x28>; clocks = <&gate_clk 7>; + pinctrl-0 = <&pmx_spi>; + pinctrl-names = "default"; status = "disabled"; }; @@ -120,24 +170,30 @@ interrupts = <29>; clock-frequency = <100000>; clocks = <&gate_clk 7>; + pinctrl-0 = <&pmx_twsi0>; + pinctrl-names = "default"; status = "disabled"; }; - serial@12000 { + uart0: serial@12000 { compatible = "ns16550a"; reg = <0x12000 0x100>; reg-shift = <2>; interrupts = <33>; clocks = <&gate_clk 7>; + pinctrl-0 = <&pmx_uart0>; + pinctrl-names = "default"; status = "disabled"; }; - serial@12100 { + uart1: serial@12100 { compatible = "ns16550a"; reg = <0x12100 0x100>; reg-shift = <2>; interrupts = <34>; clocks = <&gate_clk 7>; + pinctrl-0 = <&pmx_uart1>; + pinctrl-names = "default"; status = "disabled"; }; @@ -146,7 +202,7 @@ reg = <0x20000 0x80>, <0x1500 0x20>; }; - system-controller@20000 { + sysc: system-controller@20000 { compatible = "marvell,orion-system-controller"; reg = <0x20000 0x120>; }; @@ -196,7 +252,7 @@ status = "okay"; }; - ehci@50000 { + usb0: ehci@50000 { compatible = "marvell,orion-ehci"; reg = <0x50000 0x1000>; interrupts = <19>; @@ -204,7 +260,7 @@ status = "okay"; }; - xor@60800 { + dma0: xor@60800 { compatible = "marvell,orion-xor"; reg = <0x60800 0x100 0x60A00 0x100>; @@ -224,7 +280,7 @@ }; }; - xor@60900 { + dma1: xor@60900 { compatible = "marvell,orion-xor"; reg = <0x60900 0x100 0x60B00 0x100>; @@ -282,6 +338,8 @@ reg = <0x76000 0x4000>; clocks = <&gate_clk 19>; marvell,tx-checksum-limit = <1600>; + pinctrl-0 = <&pmx_ge1>; + pinctrl-names = "default"; status = "disabled"; ethernet1-port@0 { @@ -314,6 +372,7 @@ audio0: audio-controller@a0000 { compatible = "marvell,kirkwood-audio"; + #sound-dai-cells = <0>; reg = <0xa0000 0x2210>; interrupts = <24>; clocks = <&gate_clk 9>; diff --git a/arch/arm/boot/dts/marco.dtsi b/arch/arm/boot/dts/marco.dtsi index 0c9647d28765..fb354225740a 100644 --- a/arch/arm/boot/dts/marco.dtsi +++ b/arch/arm/boot/dts/marco.dtsi @@ -36,7 +36,7 @@ ranges = <0x40000000 0x40000000 0xa0000000>; l2-cache-controller@c0030000 { - compatible = "sirf,marco-pl310-cache", "arm,pl310-cache"; + compatible = "arm,pl310-cache"; reg = <0xc0030000 0x1000>; interrupts = <0 59 0>; arm,tag-latency = <1 1 1>; diff --git a/arch/arm/boot/dts/omap2420-clocks.dtsi b/arch/arm/boot/dts/omap2420-clocks.dtsi new file mode 100644 index 000000000000..ce8c742d7e92 --- /dev/null +++ b/arch/arm/boot/dts/omap2420-clocks.dtsi @@ -0,0 +1,270 @@ +/* + * Device Tree Source for OMAP2420 clock data + * + * Copyright (C) 2014 Texas Instruments, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +&prcm_clocks { + sys_clkout2_src_gate: sys_clkout2_src_gate { + #clock-cells = <0>; + compatible = "ti,composite-no-wait-gate-clock"; + clocks = <&core_ck>; + ti,bit-shift = <15>; + reg = <0x0070>; + }; + + sys_clkout2_src_mux: sys_clkout2_src_mux { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&core_ck>, <&sys_ck>, <&func_96m_ck>, <&func_54m_ck>; + ti,bit-shift = <8>; + reg = <0x0070>; + }; + + sys_clkout2_src: sys_clkout2_src { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&sys_clkout2_src_gate>, <&sys_clkout2_src_mux>; + }; + + sys_clkout2: sys_clkout2 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&sys_clkout2_src>; + ti,bit-shift = <11>; + ti,max-div = <64>; + reg = <0x0070>; + ti,index-power-of-two; + }; + + dsp_gate_ick: dsp_gate_ick { + #clock-cells = <0>; + compatible = "ti,composite-interface-clock"; + clocks = <&dsp_fck>; + ti,bit-shift = <1>; + reg = <0x0810>; + }; + + dsp_div_ick: dsp_div_ick { + #clock-cells = <0>; + compatible = "ti,composite-divider-clock"; + clocks = <&dsp_fck>; + ti,bit-shift = <5>; + ti,max-div = <3>; + reg = <0x0840>; + ti,index-starts-at-one; + }; + + dsp_ick: dsp_ick { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&dsp_gate_ick>, <&dsp_div_ick>; + }; + + iva1_gate_ifck: iva1_gate_ifck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clocks = <&core_ck>; + ti,bit-shift = <10>; + reg = <0x0800>; + }; + + iva1_div_ifck: iva1_div_ifck { + #clock-cells = <0>; + compatible = "ti,composite-divider-clock"; + clocks = <&core_ck>; + ti,bit-shift = <8>; + reg = <0x0840>; + ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>, <0>, <0>, <0>, <12>; + }; + + iva1_ifck: iva1_ifck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&iva1_gate_ifck>, <&iva1_div_ifck>; + }; + + iva1_ifck_div: iva1_ifck_div { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&iva1_ifck>; + clock-mult = <1>; + clock-div = <2>; + }; + + iva1_mpu_int_ifck: iva1_mpu_int_ifck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&iva1_ifck_div>; + ti,bit-shift = <8>; + reg = <0x0800>; + }; + + wdt3_ick: wdt3_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&l4_ck>; + ti,bit-shift = <28>; + reg = <0x0210>; + }; + + wdt3_fck: wdt3_fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&func_32k_ck>; + ti,bit-shift = <28>; + reg = <0x0200>; + }; + + mmc_ick: mmc_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&l4_ck>; + ti,bit-shift = <26>; + reg = <0x0210>; + }; + + mmc_fck: mmc_fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&func_96m_ck>; + ti,bit-shift = <26>; + reg = <0x0200>; + }; + + eac_ick: eac_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&l4_ck>; + ti,bit-shift = <24>; + reg = <0x0210>; + }; + + eac_fck: eac_fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&func_96m_ck>; + ti,bit-shift = <24>; + reg = <0x0200>; + }; + + i2c1_fck: i2c1_fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&func_12m_ck>; + ti,bit-shift = <19>; + reg = <0x0200>; + }; + + i2c2_fck: i2c2_fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&func_12m_ck>; + ti,bit-shift = <20>; + reg = <0x0200>; + }; + + vlynq_ick: vlynq_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&core_l3_ck>; + ti,bit-shift = <3>; + reg = <0x0210>; + }; + + vlynq_gate_fck: vlynq_gate_fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clocks = <&core_ck>; + ti,bit-shift = <3>; + reg = <0x0200>; + }; + + core_d18_ck: core_d18_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&core_ck>; + clock-mult = <1>; + clock-div = <18>; + }; + + vlynq_mux_fck: vlynq_mux_fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&func_96m_ck>, <&core_ck>, <&core_d2_ck>, <&core_d3_ck>, <&core_d4_ck>, <&dummy_ck>, <&core_d6_ck>, <&dummy_ck>, <&core_d8_ck>, <&core_d9_ck>, <&dummy_ck>, <&dummy_ck>, <&core_d12_ck>, <&dummy_ck>, <&dummy_ck>, <&dummy_ck>, <&core_d16_ck>, <&dummy_ck>, <&core_d18_ck>; + ti,bit-shift = <15>; + reg = <0x0240>; + }; + + vlynq_fck: vlynq_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&vlynq_gate_fck>, <&vlynq_mux_fck>; + }; +}; + +&prcm_clockdomains { + gfx_clkdm: gfx_clkdm { + compatible = "ti,clockdomain"; + clocks = <&gfx_ick>; + }; + + core_l3_clkdm: core_l3_clkdm { + compatible = "ti,clockdomain"; + clocks = <&cam_fck>, <&vlynq_ick>, <&usb_fck>; + }; + + wkup_clkdm: wkup_clkdm { + compatible = "ti,clockdomain"; + clocks = <&dpll_ck>, <&emul_ck>, <&gpt1_ick>, <&gpios_ick>, + <&gpios_fck>, <&mpu_wdt_ick>, <&mpu_wdt_fck>, + <&sync_32k_ick>, <&wdt1_ick>, <&omapctrl_ick>; + }; + + iva1_clkdm: iva1_clkdm { + compatible = "ti,clockdomain"; + clocks = <&iva1_mpu_int_ifck>; + }; + + dss_clkdm: dss_clkdm { + compatible = "ti,clockdomain"; + clocks = <&dss_ick>, <&dss_54m_fck>; + }; + + core_l4_clkdm: core_l4_clkdm { + compatible = "ti,clockdomain"; + clocks = <&ssi_l4_ick>, <&gpt2_ick>, <&gpt3_ick>, <&gpt4_ick>, + <&gpt5_ick>, <&gpt6_ick>, <&gpt7_ick>, <&gpt8_ick>, + <&gpt9_ick>, <&gpt10_ick>, <&gpt11_ick>, <&gpt12_ick>, + <&mcbsp1_ick>, <&mcbsp2_ick>, <&mcspi1_ick>, + <&mcspi1_fck>, <&mcspi2_ick>, <&mcspi2_fck>, + <&uart1_ick>, <&uart1_fck>, <&uart2_ick>, <&uart2_fck>, + <&uart3_ick>, <&uart3_fck>, <&cam_ick>, + <&mailboxes_ick>, <&wdt4_ick>, <&wdt4_fck>, + <&wdt3_ick>, <&wdt3_fck>, <&mspro_ick>, <&mspro_fck>, + <&mmc_ick>, <&mmc_fck>, <&fac_ick>, <&fac_fck>, + <&eac_ick>, <&eac_fck>, <&hdq_ick>, <&hdq_fck>, + <&i2c1_ick>, <&i2c1_fck>, <&i2c2_ick>, <&i2c2_fck>, + <&des_ick>, <&sha_ick>, <&rng_ick>, <&aes_ick>, + <&pka_ick>; + }; +}; + +&func_96m_ck { + compatible = "fixed-factor-clock"; + clocks = <&apll96_ck>; + clock-mult = <1>; + clock-div = <1>; +}; + +&dsp_div_fck { + ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>, <0>, <0>, <0>, <12>; +}; + +&ssi_ssr_sst_div_fck { + ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>; +}; diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi index 2d9979835f24..e83b0468080c 100644 --- a/arch/arm/boot/dts/omap2420.dtsi +++ b/arch/arm/boot/dts/omap2420.dtsi @@ -14,6 +14,32 @@ compatible = "ti,omap2420", "ti,omap2"; ocp { + prcm: prcm@48008000 { + compatible = "ti,omap2-prcm"; + reg = <0x48008000 0x1000>; + + prcm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + prcm_clockdomains: clockdomains { + }; + }; + + scrm: scrm@48000000 { + compatible = "ti,omap2-scrm"; + reg = <0x48000000 0x1000>; + + scrm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + scrm_clockdomains: clockdomains { + }; + }; + counter32k: counter@48004000 { compatible = "ti,omap-counter32k"; reg = <0x48004000 0x20>; diff --git a/arch/arm/boot/dts/omap2430-clocks.dtsi b/arch/arm/boot/dts/omap2430-clocks.dtsi new file mode 100644 index 000000000000..805f75df1cf2 --- /dev/null +++ b/arch/arm/boot/dts/omap2430-clocks.dtsi @@ -0,0 +1,344 @@ +/* + * Device Tree Source for OMAP2430 clock data + * + * Copyright (C) 2014 Texas Instruments, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +&scrm_clocks { + mcbsp3_mux_fck: mcbsp3_mux_fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&func_96m_ck>, <&mcbsp_clks>; + reg = <0x02e8>; + }; + + mcbsp3_fck: mcbsp3_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&mcbsp3_gate_fck>, <&mcbsp3_mux_fck>; + }; + + mcbsp4_mux_fck: mcbsp4_mux_fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&func_96m_ck>, <&mcbsp_clks>; + ti,bit-shift = <2>; + reg = <0x02e8>; + }; + + mcbsp4_fck: mcbsp4_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&mcbsp4_gate_fck>, <&mcbsp4_mux_fck>; + }; + + mcbsp5_mux_fck: mcbsp5_mux_fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&func_96m_ck>, <&mcbsp_clks>; + ti,bit-shift = <4>; + reg = <0x02e8>; + }; + + mcbsp5_fck: mcbsp5_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&mcbsp5_gate_fck>, <&mcbsp5_mux_fck>; + }; +}; + +&prcm_clocks { + iva2_1_gate_ick: iva2_1_gate_ick { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clocks = <&dsp_fck>; + ti,bit-shift = <0>; + reg = <0x0800>; + }; + + iva2_1_div_ick: iva2_1_div_ick { + #clock-cells = <0>; + compatible = "ti,composite-divider-clock"; + clocks = <&dsp_fck>; + ti,bit-shift = <5>; + ti,max-div = <3>; + reg = <0x0840>; + ti,index-starts-at-one; + }; + + iva2_1_ick: iva2_1_ick { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&iva2_1_gate_ick>, <&iva2_1_div_ick>; + }; + + mdm_gate_ick: mdm_gate_ick { + #clock-cells = <0>; + compatible = "ti,composite-interface-clock"; + clocks = <&core_ck>; + ti,bit-shift = <0>; + reg = <0x0c10>; + }; + + mdm_div_ick: mdm_div_ick { + #clock-cells = <0>; + compatible = "ti,composite-divider-clock"; + clocks = <&core_ck>; + reg = <0x0c40>; + ti,dividers = <0>, <1>, <0>, <0>, <4>, <0>, <6>, <0>, <0>, <9>; + }; + + mdm_ick: mdm_ick { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&mdm_gate_ick>, <&mdm_div_ick>; + }; + + mdm_osc_ck: mdm_osc_ck { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&osc_ck>; + ti,bit-shift = <1>; + reg = <0x0c00>; + }; + + mcbsp3_ick: mcbsp3_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&l4_ck>; + ti,bit-shift = <3>; + reg = <0x0214>; + }; + + mcbsp3_gate_fck: mcbsp3_gate_fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clocks = <&mcbsp_clks>; + ti,bit-shift = <3>; + reg = <0x0204>; + }; + + mcbsp4_ick: mcbsp4_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&l4_ck>; + ti,bit-shift = <4>; + reg = <0x0214>; + }; + + mcbsp4_gate_fck: mcbsp4_gate_fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clocks = <&mcbsp_clks>; + ti,bit-shift = <4>; + reg = <0x0204>; + }; + + mcbsp5_ick: mcbsp5_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&l4_ck>; + ti,bit-shift = <5>; + reg = <0x0214>; + }; + + mcbsp5_gate_fck: mcbsp5_gate_fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clocks = <&mcbsp_clks>; + ti,bit-shift = <5>; + reg = <0x0204>; + }; + + mcspi3_ick: mcspi3_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&l4_ck>; + ti,bit-shift = <9>; + reg = <0x0214>; + }; + + mcspi3_fck: mcspi3_fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&func_48m_ck>; + ti,bit-shift = <9>; + reg = <0x0204>; + }; + + icr_ick: icr_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&sys_ck>; + ti,bit-shift = <6>; + reg = <0x0410>; + }; + + i2chs1_fck: i2chs1_fck { + #clock-cells = <0>; + compatible = "ti,omap2430-interface-clock"; + clocks = <&func_96m_ck>; + ti,bit-shift = <19>; + reg = <0x0204>; + }; + + i2chs2_fck: i2chs2_fck { + #clock-cells = <0>; + compatible = "ti,omap2430-interface-clock"; + clocks = <&func_96m_ck>; + ti,bit-shift = <20>; + reg = <0x0204>; + }; + + usbhs_ick: usbhs_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&core_l3_ck>; + ti,bit-shift = <6>; + reg = <0x0214>; + }; + + mmchs1_ick: mmchs1_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&l4_ck>; + ti,bit-shift = <7>; + reg = <0x0214>; + }; + + mmchs1_fck: mmchs1_fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&func_96m_ck>; + ti,bit-shift = <7>; + reg = <0x0204>; + }; + + mmchs2_ick: mmchs2_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&l4_ck>; + ti,bit-shift = <8>; + reg = <0x0214>; + }; + + mmchs2_fck: mmchs2_fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&func_96m_ck>; + ti,bit-shift = <8>; + reg = <0x0204>; + }; + + gpio5_ick: gpio5_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&l4_ck>; + ti,bit-shift = <10>; + reg = <0x0214>; + }; + + gpio5_fck: gpio5_fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&func_32k_ck>; + ti,bit-shift = <10>; + reg = <0x0204>; + }; + + mdm_intc_ick: mdm_intc_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&l4_ck>; + ti,bit-shift = <11>; + reg = <0x0214>; + }; + + mmchsdb1_fck: mmchsdb1_fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&func_32k_ck>; + ti,bit-shift = <16>; + reg = <0x0204>; + }; + + mmchsdb2_fck: mmchsdb2_fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&func_32k_ck>; + ti,bit-shift = <17>; + reg = <0x0204>; + }; +}; + +&prcm_clockdomains { + gfx_clkdm: gfx_clkdm { + compatible = "ti,clockdomain"; + clocks = <&gfx_ick>; + }; + + core_l3_clkdm: core_l3_clkdm { + compatible = "ti,clockdomain"; + clocks = <&cam_fck>, <&usb_fck>, <&usbhs_ick>; + }; + + wkup_clkdm: wkup_clkdm { + compatible = "ti,clockdomain"; + clocks = <&dpll_ck>, <&emul_ck>, <&gpt1_ick>, <&gpios_ick>, + <&gpios_fck>, <&mpu_wdt_ick>, <&mpu_wdt_fck>, + <&sync_32k_ick>, <&wdt1_ick>, <&omapctrl_ick>, + <&icr_ick>; + }; + + dss_clkdm: dss_clkdm { + compatible = "ti,clockdomain"; + clocks = <&dss_ick>, <&dss_54m_fck>; + }; + + core_l4_clkdm: core_l4_clkdm { + compatible = "ti,clockdomain"; + clocks = <&ssi_l4_ick>, <&gpt2_ick>, <&gpt3_ick>, <&gpt4_ick>, + <&gpt5_ick>, <&gpt6_ick>, <&gpt7_ick>, <&gpt8_ick>, + <&gpt9_ick>, <&gpt10_ick>, <&gpt11_ick>, <&gpt12_ick>, + <&mcbsp1_ick>, <&mcbsp2_ick>, <&mcbsp3_ick>, + <&mcbsp4_ick>, <&mcbsp5_ick>, <&mcspi1_ick>, + <&mcspi1_fck>, <&mcspi2_ick>, <&mcspi2_fck>, + <&mcspi3_ick>, <&mcspi3_fck>, <&uart1_ick>, + <&uart1_fck>, <&uart2_ick>, <&uart2_fck>, <&uart3_ick>, + <&uart3_fck>, <&cam_ick>, <&mailboxes_ick>, + <&wdt4_ick>, <&wdt4_fck>, <&mspro_ick>, <&mspro_fck>, + <&fac_ick>, <&fac_fck>, <&hdq_ick>, <&hdq_fck>, + <&i2c1_ick>, <&i2chs1_fck>, <&i2c2_ick>, <&i2chs2_fck>, + <&des_ick>, <&sha_ick>, <&rng_ick>, <&aes_ick>, + <&pka_ick>, <&mmchs1_ick>, <&mmchs1_fck>, + <&mmchs2_ick>, <&mmchs2_fck>, <&gpio5_ick>, + <&gpio5_fck>, <&mdm_intc_ick>, <&mmchsdb1_fck>, + <&mmchsdb2_fck>; + }; + + mdm_clkdm: mdm_clkdm { + compatible = "ti,clockdomain"; + clocks = <&mdm_osc_ck>; + }; +}; + +&func_96m_ck { + compatible = "ti,mux-clock"; + clocks = <&apll96_ck>, <&alt_ck>; + ti,bit-shift = <4>; + reg = <0x0540>; +}; + +&dsp_div_fck { + ti,max-div = <4>; + ti,index-starts-at-one; +}; + +&ssi_ssr_sst_div_fck { + ti,max-div = <5>; + ti,index-starts-at-one; +}; diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi index 42d2c61c9e2d..c4e8013801ee 100644 --- a/arch/arm/boot/dts/omap2430.dtsi +++ b/arch/arm/boot/dts/omap2430.dtsi @@ -14,6 +14,32 @@ compatible = "ti,omap2430", "ti,omap2"; ocp { + prcm: prcm@49006000 { + compatible = "ti,omap2-prcm"; + reg = <0x49006000 0x1000>; + + prcm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + prcm_clockdomains: clockdomains { + }; + }; + + scrm: scrm@49002000 { + compatible = "ti,omap2-scrm"; + reg = <0x49002000 0x1000>; + + scrm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + scrm_clockdomains: clockdomains { + }; + }; + counter32k: counter@49020000 { compatible = "ti,omap-counter32k"; reg = <0x49020000 0x20>; diff --git a/arch/arm/boot/dts/omap24xx-clocks.dtsi b/arch/arm/boot/dts/omap24xx-clocks.dtsi new file mode 100644 index 000000000000..a1365ca926eb --- /dev/null +++ b/arch/arm/boot/dts/omap24xx-clocks.dtsi @@ -0,0 +1,1244 @@ +/* + * Device Tree Source for OMAP24xx clock data + * + * Copyright (C) 2014 Texas Instruments, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +&scrm_clocks { + mcbsp1_mux_fck: mcbsp1_mux_fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&func_96m_ck>, <&mcbsp_clks>; + ti,bit-shift = <2>; + reg = <0x0274>; + }; + + mcbsp1_fck: mcbsp1_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&mcbsp1_gate_fck>, <&mcbsp1_mux_fck>; + }; + + mcbsp2_mux_fck: mcbsp2_mux_fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&func_96m_ck>, <&mcbsp_clks>; + ti,bit-shift = <6>; + reg = <0x0274>; + }; + + mcbsp2_fck: mcbsp2_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&mcbsp2_gate_fck>, <&mcbsp2_mux_fck>; + }; +}; + +&prcm_clocks { + func_32k_ck: func_32k_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + + secure_32k_ck: secure_32k_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + + virt_12m_ck: virt_12m_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <12000000>; + }; + + virt_13m_ck: virt_13m_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <13000000>; + }; + + virt_19200000_ck: virt_19200000_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <19200000>; + }; + + virt_26m_ck: virt_26m_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <26000000>; + }; + + aplls_clkin_ck: aplls_clkin_ck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&virt_19200000_ck>, <&virt_26m_ck>, <&virt_13m_ck>, <&virt_12m_ck>; + ti,bit-shift = <23>; + reg = <0x0540>; + }; + + aplls_clkin_x2_ck: aplls_clkin_x2_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&aplls_clkin_ck>; + clock-mult = <2>; + clock-div = <1>; + }; + + osc_ck: osc_ck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&aplls_clkin_ck>, <&aplls_clkin_x2_ck>; + ti,bit-shift = <6>; + reg = <0x0060>; + ti,index-starts-at-one; + }; + + sys_ck: sys_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&osc_ck>; + ti,bit-shift = <6>; + ti,max-div = <3>; + reg = <0x0060>; + ti,index-starts-at-one; + }; + + alt_ck: alt_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <54000000>; + }; + + mcbsp_clks: mcbsp_clks { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0x0>; + }; + + dpll_ck: dpll_ck { + #clock-cells = <0>; + compatible = "ti,omap2-dpll-core-clock"; + clocks = <&sys_ck>, <&sys_ck>; + reg = <0x0500>, <0x0540>; + }; + + apll96_ck: apll96_ck { + #clock-cells = <0>; + compatible = "ti,omap2-apll-clock"; + clocks = <&sys_ck>; + ti,bit-shift = <2>; + ti,idlest-shift = <8>; + ti,clock-frequency = <96000000>; + reg = <0x0500>, <0x0530>, <0x0520>; + }; + + apll54_ck: apll54_ck { + #clock-cells = <0>; + compatible = "ti,omap2-apll-clock"; + clocks = <&sys_ck>; + ti,bit-shift = <6>; + ti,idlest-shift = <9>; + ti,clock-frequency = <54000000>; + reg = <0x0500>, <0x0530>, <0x0520>; + }; + + func_54m_ck: func_54m_ck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&apll54_ck>, <&alt_ck>; + ti,bit-shift = <5>; + reg = <0x0540>; + }; + + core_ck: core_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + func_96m_ck: func_96m_ck { + #clock-cells = <0>; + }; + + apll96_d2_ck: apll96_d2_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&apll96_ck>; + clock-mult = <1>; + clock-div = <2>; + }; + + func_48m_ck: func_48m_ck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&apll96_d2_ck>, <&alt_ck>; + ti,bit-shift = <3>; + reg = <0x0540>; + }; + + func_12m_ck: func_12m_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&func_48m_ck>; + clock-mult = <1>; + clock-div = <4>; + }; + + sys_clkout_src_gate: sys_clkout_src_gate { + #clock-cells = <0>; + compatible = "ti,composite-no-wait-gate-clock"; + clocks = <&core_ck>; + ti,bit-shift = <7>; + reg = <0x0070>; + }; + + sys_clkout_src_mux: sys_clkout_src_mux { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&core_ck>, <&sys_ck>, <&func_96m_ck>, <&func_54m_ck>; + reg = <0x0070>; + }; + + sys_clkout_src: sys_clkout_src { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&sys_clkout_src_gate>, <&sys_clkout_src_mux>; + }; + + sys_clkout: sys_clkout { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&sys_clkout_src>; + ti,bit-shift = <3>; + ti,max-div = <64>; + reg = <0x0070>; + ti,index-power-of-two; + }; + + emul_ck: emul_ck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&func_54m_ck>; + ti,bit-shift = <0>; + reg = <0x0078>; + }; + + mpu_ck: mpu_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&core_ck>; + ti,max-div = <31>; + reg = <0x0140>; + ti,index-starts-at-one; + }; + + dsp_gate_fck: dsp_gate_fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clocks = <&core_ck>; + ti,bit-shift = <0>; + reg = <0x0800>; + }; + + dsp_div_fck: dsp_div_fck { + #clock-cells = <0>; + compatible = "ti,composite-divider-clock"; + clocks = <&core_ck>; + reg = <0x0840>; + }; + + dsp_fck: dsp_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&dsp_gate_fck>, <&dsp_div_fck>; + }; + + core_l3_ck: core_l3_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&core_ck>; + ti,max-div = <31>; + reg = <0x0240>; + ti,index-starts-at-one; + }; + + gfx_3d_gate_fck: gfx_3d_gate_fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clocks = <&core_l3_ck>; + ti,bit-shift = <2>; + reg = <0x0300>; + }; + + gfx_3d_div_fck: gfx_3d_div_fck { + #clock-cells = <0>; + compatible = "ti,composite-divider-clock"; + clocks = <&core_l3_ck>; + ti,max-div = <4>; + reg = <0x0340>; + ti,index-starts-at-one; + }; + + gfx_3d_fck: gfx_3d_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&gfx_3d_gate_fck>, <&gfx_3d_div_fck>; + }; + + gfx_2d_gate_fck: gfx_2d_gate_fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clocks = <&core_l3_ck>; + ti,bit-shift = <1>; + reg = <0x0300>; + }; + + gfx_2d_div_fck: gfx_2d_div_fck { + #clock-cells = <0>; + compatible = "ti,composite-divider-clock"; + clocks = <&core_l3_ck>; + ti,max-div = <4>; + reg = <0x0340>; + ti,index-starts-at-one; + }; + + gfx_2d_fck: gfx_2d_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&gfx_2d_gate_fck>, <&gfx_2d_div_fck>; + }; + + gfx_ick: gfx_ick { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&core_l3_ck>; + ti,bit-shift = <0>; + reg = <0x0310>; + }; + + l4_ck: l4_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&core_l3_ck>; + ti,bit-shift = <5>; + ti,max-div = <3>; + reg = <0x0240>; + ti,index-starts-at-one; + }; + + dss_ick: dss_ick { + #clock-cells = <0>; + compatible = "ti,omap3-no-wait-interface-clock"; + clocks = <&l4_ck>; + ti,bit-shift = <0>; + reg = <0x0210>; + }; + + dss1_gate_fck: dss1_gate_fck { + #clock-cells = <0>; + compatible = "ti,composite-no-wait-gate-clock"; + clocks = <&core_ck>; + ti,bit-shift = <0>; + reg = <0x0200>; + }; + + core_d2_ck: core_d2_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&core_ck>; + clock-mult = <1>; + clock-div = <2>; + }; + + core_d3_ck: core_d3_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&core_ck>; + clock-mult = <1>; + clock-div = <3>; + }; + + core_d4_ck: core_d4_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&core_ck>; + clock-mult = <1>; + clock-div = <4>; + }; + + core_d5_ck: core_d5_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&core_ck>; + clock-mult = <1>; + clock-div = <5>; + }; + + core_d6_ck: core_d6_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&core_ck>; + clock-mult = <1>; + clock-div = <6>; + }; + + dummy_ck: dummy_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + core_d8_ck: core_d8_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&core_ck>; + clock-mult = <1>; + clock-div = <8>; + }; + + core_d9_ck: core_d9_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&core_ck>; + clock-mult = <1>; + clock-div = <9>; + }; + + core_d12_ck: core_d12_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&core_ck>; + clock-mult = <1>; + clock-div = <12>; + }; + + core_d16_ck: core_d16_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&core_ck>; + clock-mult = <1>; + clock-div = <16>; + }; + + dss1_mux_fck: dss1_mux_fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&sys_ck>, <&core_ck>, <&core_d2_ck>, <&core_d3_ck>, <&core_d4_ck>, <&core_d5_ck>, <&core_d6_ck>, <&core_d8_ck>, <&core_d9_ck>, <&core_d12_ck>, <&core_d16_ck>; + ti,bit-shift = <8>; + reg = <0x0240>; + }; + + dss1_fck: dss1_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&dss1_gate_fck>, <&dss1_mux_fck>; + }; + + dss2_gate_fck: dss2_gate_fck { + #clock-cells = <0>; + compatible = "ti,composite-no-wait-gate-clock"; + clocks = <&func_48m_ck>; + ti,bit-shift = <1>; + reg = <0x0200>; + }; + + dss2_mux_fck: dss2_mux_fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&sys_ck>, <&func_48m_ck>; + ti,bit-shift = <13>; + reg = <0x0240>; + }; + + dss2_fck: dss2_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&dss2_gate_fck>, <&dss2_mux_fck>; + }; + + dss_54m_fck: dss_54m_fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&func_54m_ck>; + ti,bit-shift = <2>; + reg = <0x0200>; + }; + + ssi_ssr_sst_gate_fck: ssi_ssr_sst_gate_fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clocks = <&core_ck>; + ti,bit-shift = <1>; + reg = <0x0204>; + }; + + ssi_ssr_sst_div_fck: ssi_ssr_sst_div_fck { + #clock-cells = <0>; + compatible = "ti,composite-divider-clock"; + clocks = <&core_ck>; + ti,bit-shift = <20>; + reg = <0x0240>; + }; + + ssi_ssr_sst_fck: ssi_ssr_sst_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&ssi_ssr_sst_gate_fck>, <&ssi_ssr_sst_div_fck>; + }; + + usb_l4_gate_ick: usb_l4_gate_ick { + #clock-cells = <0>; + compatible = "ti,composite-interface-clock"; + clocks = <&core_l3_ck>; + ti,bit-shift = <0>; + reg = <0x0214>; + }; + + usb_l4_div_ick: usb_l4_div_ick { + #clock-cells = <0>; + compatible = "ti,composite-divider-clock"; + clocks = <&core_l3_ck>; + ti,bit-shift = <25>; + reg = <0x0240>; + ti,dividers = <0>, <1>, <2>, <0>, <4>; + }; + + usb_l4_ick: usb_l4_ick { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&usb_l4_gate_ick>, <&usb_l4_div_ick>; + }; + + ssi_l4_ick: ssi_l4_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&l4_ck>; + ti,bit-shift = <1>; + reg = <0x0214>; + }; + + gpt1_ick: gpt1_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&sys_ck>; + ti,bit-shift = <0>; + reg = <0x0410>; + }; + + gpt1_gate_fck: gpt1_gate_fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clocks = <&func_32k_ck>; + ti,bit-shift = <0>; + reg = <0x0400>; + }; + + gpt1_mux_fck: gpt1_mux_fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; + reg = <0x0440>; + }; + + gpt1_fck: gpt1_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&gpt1_gate_fck>, <&gpt1_mux_fck>; + }; + + gpt2_ick: gpt2_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&l4_ck>; + ti,bit-shift = <4>; + reg = <0x0210>; + }; + + gpt2_gate_fck: gpt2_gate_fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clocks = <&func_32k_ck>; + ti,bit-shift = <4>; + reg = <0x0200>; + }; + + gpt2_mux_fck: gpt2_mux_fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; + ti,bit-shift = <2>; + reg = <0x0244>; + }; + + gpt2_fck: gpt2_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&gpt2_gate_fck>, <&gpt2_mux_fck>; + }; + + gpt3_ick: gpt3_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&l4_ck>; + ti,bit-shift = <5>; + reg = <0x0210>; + }; + + gpt3_gate_fck: gpt3_gate_fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clocks = <&func_32k_ck>; + ti,bit-shift = <5>; + reg = <0x0200>; + }; + + gpt3_mux_fck: gpt3_mux_fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; + ti,bit-shift = <4>; + reg = <0x0244>; + }; + + gpt3_fck: gpt3_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&gpt3_gate_fck>, <&gpt3_mux_fck>; + }; + + gpt4_ick: gpt4_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&l4_ck>; + ti,bit-shift = <6>; + reg = <0x0210>; + }; + + gpt4_gate_fck: gpt4_gate_fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clocks = <&func_32k_ck>; + ti,bit-shift = <6>; + reg = <0x0200>; + }; + + gpt4_mux_fck: gpt4_mux_fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; + ti,bit-shift = <6>; + reg = <0x0244>; + }; + + gpt4_fck: gpt4_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&gpt4_gate_fck>, <&gpt4_mux_fck>; + }; + + gpt5_ick: gpt5_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&l4_ck>; + ti,bit-shift = <7>; + reg = <0x0210>; + }; + + gpt5_gate_fck: gpt5_gate_fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clocks = <&func_32k_ck>; + ti,bit-shift = <7>; + reg = <0x0200>; + }; + + gpt5_mux_fck: gpt5_mux_fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; + ti,bit-shift = <8>; + reg = <0x0244>; + }; + + gpt5_fck: gpt5_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&gpt5_gate_fck>, <&gpt5_mux_fck>; + }; + + gpt6_ick: gpt6_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&l4_ck>; + ti,bit-shift = <8>; + reg = <0x0210>; + }; + + gpt6_gate_fck: gpt6_gate_fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clocks = <&func_32k_ck>; + ti,bit-shift = <8>; + reg = <0x0200>; + }; + + gpt6_mux_fck: gpt6_mux_fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; + ti,bit-shift = <10>; + reg = <0x0244>; + }; + + gpt6_fck: gpt6_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&gpt6_gate_fck>, <&gpt6_mux_fck>; + }; + + gpt7_ick: gpt7_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&l4_ck>; + ti,bit-shift = <9>; + reg = <0x0210>; + }; + + gpt7_gate_fck: gpt7_gate_fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clocks = <&func_32k_ck>; + ti,bit-shift = <9>; + reg = <0x0200>; + }; + + gpt7_mux_fck: gpt7_mux_fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; + ti,bit-shift = <12>; + reg = <0x0244>; + }; + + gpt7_fck: gpt7_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&gpt7_gate_fck>, <&gpt7_mux_fck>; + }; + + gpt8_ick: gpt8_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&l4_ck>; + ti,bit-shift = <10>; + reg = <0x0210>; + }; + + gpt8_gate_fck: gpt8_gate_fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clocks = <&func_32k_ck>; + ti,bit-shift = <10>; + reg = <0x0200>; + }; + + gpt8_mux_fck: gpt8_mux_fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; + ti,bit-shift = <14>; + reg = <0x0244>; + }; + + gpt8_fck: gpt8_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&gpt8_gate_fck>, <&gpt8_mux_fck>; + }; + + gpt9_ick: gpt9_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&l4_ck>; + ti,bit-shift = <11>; + reg = <0x0210>; + }; + + gpt9_gate_fck: gpt9_gate_fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clocks = <&func_32k_ck>; + ti,bit-shift = <11>; + reg = <0x0200>; + }; + + gpt9_mux_fck: gpt9_mux_fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; + ti,bit-shift = <16>; + reg = <0x0244>; + }; + + gpt9_fck: gpt9_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&gpt9_gate_fck>, <&gpt9_mux_fck>; + }; + + gpt10_ick: gpt10_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&l4_ck>; + ti,bit-shift = <12>; + reg = <0x0210>; + }; + + gpt10_gate_fck: gpt10_gate_fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clocks = <&func_32k_ck>; + ti,bit-shift = <12>; + reg = <0x0200>; + }; + + gpt10_mux_fck: gpt10_mux_fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; + ti,bit-shift = <18>; + reg = <0x0244>; + }; + + gpt10_fck: gpt10_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&gpt10_gate_fck>, <&gpt10_mux_fck>; + }; + + gpt11_ick: gpt11_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&l4_ck>; + ti,bit-shift = <13>; + reg = <0x0210>; + }; + + gpt11_gate_fck: gpt11_gate_fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clocks = <&func_32k_ck>; + ti,bit-shift = <13>; + reg = <0x0200>; + }; + + gpt11_mux_fck: gpt11_mux_fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; + ti,bit-shift = <20>; + reg = <0x0244>; + }; + + gpt11_fck: gpt11_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&gpt11_gate_fck>, <&gpt11_mux_fck>; + }; + + gpt12_ick: gpt12_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&l4_ck>; + ti,bit-shift = <14>; + reg = <0x0210>; + }; + + gpt12_gate_fck: gpt12_gate_fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clocks = <&func_32k_ck>; + ti,bit-shift = <14>; + reg = <0x0200>; + }; + + gpt12_mux_fck: gpt12_mux_fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; + ti,bit-shift = <22>; + reg = <0x0244>; + }; + + gpt12_fck: gpt12_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&gpt12_gate_fck>, <&gpt12_mux_fck>; + }; + + mcbsp1_ick: mcbsp1_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&l4_ck>; + ti,bit-shift = <15>; + reg = <0x0210>; + }; + + mcbsp1_gate_fck: mcbsp1_gate_fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clocks = <&mcbsp_clks>; + ti,bit-shift = <15>; + reg = <0x0200>; + }; + + mcbsp2_ick: mcbsp2_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&l4_ck>; + ti,bit-shift = <16>; + reg = <0x0210>; + }; + + mcbsp2_gate_fck: mcbsp2_gate_fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clocks = <&mcbsp_clks>; + ti,bit-shift = <16>; + reg = <0x0200>; + }; + + mcspi1_ick: mcspi1_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&l4_ck>; + ti,bit-shift = <17>; + reg = <0x0210>; + }; + + mcspi1_fck: mcspi1_fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&func_48m_ck>; + ti,bit-shift = <17>; + reg = <0x0200>; + }; + + mcspi2_ick: mcspi2_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&l4_ck>; + ti,bit-shift = <18>; + reg = <0x0210>; + }; + + mcspi2_fck: mcspi2_fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&func_48m_ck>; + ti,bit-shift = <18>; + reg = <0x0200>; + }; + + uart1_ick: uart1_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&l4_ck>; + ti,bit-shift = <21>; + reg = <0x0210>; + }; + + uart1_fck: uart1_fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&func_48m_ck>; + ti,bit-shift = <21>; + reg = <0x0200>; + }; + + uart2_ick: uart2_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&l4_ck>; + ti,bit-shift = <22>; + reg = <0x0210>; + }; + + uart2_fck: uart2_fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&func_48m_ck>; + ti,bit-shift = <22>; + reg = <0x0200>; + }; + + uart3_ick: uart3_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&l4_ck>; + ti,bit-shift = <2>; + reg = <0x0214>; + }; + + uart3_fck: uart3_fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&func_48m_ck>; + ti,bit-shift = <2>; + reg = <0x0204>; + }; + + gpios_ick: gpios_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&sys_ck>; + ti,bit-shift = <2>; + reg = <0x0410>; + }; + + gpios_fck: gpios_fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&func_32k_ck>; + ti,bit-shift = <2>; + reg = <0x0400>; + }; + + mpu_wdt_ick: mpu_wdt_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&sys_ck>; + ti,bit-shift = <3>; + reg = <0x0410>; + }; + + mpu_wdt_fck: mpu_wdt_fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&func_32k_ck>; + ti,bit-shift = <3>; + reg = <0x0400>; + }; + + sync_32k_ick: sync_32k_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&sys_ck>; + ti,bit-shift = <1>; + reg = <0x0410>; + }; + + wdt1_ick: wdt1_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&sys_ck>; + ti,bit-shift = <4>; + reg = <0x0410>; + }; + + omapctrl_ick: omapctrl_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&sys_ck>; + ti,bit-shift = <5>; + reg = <0x0410>; + }; + + cam_fck: cam_fck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&func_96m_ck>; + ti,bit-shift = <31>; + reg = <0x0200>; + }; + + cam_ick: cam_ick { + #clock-cells = <0>; + compatible = "ti,omap3-no-wait-interface-clock"; + clocks = <&l4_ck>; + ti,bit-shift = <31>; + reg = <0x0210>; + }; + + mailboxes_ick: mailboxes_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&l4_ck>; + ti,bit-shift = <30>; + reg = <0x0210>; + }; + + wdt4_ick: wdt4_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&l4_ck>; + ti,bit-shift = <29>; + reg = <0x0210>; + }; + + wdt4_fck: wdt4_fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&func_32k_ck>; + ti,bit-shift = <29>; + reg = <0x0200>; + }; + + mspro_ick: mspro_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&l4_ck>; + ti,bit-shift = <27>; + reg = <0x0210>; + }; + + mspro_fck: mspro_fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&func_96m_ck>; + ti,bit-shift = <27>; + reg = <0x0200>; + }; + + fac_ick: fac_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&l4_ck>; + ti,bit-shift = <25>; + reg = <0x0210>; + }; + + fac_fck: fac_fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&func_12m_ck>; + ti,bit-shift = <25>; + reg = <0x0200>; + }; + + hdq_ick: hdq_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&l4_ck>; + ti,bit-shift = <23>; + reg = <0x0210>; + }; + + hdq_fck: hdq_fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&func_12m_ck>; + ti,bit-shift = <23>; + reg = <0x0200>; + }; + + i2c1_ick: i2c1_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&l4_ck>; + ti,bit-shift = <19>; + reg = <0x0210>; + }; + + i2c2_ick: i2c2_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&l4_ck>; + ti,bit-shift = <20>; + reg = <0x0210>; + }; + + gpmc_fck: gpmc_fck { + #clock-cells = <0>; + compatible = "ti,fixed-factor-clock"; + clocks = <&core_l3_ck>; + ti,clock-div = <1>; + ti,autoidle-shift = <1>; + reg = <0x0238>; + ti,clock-mult = <1>; + }; + + sdma_fck: sdma_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&core_l3_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + sdma_ick: sdma_ick { + #clock-cells = <0>; + compatible = "ti,fixed-factor-clock"; + clocks = <&core_l3_ck>; + ti,clock-div = <1>; + ti,autoidle-shift = <0>; + reg = <0x0238>; + ti,clock-mult = <1>; + }; + + sdrc_ick: sdrc_ick { + #clock-cells = <0>; + compatible = "ti,fixed-factor-clock"; + clocks = <&core_l3_ck>; + ti,clock-div = <1>; + ti,autoidle-shift = <2>; + reg = <0x0238>; + ti,clock-mult = <1>; + }; + + des_ick: des_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&l4_ck>; + ti,bit-shift = <0>; + reg = <0x021c>; + }; + + sha_ick: sha_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&l4_ck>; + ti,bit-shift = <1>; + reg = <0x021c>; + }; + + rng_ick: rng_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&l4_ck>; + ti,bit-shift = <2>; + reg = <0x021c>; + }; + + aes_ick: aes_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&l4_ck>; + ti,bit-shift = <3>; + reg = <0x021c>; + }; + + pka_ick: pka_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&l4_ck>; + ti,bit-shift = <4>; + reg = <0x021c>; + }; + + usb_fck: usb_fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&func_48m_ck>; + ti,bit-shift = <0>; + reg = <0x0204>; + }; +}; diff --git a/arch/arm/boot/dts/omap3-evm-37xx.dts b/arch/arm/boot/dts/omap3-evm-37xx.dts index 4df68ad3736a..9cba94bed7ad 100644 --- a/arch/arm/boot/dts/omap3-evm-37xx.dts +++ b/arch/arm/boot/dts/omap3-evm-37xx.dts @@ -89,7 +89,16 @@ status = "disabled"; }; +&uart1 { + interrupts-extended = <&intc 72 &omap3_pmx_core OMAP3_UART1_RX>; +}; + +&uart2 { + interrupts-extended = <&intc 73 &omap3_pmx_core OMAP3_UART2_RX>; +}; + &uart3 { + interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>; pinctrl-names = "default"; pinctrl-0 = <&uart3_pins>; }; diff --git a/arch/arm/boot/dts/omap3-ldp.dts b/arch/arm/boot/dts/omap3-ldp.dts index 0abe986a4ecc..476ff158ddb3 100644 --- a/arch/arm/boot/dts/omap3-ldp.dts +++ b/arch/arm/boot/dts/omap3-ldp.dts @@ -234,6 +234,10 @@ }; }; +&uart3 { + interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>; +}; + &usb_otg_hs { pinctrl-names = "default"; pinctrl-0 = <&musb_pins>; diff --git a/arch/arm/boot/dts/omap3-lilly-a83x.dtsi b/arch/arm/boot/dts/omap3-lilly-a83x.dtsi index cc1dce6978f5..d97308896f0c 100644 --- a/arch/arm/boot/dts/omap3-lilly-a83x.dtsi +++ b/arch/arm/boot/dts/omap3-lilly-a83x.dtsi @@ -176,9 +176,6 @@ &omap3_pmx_core2 { pinctrl-names = "default"; - pinctrl-0 = < - &hsusb1_2_pins - >; hsusb1_2_pins: pinmux_hsusb1_2_pins { pinctrl-single,pins = < @@ -357,6 +354,10 @@ power = <50>; }; +&mcbsp2 { + status = "okay"; +}; + &gpmc { ranges = <0 0 0x30000000 0x1000000>, <7 0 0x15000000 0x01000000>; diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts index 1a57b61f5e24..059a8ff1e6ac 100644 --- a/arch/arm/boot/dts/omap3-n900.dts +++ b/arch/arm/boot/dts/omap3-n900.dts @@ -10,6 +10,7 @@ /dts-v1/; #include "omap34xx-hs.dtsi" +#include <dt-bindings/input/input.h> / { model = "Nokia N900"; @@ -21,6 +22,17 @@ }; }; + leds { + compatible = "gpio-leds"; + heartbeat { + label = "debug::sleep"; + gpios = <&gpio6 2 GPIO_ACTIVE_HIGH>; /* gpio162 */ + linux,default-trigger = "default-on"; + pinctrl-names = "default"; + pinctrl-0 = <&debug_leds>; + }; + }; + memory { device_type = "memory"; reg = <0x80000000 0x10000000>; /* 256 MB */ @@ -90,6 +102,19 @@ }; }; }; + + sound: n900-audio { + compatible = "nokia,n900-audio"; + + nokia,cpu-dai = <&mcbsp2>; + nokia,audio-codec = <&tlv320aic3x>, <&tlv320aic3x_aux>; + nokia,headphone-amplifier = <&tpa6130a2>; + + tvout-selection-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; /* 40 */ + jack-detection-gpios = <&gpio6 17 GPIO_ACTIVE_HIGH>; /* 177 */ + eci-switch-gpios = <&gpio6 22 GPIO_ACTIVE_HIGH>; /* 182 */ + speaker-amplifier-gpios = <&twl_gpio 7 GPIO_ACTIVE_HIGH>; + }; }; &omap3_pmx_core { @@ -130,6 +155,21 @@ >; }; + debug_leds: pinmux_debug_led_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2198, PIN_OUTPUT | MUX_MODE4) /* mcbsp1_clkx.gpio_162 */ + >; + }; + + mcspi4_pins: pinmux_mcspi4_pins { + pinctrl-single,pins = < + 0x15c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mcspi4_clk */ + 0x162 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mcspi4_somi */ + 0x160 (PIN_OUTPUT | MUX_MODE1) /* mcspi4_simo */ + 0x166 (PIN_OUTPUT | MUX_MODE1) /* mcspi4_cs0 */ + >; + }; + mmc1_pins: pinmux_mmc1_pins { pinctrl-single,pins = < 0x114 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk */ @@ -173,6 +213,37 @@ 0x0da (PIN_OUTPUT | MUX_MODE1) /* dss_data23.sdi_clkn */ >; }; + + wl1251_pins: pinmux_wl1251 { + pinctrl-single,pins = < + 0x0ce (PIN_OUTPUT | MUX_MODE4) /* gpio 87 => wl1251 enable */ + 0x05a (PIN_INPUT | MUX_MODE4) /* gpio 42 => wl1251 irq */ + >; + }; + + ssi_pins: pinmux_ssi { + pinctrl-single,pins = < + 0x150 (PIN_INPUT_PULLUP | MUX_MODE1) /* ssi1_rdy_tx */ + 0x14e (PIN_OUTPUT | MUX_MODE1) /* ssi1_flag_tx */ + 0x152 (PIN_INPUT | WAKEUP_EN | MUX_MODE4) /* ssi1_wake_tx (cawake) */ + 0x14c (PIN_OUTPUT | MUX_MODE1) /* ssi1_dat_tx */ + 0x154 (PIN_INPUT | MUX_MODE1) /* ssi1_dat_rx */ + 0x156 (PIN_INPUT | MUX_MODE1) /* ssi1_flag_rx */ + 0x158 (PIN_OUTPUT | MUX_MODE1) /* ssi1_rdy_rx */ + 0x15a (PIN_OUTPUT | MUX_MODE1) /* ssi1_wake */ + >; + }; + + modem_pins: pinmux_modem { + pinctrl-single,pins = < + 0x0ac (PIN_OUTPUT | MUX_MODE4) /* gpio 70 => cmt_apeslpx */ + 0x0b0 (PIN_INPUT | WAKEUP_EN | MUX_MODE4) /* gpio 72 => ape_rst_rq */ + 0x0b2 (PIN_OUTPUT | MUX_MODE4) /* gpio 73 => cmt_rst_rq */ + 0x0b4 (PIN_OUTPUT | MUX_MODE4) /* gpio 74 => cmt_en */ + 0x0b6 (PIN_OUTPUT | MUX_MODE4) /* gpio 75 => cmt_rst */ + 0x15e (PIN_OUTPUT | MUX_MODE4) /* gpio 157 => cmt_bsi */ + >; + }; }; &i2c1 { @@ -283,57 +354,57 @@ }; &twl_keypad { - linux,keymap = < 0x00000010 /* KEY_Q */ - 0x00010018 /* KEY_O */ - 0x00020019 /* KEY_P */ - 0x00030033 /* KEY_COMMA */ - 0x0004000e /* KEY_BACKSPACE */ - 0x0006001e /* KEY_A */ - 0x0007001f /* KEY_S */ - - 0x01000011 /* KEY_W */ - 0x01010020 /* KEY_D */ - 0x01020021 /* KEY_F */ - 0x01030022 /* KEY_G */ - 0x01040023 /* KEY_H */ - 0x01050024 /* KEY_J */ - 0x01060025 /* KEY_K */ - 0x01070026 /* KEY_L */ - - 0x02000012 /* KEY_E */ - 0x02010034 /* KEY_DOT */ - 0x02020067 /* KEY_UP */ - 0x0203001c /* KEY_ENTER */ - 0x0205002c /* KEY_Z */ - 0x0206002d /* KEY_X */ - 0x0207002e /* KEY_C */ - 0x02080043 /* KEY_F9 */ - - 0x03000013 /* KEY_R */ - 0x0301002f /* KEY_V */ - 0x03020030 /* KEY_B */ - 0x03030031 /* KEY_N */ - 0x03040032 /* KEY_M */ - 0x03050039 /* KEY_SPACE */ - 0x03060039 /* KEY_SPACE */ - 0x03070069 /* KEY_LEFT */ - - 0x04000014 /* KEY_T */ - 0x0401006c /* KEY_DOWN */ - 0x0402006a /* KEY_RIGHT */ - 0x0404001d /* KEY_LEFTCTRL */ - 0x04050064 /* KEY_RIGHTALT */ - 0x0406002a /* KEY_LEFTSHIFT */ - 0x04080044 /* KEY_F10 */ - - 0x05000015 /* KEY_Y */ - 0x05080057 /* KEY_F11 */ - - 0x06000016 /* KEY_U */ - - 0x07000017 /* KEY_I */ - 0x07010041 /* KEY_F7 */ - 0x07020042 /* KEY_F8 */ + linux,keymap = < MATRIX_KEY(0x00, 0x00, KEY_Q) + MATRIX_KEY(0x00, 0x01, KEY_O) + MATRIX_KEY(0x00, 0x02, KEY_P) + MATRIX_KEY(0x00, 0x03, KEY_COMMA) + MATRIX_KEY(0x00, 0x04, KEY_BACKSPACE) + MATRIX_KEY(0x00, 0x06, KEY_A) + MATRIX_KEY(0x00, 0x07, KEY_S) + + MATRIX_KEY(0x01, 0x00, KEY_W) + MATRIX_KEY(0x01, 0x01, KEY_D) + MATRIX_KEY(0x01, 0x02, KEY_F) + MATRIX_KEY(0x01, 0x03, KEY_G) + MATRIX_KEY(0x01, 0x04, KEY_H) + MATRIX_KEY(0x01, 0x05, KEY_J) + MATRIX_KEY(0x01, 0x06, KEY_K) + MATRIX_KEY(0x01, 0x07, KEY_L) + + MATRIX_KEY(0x02, 0x00, KEY_E) + MATRIX_KEY(0x02, 0x01, KEY_DOT) + MATRIX_KEY(0x02, 0x02, KEY_UP) + MATRIX_KEY(0x02, 0x03, KEY_ENTER) + MATRIX_KEY(0x02, 0x05, KEY_Z) + MATRIX_KEY(0x02, 0x06, KEY_X) + MATRIX_KEY(0x02, 0x07, KEY_C) + MATRIX_KEY(0x02, 0x08, KEY_F9) + + MATRIX_KEY(0x03, 0x00, KEY_R) + MATRIX_KEY(0x03, 0x01, KEY_V) + MATRIX_KEY(0x03, 0x02, KEY_B) + MATRIX_KEY(0x03, 0x03, KEY_N) + MATRIX_KEY(0x03, 0x04, KEY_M) + MATRIX_KEY(0x03, 0x05, KEY_SPACE) + MATRIX_KEY(0x03, 0x06, KEY_SPACE) + MATRIX_KEY(0x03, 0x07, KEY_LEFT) + + MATRIX_KEY(0x04, 0x00, KEY_T) + MATRIX_KEY(0x04, 0x01, KEY_DOWN) + MATRIX_KEY(0x04, 0x02, KEY_RIGHT) + MATRIX_KEY(0x04, 0x04, KEY_LEFTCTRL) + MATRIX_KEY(0x04, 0x05, KEY_RIGHTALT) + MATRIX_KEY(0x04, 0x06, KEY_LEFTSHIFT) + MATRIX_KEY(0x04, 0x08, KEY_F10) + + MATRIX_KEY(0x05, 0x00, KEY_Y) + MATRIX_KEY(0x05, 0x08, KEY_F11) + + MATRIX_KEY(0x06, 0x00, KEY_U) + + MATRIX_KEY(0x07, 0x00, KEY_I) + MATRIX_KEY(0x07, 0x01, KEY_F7) + MATRIX_KEY(0x07, 0x02, KEY_F8) >; }; @@ -604,6 +675,30 @@ }; }; +&mcspi4 { + pinctrl-names = "default"; + pinctrl-0 = <&mcspi4_pins>; + + wl1251@0 { + pinctrl-names = "default"; + pinctrl-0 = <&wl1251_pins>; + + vio-supply = <&vio>; + + compatible = "ti,wl1251"; + reg = <0>; + spi-max-frequency = <48000000>; + + spi-cpol; + spi-cpha; + + ti,power-gpio = <&gpio3 23 GPIO_ACTIVE_HIGH>; /* 87 */ + + interrupt-parent = <&gpio2>; + interrupts = <10 IRQ_TYPE_NONE>; /* gpio line 42 */ + }; +}; + &usb_otg_hs { interface-type = <0>; usb-phy = <&usb2_phy>; @@ -618,11 +713,13 @@ }; &uart2 { + interrupts-extended = <&intc 73 &omap3_pmx_core OMAP3_UART2_RX>; pinctrl-names = "default"; pinctrl-0 = <&uart2_pins>; }; &uart3 { + interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>; pinctrl-names = "default"; pinctrl-0 = <&uart3_pins>; }; @@ -662,3 +759,48 @@ }; }; }; + +&mcbsp2 { + status = "ok"; +}; + +&ssi_port1 { + pinctrl-names = "default"; + pinctrl-0 = <&ssi_pins>; + + ti,ssi-cawake-gpio = <&gpio5 23 GPIO_ACTIVE_HIGH>; /* 151 */ + + modem: hsi-client { + compatible = "nokia,n900-modem"; + + pinctrl-names = "default"; + pinctrl-0 = <&modem_pins>; + + hsi-channel-ids = <0>, <1>, <2>, <3>; + hsi-channel-names = "mcsaab-control", + "speech-control", + "speech-data", + "mcsaab-data"; + hsi-speed-kbps = <55000>; + hsi-mode = "frame"; + hsi-flow = "synchronized"; + hsi-arb-mode = "round-robin"; + + interrupts-extended = <&gpio3 8 IRQ_TYPE_EDGE_FALLING>; /* 72 */ + + gpios = <&gpio3 6 GPIO_ACTIVE_HIGH>, /* 70 */ + <&gpio3 9 GPIO_ACTIVE_HIGH>, /* 73 */ + <&gpio3 10 GPIO_ACTIVE_HIGH>, /* 74 */ + <&gpio3 11 GPIO_ACTIVE_HIGH>, /* 75 */ + <&gpio5 29 GPIO_ACTIVE_HIGH>; /* 157 */ + gpio-names = "cmt_apeslpx", + "cmt_rst_rq", + "cmt_en", + "cmt_rst", + "cmt_bsi"; + }; +}; + +&ssi_port2 { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/omap3-n950-n9.dtsi b/arch/arm/boot/dts/omap3-n950-n9.dtsi index 5c26c184f2c1..70addcba37c5 100644 --- a/arch/arm/boot/dts/omap3-n950-n9.dtsi +++ b/arch/arm/boot/dts/omap3-n950-n9.dtsi @@ -67,6 +67,20 @@ ti,pulldowns = <0x008106>; /* BIT(1) | BIT(2) | BIT(8) | BIT(15) */ }; +/* CSI-2 receiver */ +&vaux2 { + regulator-name = "vaux2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; +}; + +/* Cameras */ +&vaux3 { + regulator-name = "vaux3"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; +}; + &i2c2 { clock-frequency = <400000>; }; diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi index 4231191ade06..b2891a9a6975 100644 --- a/arch/arm/boot/dts/omap3.dtsi +++ b/arch/arm/boot/dts/omap3.dtsi @@ -267,7 +267,7 @@ uart1: serial@4806a000 { compatible = "ti,omap3-uart"; reg = <0x4806a000 0x2000>; - interrupts = <72>; + interrupts-extended = <&intc 72>; dmas = <&sdma 49 &sdma 50>; dma-names = "tx", "rx"; ti,hwmods = "uart1"; @@ -277,7 +277,7 @@ uart2: serial@4806c000 { compatible = "ti,omap3-uart"; reg = <0x4806c000 0x400>; - interrupts = <73>; + interrupts-extended = <&intc 73>; dmas = <&sdma 51 &sdma 52>; dma-names = "tx", "rx"; ti,hwmods = "uart2"; @@ -287,7 +287,7 @@ uart3: serial@49020000 { compatible = "ti,omap3-uart"; reg = <0x49020000 0x400>; - interrupts = <74>; + interrupts-extended = <&intc 74>; dmas = <&sdma 53 &sdma 54>; dma-names = "tx", "rx"; ti,hwmods = "uart3"; @@ -757,6 +757,51 @@ clock-names = "fck"; }; }; + + ssi: ssi-controller@48058000 { + compatible = "ti,omap3-ssi"; + ti,hwmods = "ssi"; + + status = "disabled"; + + reg = <0x48058000 0x1000>, + <0x48059000 0x1000>; + reg-names = "sys", + "gdd"; + + interrupts = <71>; + interrupt-names = "gdd_mpu"; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + ssi_port1: ssi-port@4805a000 { + compatible = "ti,omap3-ssi-port"; + + reg = <0x4805a000 0x800>, + <0x4805a800 0x800>; + reg-names = "tx", + "rx"; + + interrupt-parent = <&intc>; + interrupts = <67>, + <68>; + }; + + ssi_port2: ssi-port@4805b000 { + compatible = "ti,omap3-ssi-port"; + + reg = <0x4805b000 0x800>, + <0x4805b800 0x800>; + reg-names = "tx", + "rx"; + + interrupt-parent = <&intc>; + interrupts = <69>, + <70>; + }; + }; }; }; diff --git a/arch/arm/boot/dts/omap34xx.dtsi b/arch/arm/boot/dts/omap34xx.dtsi index 2e92360da1f3..3819c1e91591 100644 --- a/arch/arm/boot/dts/omap34xx.dtsi +++ b/arch/arm/boot/dts/omap34xx.dtsi @@ -40,6 +40,17 @@ }; }; +&ssi { + status = "ok"; + + clocks = <&ssi_ssr_fck>, + <&ssi_sst_fck>, + <&ssi_ick>; + clock-names = "ssi_ssr_fck", + "ssi_sst_fck", + "ssi_ick"; +}; + /include/ "omap34xx-omap36xx-clocks.dtsi" /include/ "omap36xx-omap3430es2plus-clocks.dtsi" /include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi" diff --git a/arch/arm/boot/dts/omap36xx-clocks.dtsi b/arch/arm/boot/dts/omap36xx-clocks.dtsi index 6b5280d04a0e..200ae3a5cbbb 100644 --- a/arch/arm/boot/dts/omap36xx-clocks.dtsi +++ b/arch/arm/boot/dts/omap36xx-clocks.dtsi @@ -83,7 +83,7 @@ }; &dpll4_m5x2_mul_ck { - clock-mult = <1>; + ti,clock-mult = <1>; }; &dpll4_m6x2_mul_ck { diff --git a/arch/arm/boot/dts/omap36xx.dtsi b/arch/arm/boot/dts/omap36xx.dtsi index 22cf4647087e..541704a59a5a 100644 --- a/arch/arm/boot/dts/omap36xx.dtsi +++ b/arch/arm/boot/dts/omap36xx.dtsi @@ -78,6 +78,17 @@ clock-names = "fck", "tv_dac_clk"; }; +&ssi { + status = "ok"; + + clocks = <&ssi_ssr_fck>, + <&ssi_sst_fck>, + <&ssi_ick>; + clock-names = "ssi_ssr_fck", + "ssi_sst_fck", + "ssi_ick"; +}; + /include/ "omap34xx-omap36xx-clocks.dtsi" /include/ "omap36xx-omap3430es2plus-clocks.dtsi" /include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi" diff --git a/arch/arm/boot/dts/omap3xxx-clocks.dtsi b/arch/arm/boot/dts/omap3xxx-clocks.dtsi index 12be2b35dae9..e47ff69dcf70 100644 --- a/arch/arm/boot/dts/omap3xxx-clocks.dtsi +++ b/arch/arm/boot/dts/omap3xxx-clocks.dtsi @@ -453,10 +453,11 @@ dpll4_m5x2_mul_ck: dpll4_m5x2_mul_ck { #clock-cells = <0>; - compatible = "fixed-factor-clock"; + compatible = "ti,fixed-factor-clock"; clocks = <&dpll4_m5_ck>; - clock-mult = <2>; - clock-div = <1>; + ti,clock-mult = <2>; + ti,clock-div = <1>; + ti,set-rate-parent; }; dpll4_m5x2_ck: dpll4_m5x2_ck { diff --git a/arch/arm/boot/dts/omap4-duovero-parlor.dts b/arch/arm/boot/dts/omap4-duovero-parlor.dts index 96f51d870812..cd53a64d8f2e 100644 --- a/arch/arm/boot/dts/omap4-duovero-parlor.dts +++ b/arch/arm/boot/dts/omap4-duovero-parlor.dts @@ -46,35 +46,35 @@ led_pins: pinmux_led_pins { pinctrl-single,pins = < - 0xd6 (PIN_OUTPUT | MUX_MODE3) /* abe_dmic_din3.gpio_122 */ + OMAP4_IOPAD(0x116, PIN_OUTPUT | MUX_MODE3) /* abe_dmic_din3.gpio_122 */ >; }; button_pins: pinmux_button_pins { pinctrl-single,pins = < - 0xd4 (PIN_INPUT_PULLUP | MUX_MODE3) /* abe_dmic_din2.gpio_121 */ + OMAP4_IOPAD(0x114, PIN_INPUT_PULLUP | MUX_MODE3) /* abe_dmic_din2.gpio_121 */ >; }; i2c2_pins: pinmux_i2c2_pins { pinctrl-single,pins = < - 0xe6 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_scl */ - 0xe8 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_sda */ + OMAP4_IOPAD(0x126, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_scl */ + OMAP4_IOPAD(0x128, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_sda */ >; }; i2c3_pins: pinmux_i2c3_pins { pinctrl-single,pins = < - 0xea (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl */ - 0xec (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */ + OMAP4_IOPAD(0x12a, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl */ + OMAP4_IOPAD(0x12c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */ >; }; smsc_pins: pinmux_smsc_pins { pinctrl-single,pins = < - 0x28 (PIN_INPUT | MUX_MODE3) /* gpmc_a20.gpio_44: IRQ */ - 0x2a (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a21.gpio_45: nReset */ - 0x30 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a24.gpio_48: amdix enabled */ + OMAP4_IOPAD(0x068, PIN_INPUT | MUX_MODE3) /* gpmc_a20.gpio_44: IRQ */ + OMAP4_IOPAD(0x06a, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a21.gpio_45: nReset */ + OMAP4_IOPAD(0x070, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a24.gpio_48: amdix enabled */ >; }; }; diff --git a/arch/arm/boot/dts/omap4-duovero.dtsi b/arch/arm/boot/dts/omap4-duovero.dtsi index a514791154eb..e860ccd9d09c 100644 --- a/arch/arm/boot/dts/omap4-duovero.dtsi +++ b/arch/arm/boot/dts/omap4-duovero.dtsi @@ -67,100 +67,98 @@ pinctrl-names = "default"; pinctrl-0 = < &twl6040_pins - &mcpdm_pins - &mcbsp1_pins &hsusbb1_pins >; twl6040_pins: pinmux_twl6040_pins { pinctrl-single,pins = < - 0x126 (PIN_OUTPUT | MUX_MODE3) /* usbb2_ulpitll_nxt.gpio_160 */ - 0x160 (PIN_INPUT | MUX_MODE0) /* sys_nirq2.sys_nirq2 */ + OMAP4_IOPAD(0x166, PIN_OUTPUT | MUX_MODE3) /* usbb2_ulpitll_nxt.gpio_160 */ + OMAP4_IOPAD(0x1a0, PIN_INPUT | MUX_MODE0) /* sys_nirq2.sys_nirq2 */ >; }; mcpdm_pins: pinmux_mcpdm_pins { pinctrl-single,pins = < - 0xc6 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_pdm_ul_data.abe_pdm_ul_data */ - 0xc8 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_pdm_dl_data.abe_pdm_dl_data */ - 0xca (PIN_INPUT_PULLUP | MUX_MODE0) /* abe_pdm_frame.abe_pdm_frame */ - 0xcc (PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_pdm_lb_clk.abe_pdm_lb_clk */ - 0xce (PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_clks.abe_clks */ + OMAP4_IOPAD(0x106, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_pdm_ul_data.abe_pdm_ul_data */ + OMAP4_IOPAD(0x108, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_pdm_dl_data.abe_pdm_dl_data */ + OMAP4_IOPAD(0x10a, PIN_INPUT_PULLUP | MUX_MODE0) /* abe_pdm_frame.abe_pdm_frame */ + OMAP4_IOPAD(0x10c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_pdm_lb_clk.abe_pdm_lb_clk */ + OMAP4_IOPAD(0x10e, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_clks.abe_clks */ >; }; mcbsp1_pins: pinmux_mcbsp1_pins { pinctrl-single,pins = < - 0xbe (PIN_INPUT | MUX_MODE0) /* abe_mcbsp1_clkx.abe_mcbsp1_clkx */ - 0xc0 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp1_dr.abe_mcbsp1_dr */ - 0xc2 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp1_dx.abe_mcbsp1_dx */ - 0xc4 (PIN_INPUT | MUX_MODE0) /* abe_mcbsp1_fsx.abe_mcbsp1_fsx */ + OMAP4_IOPAD(0x0fe, PIN_INPUT | MUX_MODE0) /* abe_mcbsp1_clkx.abe_mcbsp1_clkx */ + OMAP4_IOPAD(0x100, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp1_dr.abe_mcbsp1_dr */ + OMAP4_IOPAD(0x102, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp1_dx.abe_mcbsp1_dx */ + OMAP4_IOPAD(0x104, PIN_INPUT | MUX_MODE0) /* abe_mcbsp1_fsx.abe_mcbsp1_fsx */ >; }; hsusbb1_pins: pinmux_hsusbb1_pins { pinctrl-single,pins = < - 0x82 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_clk.usbb1_ulpiphy_clk */ - 0x84 (PIN_OUTPUT | MUX_MODE4) /* usbb1_ulpitll_stp.usbb1_ulpiphy_stp */ - 0x86 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dir.usbb1_ulpiphy_dir */ - 0x88 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_nxt.usbb1_ulpiphy_nxt */ - 0x8a (PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat0.usbb1_ulpiphy_dat0 */ - 0x8c (PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat1.usbb1_ulpiphy_dat1 */ - 0x8e (PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat2.usbb1_ulpiphy_dat2 */ - 0x90 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat3.usbb1_ulpiphy_dat3 */ - 0x92 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat4.usbb1_ulpiphy_dat4 */ - 0x94 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat5.usbb1_ulpiphy_dat5 */ - 0x96 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat6.usbb1_ulpiphy_dat6 */ - 0x98 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat7.usbb1_ulpiphy_dat7 */ + OMAP4_IOPAD(0x0c2, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_clk.usbb1_ulpiphy_clk */ + OMAP4_IOPAD(0x0c4, PIN_OUTPUT | MUX_MODE4) /* usbb1_ulpitll_stp.usbb1_ulpiphy_stp */ + OMAP4_IOPAD(0x0c6, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dir.usbb1_ulpiphy_dir */ + OMAP4_IOPAD(0x0c8, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_nxt.usbb1_ulpiphy_nxt */ + OMAP4_IOPAD(0x0ca, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat0.usbb1_ulpiphy_dat0 */ + OMAP4_IOPAD(0x0cc, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat1.usbb1_ulpiphy_dat1 */ + OMAP4_IOPAD(0x0ce, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat2.usbb1_ulpiphy_dat2 */ + OMAP4_IOPAD(0x0d0, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat3.usbb1_ulpiphy_dat3 */ + OMAP4_IOPAD(0x0d2, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat4.usbb1_ulpiphy_dat4 */ + OMAP4_IOPAD(0x0d4, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat5.usbb1_ulpiphy_dat5 */ + OMAP4_IOPAD(0x0d6, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat6.usbb1_ulpiphy_dat6 */ + OMAP4_IOPAD(0x0d8, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat7.usbb1_ulpiphy_dat7 */ >; }; hsusb1phy_pins: pinmux_hsusb1phy_pins { pinctrl-single,pins = < - 0x4c (PIN_OUTPUT | MUX_MODE3) /* gpmc_wait1.gpio_62 */ + OMAP4_IOPAD(0x08c, PIN_OUTPUT | MUX_MODE3) /* gpmc_wait1.gpio_62 */ >; }; w2cbw0015_pins: pinmux_w2cbw0015_pins { pinctrl-single,pins = < - 0x26 (PIN_OUTPUT | MUX_MODE3) /* gpmc_a19.gpio_43 */ - 0x3a (PIN_INPUT | MUX_MODE3) /* gpmc_ncs3.gpio_53 */ + OMAP4_IOPAD(0x066, PIN_OUTPUT | MUX_MODE3) /* gpmc_a19.gpio_43 */ + OMAP4_IOPAD(0x07a, PIN_INPUT | MUX_MODE3) /* gpmc_ncs3.gpio_53 */ >; }; i2c1_pins: pinmux_i2c1_pins { pinctrl-single,pins = < - 0xe2 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */ - 0xe4 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */ + OMAP4_IOPAD(0x122, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */ + OMAP4_IOPAD(0x124, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */ >; }; i2c4_pins: pinmux_i2c4_pins { pinctrl-single,pins = < - 0xee (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_scl */ - 0xf0 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_sda */ + OMAP4_IOPAD(0x12e, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_scl */ + OMAP4_IOPAD(0x130, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_sda */ >; }; mmc1_pins: pinmux_mmc1_pins { pinctrl-single,pins = < - 0xa2 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk */ - 0xa4 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmcc1_cmd */ - 0xa6 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmcc1_dat0 */ - 0xa8 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1 */ - 0xaa (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2 */ - 0xac (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3 */ + OMAP4_IOPAD(0x0e2, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk */ + OMAP4_IOPAD(0x0e4, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmcc1_cmd */ + OMAP4_IOPAD(0x0e6, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmcc1_dat0 */ + OMAP4_IOPAD(0x0e8, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1 */ + OMAP4_IOPAD(0x0ea, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2 */ + OMAP4_IOPAD(0x0ec, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3 */ >; }; mmc5_pins: pinmux_mmc5_pins { pinctrl-single,pins = < - 0x108 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_clk */ - 0x10a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmcc5_cmd */ - 0x10c (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmcc5_dat0 */ - 0x10e (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat1 */ - 0x110 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat2 */ - 0x112 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat3 */ + OMAP4_IOPAD(0x148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_clk */ + OMAP4_IOPAD(0x14a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmcc5_cmd */ + OMAP4_IOPAD(0x14c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmcc5_dat0 */ + OMAP4_IOPAD(0x14e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat1 */ + OMAP4_IOPAD(0x150, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat2 */ + OMAP4_IOPAD(0x152, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat3 */ >; }; }; @@ -202,6 +200,18 @@ clock-frequency = <400000>; }; +&mcbsp1 { + pinctrl-names = "default"; + pinctrl-0 = <&mcbsp1_pins>; + status = "okay"; +}; + +&mcpdm { + pinctrl-names = "default"; + pinctrl-0 = <&mcpdm_pins>; + status = "okay"; +}; + &mmc1 { pinctrl-names = "default"; pinctrl-0 = <&mmc1_pins>; diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi index d2c45bfaaa2c..8cfa3c8a72b0 100644 --- a/arch/arm/boot/dts/omap4-panda-common.dtsi +++ b/arch/arm/boot/dts/omap4-panda-common.dtsi @@ -481,6 +481,21 @@ usb-supply = <&vusb>; }; +&uart2 { + interrupts-extended = <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH + &omap4_pmx_core OMAP4_UART2_RX>; +}; + +&uart3 { + interrupts-extended = <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH + &omap4_pmx_core OMAP4_UART3_RX>; +}; + +&uart4 { + interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH + &omap4_pmx_core OMAP4_UART4_RX>; +}; + &usb_otg_hs { interface-type = <1>; mode = <3>; diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts index 48983c8d56c2..3e1da43068f6 100644 --- a/arch/arm/boot/dts/omap4-sdp.dts +++ b/arch/arm/boot/dts/omap4-sdp.dts @@ -570,16 +570,22 @@ }; &uart2 { + interrupts-extended = <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH + &omap4_pmx_core OMAP4_UART2_RX>; pinctrl-names = "default"; pinctrl-0 = <&uart2_pins>; }; &uart3 { + interrupts-extended = <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH + &omap4_pmx_core OMAP4_UART3_RX>; pinctrl-names = "default"; pinctrl-0 = <&uart3_pins>; }; &uart4 { + interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH + &omap4_pmx_core OMAP4_UART4_RX>; pinctrl-names = "default"; pinctrl-0 = <&uart4_pins>; }; diff --git a/arch/arm/boot/dts/omap4-var-dvk-om44.dts b/arch/arm/boot/dts/omap4-var-dvk-om44.dts new file mode 100644 index 000000000000..458d79fa378b --- /dev/null +++ b/arch/arm/boot/dts/omap4-var-dvk-om44.dts @@ -0,0 +1,71 @@ +/* + * Copyright (C) 2014 Joachim Eastwood <manabian@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +#include "omap4-var-som-om44.dtsi" +#include "omap4-var-som-om44-wlan.dtsi" +#include "omap4-var-om44customboard.dtsi" + +/ { + model = "Variscite VAR-DVK-OM44"; + compatible = "variscite,var-dvk-om44", "variscite,var-som-om44", "ti,omap4460", "ti,omap4"; + + aliases { + display0 = &lcd0; + display1 = &hdmi0; + }; + + lcd0: display { + compatible = "innolux,at070tn83", "panel-dpi"; + label = "lcd"; + panel-timing { + clock-frequency = <33333333>; + + hback-porch = <40>; + hactive = <800>; + hfront-porch = <40>; + hsync-len = <48>; + + vback-porch = <29>; + vactive = <480>; + vfront-porch = <13>; + vsync-len = <3>; + }; + + port { + lcd_in: endpoint { + remote-endpoint = <&dpi_out>; + }; + }; + }; + + backlight { + compatible = "gpio-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&backlight_pins>; + + gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>; /* gpio 122 */ + }; +}; + +&dss { + pinctrl-names = "default"; + pinctrl-0 = <&dss_dpi_pins>; + + port { + dpi_out: endpoint { + remote-endpoint = <&lcd_in>; + data-lines = <24>; + }; + }; +}; + +&dsi2 { + status = "okay"; + vdd-supply = <&vcxio>; +}; diff --git a/arch/arm/boot/dts/omap4-var-om44customboard.dtsi b/arch/arm/boot/dts/omap4-var-om44customboard.dtsi new file mode 100644 index 000000000000..f2d2fdb75628 --- /dev/null +++ b/arch/arm/boot/dts/omap4-var-om44customboard.dtsi @@ -0,0 +1,235 @@ +/* + * Copyright (C) 2014 Joachim Eastwood <manabian@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <dt-bindings/input/input.h> + +/ { + aliases { + display0 = &hdmi0; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_led_pins>; + + led0 { + label = "var:green:led0"; + gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>; /* gpio 173 */ + linux,default-trigger = "heartbeat"; + }; + + led1 { + label = "var:green:led1"; + gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>; /* gpio 172 */ + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_key_pins>; + #address-cells = <1>; + #size-cells = <0>; + + user-key@184 { + label = "user"; + gpios = <&gpio6 24 GPIO_ACTIVE_HIGH>; /* gpio 184 */ + linux,code = <BTN_EXTRA>; + gpio-key,wakeup; + }; + }; + + hdmi0: connector@0 { + compatible = "hdmi-connector"; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_hpd_pins>; + label = "hdmi"; + type = "a"; + + hpd-gpios = <&gpio2 31 GPIO_ACTIVE_HIGH>; /* gpio_63 */ + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi_out>; + }; + }; + }; +}; + +&omap4_pmx_core { + uart1_pins: pinmux_uart1_pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x13c, PIN_INPUT_PULLUP | MUX_MODE1) /* mcspi1_cs2.uart1_cts */ + OMAP4_IOPAD(0x13e, PIN_OUTPUT | MUX_MODE1) /* mcspi1_cs3.uart1_rts */ + OMAP4_IOPAD(0x126, PIN_INPUT_PULLUP | MUX_MODE1) /* i2c2_scl.uart1_rx */ + OMAP4_IOPAD(0x128, PIN_OUTPUT | MUX_MODE1) /* i2c2_sda.uart1_tx */ + >; + }; + + mcspi1_pins: pinmux_mcspi1_pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x132, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */ + OMAP4_IOPAD(0x134, PIN_INPUT | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */ + OMAP4_IOPAD(0x136, PIN_INPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */ + OMAP4_IOPAD(0x138, PIN_INPUT | MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 */ + >; + }; + + mcasp_pins: pinmux_mcsasp_pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x0f8, PIN_OUTPUT | MUX_MODE2) /* mcbsp2_dr.abe_mcasp_axr */ + >; + }; + + dss_dpi_pins: pinmux_dss_dpi_pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x162, PIN_OUTPUT | MUX_MODE5) /* dispc2_data23 */ + OMAP4_IOPAD(0x164, PIN_OUTPUT | MUX_MODE5) /* dispc2_data22 */ + OMAP4_IOPAD(0x166, PIN_OUTPUT | MUX_MODE5) /* dispc2_data21 */ + OMAP4_IOPAD(0x168, PIN_OUTPUT | MUX_MODE5) /* dispc2_data20 */ + OMAP4_IOPAD(0x16a, PIN_OUTPUT | MUX_MODE5) /* dispc2_data19 */ + OMAP4_IOPAD(0x16c, PIN_OUTPUT | MUX_MODE5) /* dispc2_data18 */ + OMAP4_IOPAD(0x16e, PIN_OUTPUT | MUX_MODE5) /* dispc2_data15 */ + OMAP4_IOPAD(0x170, PIN_OUTPUT | MUX_MODE5) /* dispc2_data14 */ + OMAP4_IOPAD(0x172, PIN_OUTPUT | MUX_MODE5) /* dispc2_data13 */ + OMAP4_IOPAD(0x174, PIN_OUTPUT | MUX_MODE5) /* dispc2_data12 */ + OMAP4_IOPAD(0x176, PIN_OUTPUT | MUX_MODE5) /* dispc2_data11 */ + OMAP4_IOPAD(0x1b4, PIN_OUTPUT | MUX_MODE5) /* dispc2_data10 */ + OMAP4_IOPAD(0x1b6, PIN_OUTPUT | MUX_MODE5) /* dispc2_data9 */ + OMAP4_IOPAD(0x1b8, PIN_OUTPUT | MUX_MODE5) /* dispc2_data16 */ + OMAP4_IOPAD(0x1ba, PIN_OUTPUT | MUX_MODE5) /* dispc2_data17 */ + OMAP4_IOPAD(0x1bc, PIN_OUTPUT | MUX_MODE5) /* dispc2_hsync */ + OMAP4_IOPAD(0x1be, PIN_OUTPUT | MUX_MODE5) /* dispc2_pclk */ + OMAP4_IOPAD(0x1c0, PIN_OUTPUT | MUX_MODE5) /* dispc2_vsync */ + OMAP4_IOPAD(0x1c2, PIN_OUTPUT | MUX_MODE5) /* dispc2_de */ + OMAP4_IOPAD(0x1c4, PIN_OUTPUT | MUX_MODE5) /* dispc2_data8 */ + OMAP4_IOPAD(0x1c6, PIN_OUTPUT | MUX_MODE5) /* dispc2_data7 */ + OMAP4_IOPAD(0x1c8, PIN_OUTPUT | MUX_MODE5) /* dispc2_data6 */ + OMAP4_IOPAD(0x1ca, PIN_OUTPUT | MUX_MODE5) /* dispc2_data5 */ + OMAP4_IOPAD(0x1cc, PIN_OUTPUT | MUX_MODE5) /* dispc2_data4 */ + OMAP4_IOPAD(0x1ce, PIN_OUTPUT | MUX_MODE5) /* dispc2_data3 */ + OMAP4_IOPAD(0x1d0, PIN_OUTPUT | MUX_MODE5) /* dispc2_data2 */ + OMAP4_IOPAD(0x1d2, PIN_OUTPUT | MUX_MODE5) /* dispc2_data1 */ + OMAP4_IOPAD(0x1d4, PIN_OUTPUT | MUX_MODE5) /* dispc2_data0 */ + >; + }; + + dss_hdmi_pins: pinmux_dss_hdmi_pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x09a, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_cec.hdmi_cec */ + OMAP4_IOPAD(0x09c, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_scl.hdmi_scl */ + OMAP4_IOPAD(0x09e, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_sda.hdmi_sda */ + >; + }; + + i2c4_pins: pinmux_i2c4_pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x12e, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_scl */ + OMAP4_IOPAD(0x130, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_sda */ + >; + }; + + mmc5_pins: pinmux_mmc5_pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x0f6, PIN_INPUT | MUX_MODE3) /* abe_mcbsp2_clkx.gpio_110 */ + OMAP4_IOPAD(0x148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_clk.sdmmc5_clk */ + OMAP4_IOPAD(0x14a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_cmd.sdmmc5_cmd */ + OMAP4_IOPAD(0x14c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat0.sdmmc5_dat0 */ + OMAP4_IOPAD(0x14e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat1.sdmmc5_dat1 */ + OMAP4_IOPAD(0x150, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat2.sdmmc5_dat2 */ + OMAP4_IOPAD(0x152, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat3.sdmmc5_dat3 */ + >; + }; + + gpio_led_pins: pinmux_gpio_led_pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x17e, PIN_OUTPUT | MUX_MODE3) /* kpd_col4.gpio_172 */ + OMAP4_IOPAD(0x180, PIN_OUTPUT | MUX_MODE3) /* kpd_col5.gpio_173 */ + >; + }; + + gpio_key_pins: pinmux_gpio_key_pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x1a2, PIN_INPUT | MUX_MODE3) /* sys_boot0.gpio_184 */ + >; + }; + + ks8851_irq_pins: pinmux_ks8851_irq_pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x17c, PIN_INPUT_PULLUP | MUX_MODE3) /* kpd_col3.gpio_171 */ + >; + }; + + hdmi_hpd_pins: pinmux_hdmi_hpd_pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x098, PIN_INPUT_PULLDOWN | MUX_MODE3) /* hdmi_hpd.gpio_63 */ + >; + }; + + backlight_pins: pinmux_backlight_pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x116, PIN_OUTPUT | MUX_MODE3) /* abe_dmic_din3.gpio_122 */ + >; + }; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_pins>; + clock-frequency = <400000>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + status = "okay"; +}; + +&mcspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&mcspi1_pins>; + status = "okay"; + + eth@0 { + compatible = "ks8851"; + pinctrl-names = "default"; + pinctrl-0 = <&ks8851_irq_pins>; + spi-max-frequency = <24000000>; + reg = <0>; + interrupt-parent = <&gpio6>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; /* gpio 171 */ + }; +}; + +&mmc5 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc5_pins>; + vmmc-supply = <&vbat>; + bus-width = <4>; + cd-gpios = <&gpio4 14 GPIO_ACTIVE_HIGH>; /* gpio 110 */ + status = "okay"; +}; + +&dss { + status = "okay"; +}; + +&hdmi { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&dss_hdmi_pins>; + vdda-supply = <&vdac>; + + port { + hdmi_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; +}; diff --git a/arch/arm/boot/dts/omap4-var-som-om44-wlan.dtsi b/arch/arm/boot/dts/omap4-var-som-om44-wlan.dtsi new file mode 100644 index 000000000000..cc66af419236 --- /dev/null +++ b/arch/arm/boot/dts/omap4-var-som-om44-wlan.dtsi @@ -0,0 +1,68 @@ +/* + * Copyright (C) 2014 Joachim Eastwood <manabian@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/ { + /* regulator for wl12xx on sdio4 */ + wl12xx_vmmc: wl12xx_vmmc { + pinctrl-names = "default"; + pinctrl-0 = <&wl12xx_ctrl_pins>; + compatible = "regulator-fixed"; + regulator-name = "vwl1271"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio2 11 0>; /* gpio 43 */ + startup-delay-us = <70000>; + enable-active-high; + }; +}; + +&omap4_pmx_core { + uart2_pins: pinmux_uart2_pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x118, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts.uart2_cts */ + OMAP4_IOPAD(0x11a, PIN_OUTPUT | MUX_MODE0) /* uart2_rts.uart2_rts */ + OMAP4_IOPAD(0x11c, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_rx.uart2_rx */ + OMAP4_IOPAD(0x11e, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ + >; + }; + + wl12xx_ctrl_pins: pinmux_wl12xx_ctrl_pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x062, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a17.gpio_41 (WLAN_IRQ) */ + OMAP4_IOPAD(0x064, PIN_OUTPUT | MUX_MODE3) /* gpmc_a18.gpio_42 (BT_EN) */ + OMAP4_IOPAD(0x066, PIN_OUTPUT | MUX_MODE3) /* gpmc_a19.gpio_43 (WLAN_EN) */ + >; + }; + + mmc4_pins: pinmux_mmc4_pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x154, PIN_INPUT_PULLUP | MUX_MODE1) /* mcspi4_clk.sdmmc4_clk */ + OMAP4_IOPAD(0x156, PIN_INPUT_PULLUP | MUX_MODE1) /* mcspi4_simo.sdmmc4_cmd */ + OMAP4_IOPAD(0x158, PIN_INPUT_PULLUP | MUX_MODE1) /* mcspi4_somi.sdmmc4_dat0 */ + OMAP4_IOPAD(0x15e, PIN_INPUT_PULLUP | MUX_MODE1) /* uart4_tx.sdmmc4_dat1 */ + OMAP4_IOPAD(0x15c, PIN_INPUT_PULLUP | MUX_MODE1) /* uart4_rx.sdmmc4_dat2 */ + OMAP4_IOPAD(0x15a, PIN_INPUT_PULLUP | MUX_MODE1) /* mcspi4_cs0.sdmmc4_dat3 */ + >; + }; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + status = "okay"; +}; + +&mmc4 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc4_pins>; + vmmc-supply = <&wl12xx_vmmc>; + non-removable; + bus-width = <4>; + cap-power-off-card; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/omap4-var-som-om44.dtsi b/arch/arm/boot/dts/omap4-var-som-om44.dtsi new file mode 100644 index 000000000000..062701e1a898 --- /dev/null +++ b/arch/arm/boot/dts/omap4-var-som-om44.dtsi @@ -0,0 +1,343 @@ +/* + * Copyright (C) 2014 Joachim Eastwood <manabian@gmail.com> + * Copyright (C) 2012 Variscite Ltd. - http://www.variscite.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include "omap4460.dtsi" + +/ { + model = "Variscite VAR-SOM-OM44"; + compatible = "variscite,var-som-om44", "ti,omap4460", "ti,omap4"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x40000000>; /* 1 GB */ + }; + + sound: sound@0 { + compatible = "ti,abe-twl6040"; + ti,model = "VAR-SOM-OM44"; + + ti,mclk-freq = <38400000>; + ti,mcpdm = <&mcpdm>; + ti,twl6040 = <&twl6040>; + + /* Audio routing */ + ti,audio-routing = + "Headset Stereophone", "HSOL", + "Headset Stereophone", "HSOR", + "AFML", "Line In", + "AFMR", "Line In"; + }; + + /* HS USB Host PHY on PORT 1 */ + hsusb1_phy: hsusb1_phy { + compatible = "usb-nop-xceiv"; + pinctrl-names = "default"; + pinctrl-0 = < + &hsusbb1_phy_clk_pins + &hsusbb1_phy_rst_pins + >; + + reset-gpios = <&gpio6 17 GPIO_ACTIVE_LOW>; /* gpio 177 */ + vcc-supply = <&vbat>; + + clocks = <&auxclk3_ck>; + clock-names = "main_clk"; + clock-frequency = <19200000>; + }; + + vbat: fixedregulator-vbat { + compatible = "regulator-fixed"; + regulator-name = "VBAT"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&omap4_pmx_core { + pinctrl-names = "default"; + pinctrl-0 = < + &hsusbb1_pins + >; + + twl6040_pins: pinmux_twl6040_pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x19c, PIN_OUTPUT | MUX_MODE3) /* fref_clk2_out.gpio_182 */ + OMAP4_IOPAD(0x1a0, PIN_INPUT | MUX_MODE0) /* sys_nirq2.sys_nirq2 */ + >; + }; + + mcpdm_pins: pinmux_mcpdm_pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x106, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_pdm_ul_data.abe_pdm_ul_data */ + OMAP4_IOPAD(0x108, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_pdm_dl_data.abe_pdm_dl_data */ + OMAP4_IOPAD(0x10a, PIN_INPUT_PULLUP | MUX_MODE0) /* abe_pdm_frame.abe_pdm_frame */ + OMAP4_IOPAD(0x10c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_pdm_lb_clk.abe_pdm_lb_clk */ + OMAP4_IOPAD(0x10e, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_clks.abe_clks */ + >; + }; + + tsc2004_pins: pinmux_tsc2004_pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x090, PIN_INPUT | MUX_MODE3) /* gpmc_ncs4.gpio_101 (irq) */ + OMAP4_IOPAD(0x092, PIN_OUTPUT | MUX_MODE3) /* gpmc_ncs5.gpio_102 (rst) */ + >; + }; + + uart3_pins: pinmux_uart3_pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x140, PIN_INPUT_PULLUP | MUX_MODE0) /* uart3_cts_rctx.uart3_cts_rctx */ + OMAP4_IOPAD(0x142, PIN_OUTPUT | MUX_MODE0) /* uart3_rts_sd.uart3_rts_sd */ + OMAP4_IOPAD(0x144, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ + OMAP4_IOPAD(0x146, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ + >; + }; + + hsusbb1_pins: pinmux_hsusbb1_pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x0c2, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_clk.usbb1_ulpiphy_clk */ + OMAP4_IOPAD(0x0c4, PIN_OUTPUT | MUX_MODE4) /* usbb1_ulpitll_stp.usbb1_ulpiphy_stp */ + OMAP4_IOPAD(0x0c6, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dir.usbb1_ulpiphy_dir */ + OMAP4_IOPAD(0x0c8, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_nxt.usbb1_ulpiphy_nxt */ + OMAP4_IOPAD(0x0ca, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat0.usbb1_ulpiphy_dat0 */ + OMAP4_IOPAD(0x0cc, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat1.usbb1_ulpiphy_dat1 */ + OMAP4_IOPAD(0x0ce, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat2.usbb1_ulpiphy_dat2 */ + OMAP4_IOPAD(0x0d0, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat3.usbb1_ulpiphy_dat3 */ + OMAP4_IOPAD(0x0d2, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat4.usbb1_ulpiphy_dat4 */ + OMAP4_IOPAD(0x0d4, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat5.usbb1_ulpiphy_dat5 */ + OMAP4_IOPAD(0x0d6, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat6.usbb1_ulpiphy_dat6 */ + OMAP4_IOPAD(0x0d8, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat7.usbb1_ulpiphy_dat7 */ + >; + }; + + hsusbb1_phy_rst_pins: pinmux_hsusbb1_phy_rst_pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x18c, PIN_OUTPUT | MUX_MODE3) /* kpd_row2.gpio_177 */ + >; + }; + + i2c1_pins: pinmux_i2c1_pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x122, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */ + OMAP4_IOPAD(0x124, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */ + >; + }; + + i2c3_pins: pinmux_i2c3_pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x12a, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl */ + OMAP4_IOPAD(0x12c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */ + >; + }; + + mmc1_pins: pinmux_mmc1_pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x0e2, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ + OMAP4_IOPAD(0x0e4, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ + OMAP4_IOPAD(0x0e6, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ + OMAP4_IOPAD(0x0e8, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ + OMAP4_IOPAD(0x0ea, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ + OMAP4_IOPAD(0x0ec, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ + >; + }; +}; + +&omap4_pmx_wkup { + pinctrl-names = "default"; + pinctrl-0 = < + &hsusbb1_hub_rst_pins + &lan7500_rst_pins + >; + + hsusbb1_phy_clk_pins: pinmux_hsusbb1_phy_clk_pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x058, PIN_OUTPUT | MUX_MODE0) /* fref_clk3_out */ + >; + }; + + hsusbb1_hub_rst_pins: pinmux_hsusbb1_hub_rst_pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x042, PIN_OUTPUT | MUX_MODE3) /* gpio_wk1 */ + >; + }; + + lan7500_rst_pins: pinmux_lan7500_rst_pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x040, PIN_OUTPUT | MUX_MODE3) /* gpio_wk0 */ + >; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + status = "okay"; + + clock-frequency = <400000>; + + twl: twl@48 { + reg = <0x48>; + /* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */ + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_1N cascaded to gic */ + interrupt-parent = <&gic>; + }; + + twl6040: twl@4b { + compatible = "ti,twl6040"; + reg = <0x4b>; + + pinctrl-names = "default"; + pinctrl-0 = <&twl6040_pins>; + + /* SPI = 0, IRQ# = 119, 4 = active high level-sensitive */ + interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_2N cascaded to gic */ + interrupt-parent = <&gic>; + ti,audpwron-gpio = <&gpio6 22 0>; /* gpio 182 */ + + vio-supply = <&v1v8>; + v2v1-supply = <&v2v1>; + enable-active-high; + }; +}; + +#include "twl6030.dtsi" +#include "twl6030_omap4.dtsi" + +&vusim { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; +}; + +&i2c2 { + status = "disabled"; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; + status = "okay"; + + clock-frequency = <400000>; + + touchscreen: tsc2004@48 { + compatible = "ti,tsc2004"; + reg = <0x48>; + pinctrl-names = "default"; + pinctrl-0 = <&tsc2004_pins>; + interrupt-parent = <&gpio4>; + interrupts = <5 IRQ_TYPE_LEVEL_LOW>; /* gpio 101 */ + status = "disabled"; + }; + + tmp105@49 { + compatible = "ti,tmp105"; + reg = <0x49>; + }; + + eeprom@50 { + compatible = "microchip,24c32"; + reg = <0x50>; + }; +}; + +&i2c4 { + status = "disabled"; +}; + +&mcpdm { + pinctrl-names = "default"; + pinctrl-0 = <&mcpdm_pins>; + status = "okay"; +}; + +&gpmc { + status = "disabled"; +}; + +&mcspi1 { + status = "disabled"; +}; + +&mcspi2 { + status = "disabled"; +}; + +&mcspi3 { + status = "disabled"; +}; + +&mcspi4 { + status = "disabled"; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + vmmc-supply = <&vmmc>; + bus-width = <4>; + ti,non-removable; + status = "okay"; +}; + +&mmc2 { + status = "disabled"; +}; + +&mmc3 { + status = "disabled"; +}; + +&mmc4 { + status = "disabled"; +}; + +&mmc5 { + status = "disabled"; +}; + +&uart1 { + status = "disabled"; +}; + +&uart2 { + status = "disabled"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; + status = "okay"; +}; + +&uart4 { + status = "disabled"; +}; + +&keypad { + status = "disabled"; +}; + +&twl_usb_comparator { + usb-supply = <&vusb>; +}; + +&usb_otg_hs { + interface-type = <1>; + mode = <3>; + power = <50>; +}; + +&usbhshost { + port1-mode = "ehci-phy"; +}; + +&usbhsehci { + phys = <&hsusb1_phy>; +}; diff --git a/arch/arm/boot/dts/omap4-var-som.dts b/arch/arm/boot/dts/omap4-var-som.dts deleted file mode 100644 index b41269e871dd..000000000000 --- a/arch/arm/boot/dts/omap4-var-som.dts +++ /dev/null @@ -1,96 +0,0 @@ -/* - * Copyright (C) 2012 Variscite Ltd. - http://www.variscite.com - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -/dts-v1/; - -#include "omap443x.dtsi" - -/ { - model = "Variscite OMAP4 SOM"; - compatible = "var,omap4-var_som", "ti,omap4430", "ti,omap4"; - - memory { - device_type = "memory"; - reg = <0x80000000 0x40000000>; /* 1 GB */ - }; - - vdd_eth: fixedregulator@0 { - compatible = "regulator-fixed"; - regulator-name = "VDD_ETH"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - regulator-boot-on; - }; -}; - -&i2c1 { - clock-frequency = <400000>; - - twl: twl@48 { - reg = <0x48>; - /* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */ - interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_1N cascaded to gic */ - interrupt-parent = <&gic>; - }; -}; - -#include "twl6030.dtsi" - -&i2c2 { - clock-frequency = <400000>; -}; - -&i2c3 { - clock-frequency = <400000>; - - /* - * Temperature Sensor - * http://www.ti.com/lit/ds/symlink/tmp105.pdf - */ - tmp105@49 { - compatible = "ti,tmp105"; - reg = <0x49>; - }; -}; - -&i2c4 { - clock-frequency = <400000>; -}; - -&mcspi1 { - eth@0 { - compatible = "ks8851"; - spi-max-frequency = <24000000>; - reg = <0>; - interrupt-parent = <&gpio6>; - interrupts = <11 IRQ_TYPE_LEVEL_LOW>; /* gpio line 171 */ - vdd-supply = <&vdd_eth>; - }; -}; - -&mmc1 { - vmmc-supply = <&vmmc>; - ti,bus-width = <8>; - ti,non-removable; -}; - -&mmc2 { - status = "disabled"; -}; - -&mmc3 { - status = "disabled"; -}; - -&mmc4 { - status = "disabled"; -}; - -&mmc5 { - ti,bus-width = <4>; -}; diff --git a/arch/arm/boot/dts/omap4-var-stk-om44.dts b/arch/arm/boot/dts/omap4-var-stk-om44.dts new file mode 100644 index 000000000000..56b64e618608 --- /dev/null +++ b/arch/arm/boot/dts/omap4-var-stk-om44.dts @@ -0,0 +1,17 @@ +/* + * Copyright (C) 2014 Joachim Eastwood <manabian@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +#include "omap4-var-som-om44.dtsi" +#include "omap4-var-som-om44-wlan.dtsi" +#include "omap4-var-om44customboard.dtsi" + +/ { + model = "Variscite VAR-STK-OM44"; + compatible = "variscite,var-stk-om44", "variscite,var-som-om44", "ti,omap4460", "ti,omap4"; +}; diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 649b5cd38b40..43a587e097d4 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -67,6 +67,7 @@ local-timer@48240600 { compatible = "arm,cortex-a9-twd-timer"; + clocks = <&mpu_periphclk>; reg = <0x48240600 0x20>; interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>; }; @@ -311,7 +312,7 @@ uart2: serial@4806c000 { compatible = "ti,omap4-uart"; reg = <0x4806c000 0x100>; - interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + interrupts-extended = <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart2"; clock-frequency = <48000000>; }; @@ -319,7 +320,7 @@ uart3: serial@48020000 { compatible = "ti,omap4-uart"; reg = <0x48020000 0x100>; - interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; + interrupts-extended = <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart3"; clock-frequency = <48000000>; }; @@ -327,7 +328,7 @@ uart4: serial@4806e000 { compatible = "ti,omap4-uart"; reg = <0x4806e000 0x100>; - interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; + interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart4"; clock-frequency = <48000000>; }; @@ -642,6 +643,8 @@ compatible = "ti,omap-usb2"; reg = <0x4a0ad080 0x58>; ctrl-module = <&omap_control_usb2phy>; + clocks = <&usb_phy_cm_clk32k>; + clock-names = "wkupclk"; #phy-cells = <0>; }; }; diff --git a/arch/arm/boot/dts/omap5-cm-t54.dts b/arch/arm/boot/dts/omap5-cm-t54.dts new file mode 100644 index 000000000000..b8698ca68647 --- /dev/null +++ b/arch/arm/boot/dts/omap5-cm-t54.dts @@ -0,0 +1,413 @@ +/* + * Support for CompuLab CM-T54 + */ +/dts-v1/; + +#include "omap5.dtsi" +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + model = "CompuLab CM-T54"; + compatible = "compulab,omap5-cm-t54", "ti,omap5"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x7F000000>; /* 2048 MB */ + }; + + vmmcsd_fixed: fixed-regulator-mmcsd { + compatible = "regulator-fixed"; + regulator-name = "vmmcsd_fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vwlan_pdn_fixed: fixed-regulator-vwlan-pdn { + compatible = "regulator-fixed"; + regulator-name = "vwlan_pdn_fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&ldo2_reg>; + gpio = <&gpio4 13 GPIO_ACTIVE_HIGH>; /* gpio4_109 */ + startup-delay-us = <1000>; + enable-active-high; + }; + + vwlan_fixed: fixed-regulator-vwlan { + compatible = "regulator-fixed"; + regulator-name = "vwlan_fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vwlan_pdn_fixed>; + gpio = <&gpio4 14 GPIO_ACTIVE_HIGH>; /* gpio4_110 */ + startup-delay-us = <1000>; + enable-active-high; + }; + + /* HS USB Host PHY on PORT 2 */ + hsusb2_phy: hsusb2_phy { + compatible = "usb-nop-xceiv"; + reset-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; /* gpio3_76 HUB_RESET */ + }; + + /* HS USB Host PHY on PORT 3 */ + hsusb3_phy: hsusb3_phy { + compatible = "usb-nop-xceiv"; + reset-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; /* gpio3_83 ETH_RESET */ + }; + + leds { + compatible = "gpio-leds"; + led@1 { + label = "Heartbeat"; + gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; /* gpio3_80 ACT_LED */ + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + }; +}; + +&omap5_pmx_core { + pinctrl-names = "default"; + pinctrl-0 = < + &led_gpio_pins + &usbhost_pins + >; + + led_gpio_pins: pinmux_led_gpio_pins { + pinctrl-single,pins = < + OMAP5_IOPAD(0x00b0, PIN_OUTPUT | MUX_MODE6) /* hsi2_caflag.gpio3_80 */ + >; + }; + + i2c1_pins: pinmux_i2c1_pins { + pinctrl-single,pins = < + OMAP5_IOPAD(0x01f2, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_pmic_scl */ + OMAP5_IOPAD(0x01f4, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_pmic_sda */ + >; + }; + + mmc1_pins: pinmux_mmc1_pins { + pinctrl-single,pins = < + OMAP5_IOPAD(0x01e2, PIN_INPUT_PULLUP | MUX_MODE0) /* sdcard_clk */ + OMAP5_IOPAD(0x01e4, PIN_INPUT_PULLUP | MUX_MODE0) /* sdcard_cmd */ + OMAP5_IOPAD(0x01e6, PIN_INPUT_PULLUP | MUX_MODE0) /* sdcard_data2 */ + OMAP5_IOPAD(0x01e8, PIN_INPUT_PULLUP | MUX_MODE0) /* sdcard_data3 */ + OMAP5_IOPAD(0x01ea, PIN_INPUT_PULLUP | MUX_MODE0) /* sdcard_data0 */ + OMAP5_IOPAD(0x01ec, PIN_INPUT_PULLUP | MUX_MODE0) /* sdcard_data1 */ + >; + }; + + mmc2_pins: pinmux_mmc2_pins { + pinctrl-single,pins = < + OMAP5_IOPAD(0x0040, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_clk */ + OMAP5_IOPAD(0x0042, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_cmd */ + OMAP5_IOPAD(0x0044, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_data0 */ + OMAP5_IOPAD(0x0046, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_data1 */ + OMAP5_IOPAD(0x0048, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_data2 */ + OMAP5_IOPAD(0x004a, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_data3 */ + OMAP5_IOPAD(0x004c, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_data4 */ + OMAP5_IOPAD(0x004e, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_data5 */ + OMAP5_IOPAD(0x0050, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_data6 */ + OMAP5_IOPAD(0x0052, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_data7 */ + >; + }; + + mmc3_pins: pinmux_mmc3_pins { + pinctrl-single,pins = < + OMAP5_IOPAD(0x01a4, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_clk */ + OMAP5_IOPAD(0x01a6, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_cmd */ + OMAP5_IOPAD(0x01a8, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data0 */ + OMAP5_IOPAD(0x01aa, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data1 */ + OMAP5_IOPAD(0x01ac, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data2 */ + OMAP5_IOPAD(0x01ae, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data3 */ + >; + }; + + wlan_gpios_pins: pinmux_wlan_gpios_pins { + pinctrl-single,pins = < + OMAP5_IOPAD(0x019c, PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* gpio4_109 */ + OMAP5_IOPAD(0x019e, PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* gpio4_110 */ + >; + }; + + usbhost_pins: pinmux_usbhost_pins { + pinctrl-single,pins = < + OMAP5_IOPAD(0x00c4, PIN_INPUT | MUX_MODE0) /* usbb2_hsic_strobe */ + OMAP5_IOPAD(0x00c6, PIN_INPUT | MUX_MODE0) /* usbb2_hsic_data */ + + OMAP5_IOPAD(0x01dc, PIN_INPUT | MUX_MODE0) /* usbb3_hsic_strobe */ + OMAP5_IOPAD(0x01de, PIN_INPUT | MUX_MODE0) /* usbb3_hsic_data */ + + OMAP5_IOPAD(0x00a8, PIN_OUTPUT | MUX_MODE6) /* hsi2_caready.gpio3_76 */ + OMAP5_IOPAD(0x00b6, PIN_OUTPUT | MUX_MODE6) /* hsi2_acdata.gpio3_83 */ + >; + }; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + vmmc-supply = <&ldo9_reg>; + bus-width = <4>; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>; + vmmc-supply = <&vmmcsd_fixed>; + bus-width = <8>; + ti,non-removable; +}; + +&mmc3 { + pinctrl-names = "default"; + pinctrl-0 = < + &mmc3_pins + &wlan_gpios_pins + >; + vmmc-supply = <&vwlan_fixed>; + bus-width = <4>; + ti,non-removable; +}; + +&mmc4 { + status = "disabled"; +}; + +&mmc5 { + status = "disabled"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + + clock-frequency = <400000>; + + at24@50 { + compatible = "at24,24c02"; + pagesize = <16>; + reg = <0x50>; + }; + + palmas: palmas@48 { + compatible = "ti,palmas"; + interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */ + interrupt-parent = <&gic>; + reg = <0x48>; + interrupt-controller; + #interrupt-cells = <2>; + ti,system-power-controller; + + extcon_usb3: palmas_usb { + compatible = "ti,palmas-usb-vid"; + ti,enable-vbus-detection; + ti,enable-id-detection; + ti,wakeup; + }; + + rtc { + compatible = "ti,palmas-rtc"; + interrupt-parent = <&palmas>; + interrupts = <8 IRQ_TYPE_NONE>; + }; + + palmas_pmic { + compatible = "ti,palmas-pmic"; + interrupt-parent = <&palmas>; + interrupts = <14 IRQ_TYPE_NONE>; + interrupt-name = "short-irq"; + + ti,ldo6-vibrator; + + regulators { + smps123_reg: smps123 { + /* VDD_OPP_MPU */ + regulator-name = "smps123"; + regulator-min-microvolt = < 600000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + smps45_reg: smps45 { + /* VDD_OPP_MM */ + regulator-name = "smps45"; + regulator-min-microvolt = < 600000>; + regulator-max-microvolt = <1310000>; + regulator-always-on; + regulator-boot-on; + }; + + smps6_reg: smps6 { + /* VDD_DDR3 - over VDD_SMPS6 */ + regulator-name = "smps6"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + smps7_reg: smps7 { + /* VDDS_1v8_OMAP over VDDS_1v8_MAIN */ + regulator-name = "smps7"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + smps8_reg: smps8 { + /* VDD_OPP_CORE */ + regulator-name = "smps8"; + regulator-min-microvolt = < 600000>; + regulator-max-microvolt = <1310000>; + regulator-always-on; + regulator-boot-on; + }; + + smps9_reg: smps9 { + /* VDDA_2v1_AUD over VDD_2v1 */ + regulator-name = "smps9"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + ti,smps-range = <0x80>; + regulator-always-on; + regulator-boot-on; + }; + + smps10_out2_reg: smps10_out2 { + /* VBUS_5V_OTG */ + regulator-name = "smps10_out2"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + smps10_out1_reg: smps10_out1 { + /* VBUS_5V_OTG */ + regulator-name = "smps10_out1"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + ldo1_reg: ldo1 { + /* VDDAPHY_CAM: vdda_csiport */ + regulator-name = "ldo1"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1800000>; + }; + + ldo2_reg: ldo2 { + /* VDD_3V3_WLAN */ + regulator-name = "ldo2"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <1000>; + }; + + ldo3_reg: ldo3 { + /* VCC_1V5_AUD */ + regulator-name = "ldo3"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo4_reg: ldo4 { + /* VDDAPHY_DISP: vdda_dsiport/hdmi */ + regulator-name = "ldo4"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1800000>; + }; + + ldo5_reg: ldo5 { + /* VDDA_1V8_PHY: usb/sata/hdmi.. */ + regulator-name = "ldo5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo6_reg: ldo6 { + /* VDDS_1V2_WKUP: hsic/ldo_emu_wkup */ + regulator-name = "ldo6"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo7_reg: ldo7 { + /* VDD_VPP: vpp1 */ + regulator-name = "ldo7"; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + /* Only for efuse reprograming! */ + status = "disabled"; + }; + + ldo8_reg: ldo8 { + /* VDD_3v0: Does not go anywhere */ + regulator-name = "ldo8"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + /* Unused */ + status = "disabled"; + }; + + ldo9_reg: ldo9 { + /* VCC_DV_SDIO: vdds_sdcard */ + regulator-name = "ldo9"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + }; + + ldoln_reg: ldoln { + /* VDDA_1v8_REF: vdds_osc/mm_l4per.. */ + regulator-name = "ldoln"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldousb_reg: ldousb { + /* VDDA_3V_USB: VDDA_USBHS33 */ + regulator-name = "ldousb"; + regulator-min-microvolt = <3250000>; + regulator-max-microvolt = <3250000>; + regulator-always-on; + regulator-boot-on; + }; + + regen3_reg: regen3 { + /* REGEN3 controls LDO9 supply to card */ + regulator-name = "regen3"; + regulator-always-on; + regulator-boot-on; + }; + }; + }; + }; +}; + +&usbhshost { + port2-mode = "ehci-hsic"; + port3-mode = "ehci-hsic"; +}; + +&usbhsehci { + phys = <0 &hsusb2_phy &hsusb3_phy>; +}; + +&cpu0 { + cpu0-supply = <&smps123_reg>; +}; diff --git a/arch/arm/boot/dts/omap5-sbc-t54.dts b/arch/arm/boot/dts/omap5-sbc-t54.dts new file mode 100644 index 000000000000..aa98fea3f2b3 --- /dev/null +++ b/arch/arm/boot/dts/omap5-sbc-t54.dts @@ -0,0 +1,51 @@ +/* + * Suppport for CompuLab SBC-T54 with CM-T54 + */ + +#include "omap5-cm-t54.dts" + +/ { + model = "CompuLab SBC-T54 with CM-T54"; + compatible = "compulab,omap5-sbc-t54", "compulab,omap5-cm-t54", "ti,omap5"; +}; + +&omap5_pmx_core { + i2c4_pins: pinmux_i2c4_pins { + pinctrl-single,pins = < + OMAP5_IOPAD(0x00f8, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_scl */ + OMAP5_IOPAD(0x00fa, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_sda */ + >; + }; + + mmc1_aux_pins: pinmux_mmc1_aux_pins { + pinctrl-single,pins = < + OMAP5_IOPAD(0x0174, PIN_INPUT_PULLUP | MUX_MODE6) /* gpio8_228 */ + OMAP5_IOPAD(0x0176, PIN_INPUT_PULLUP | MUX_MODE6) /* gpio8_229 */ + >; + }; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = < + &mmc1_pins + &mmc1_aux_pins + >; + cd-inverted; + wp-inverted; + cd-gpios = <&gpio8 4 GPIO_ACTIVE_LOW>; /* gpio8_228 */ + wp-gpios = <&gpio8 5 GPIO_ACTIVE_LOW>; /* gpio8_229 */ +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_pins>; + + clock-frequency = <400000>; + + at24@50 { + compatible = "at24,24c02"; + pagesize = <16>; + reg = <0x50>; + }; +}; diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index 36b4312a5e0d..e58be57984ab 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -82,6 +82,12 @@ <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>; }; + pmu { + compatible = "arm,cortex-a15-pmu"; + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; + }; + gic: interrupt-controller@48211000 { compatible = "arm,cortex-a15-gic"; interrupt-controller; @@ -810,6 +816,8 @@ compatible = "ti,omap-usb2"; reg = <0x4a084000 0x7c>; ctrl-module = <&omap_control_usb2phy>; + clocks = <&usb_phy_cm_clk32k>, <&usb_otg_ss_refclk960m>; + clock-names = "wkupclk", "refclk"; #phy-cells = <0>; }; @@ -876,6 +884,46 @@ #thermal-sensor-cells = <1>; }; + + omap_control_sata: control-phy@4a002374 { + compatible = "ti,control-phy-pipe3"; + reg = <0x4a002374 0x4>; + reg-names = "power"; + clocks = <&sys_clkin>; + clock-names = "sysclk"; + }; + + /* OCP2SCP3 */ + ocp2scp@4a090000 { + compatible = "ti,omap-ocp2scp"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x4a090000 0x20>; + ranges; + ti,hwmods = "ocp2scp3"; + sata_phy: phy@4a096000 { + compatible = "ti,phy-pipe3-sata"; + reg = <0x4A096000 0x80>, /* phy_rx */ + <0x4A096400 0x64>, /* phy_tx */ + <0x4A096800 0x40>; /* pll_ctrl */ + reg-names = "phy_rx", "phy_tx", "pll_ctrl"; + ctrl-module = <&omap_control_sata>; + clocks = <&sys_clkin>; + clock-names = "sysclk"; + #phy-cells = <0>; + }; + }; + + sata: sata@4a141100 { + compatible = "snps,dwc-ahci"; + reg = <0x4a140000 0x1100>, <0x4a141100 0x7>; + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; + phys = <&sata_phy>; + phy-names = "sata-phy"; + clocks = <&sata_ref_clk>; + ti,hwmods = "sata"; + }; + }; }; diff --git a/arch/arm/boot/dts/omap54xx-clocks.dtsi b/arch/arm/boot/dts/omap54xx-clocks.dtsi index d487fdab3921..aeb142ce8e9d 100644 --- a/arch/arm/boot/dts/omap54xx-clocks.dtsi +++ b/arch/arm/boot/dts/omap54xx-clocks.dtsi @@ -120,10 +120,8 @@ compatible = "ti,divider-clock"; clocks = <&dpll_abe_x2_ck>; ti,max-div = <31>; - ti,autoidle-shift = <8>; reg = <0x01f0>; ti,index-starts-at-one; - ti,invert-autoidle-bit; }; abe_24m_fclk: abe_24m_fclk { @@ -145,10 +143,11 @@ abe_iclk: abe_iclk { #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&abe_clk>; - clock-mult = <1>; - clock-div = <2>; + compatible = "ti,divider-clock"; + clocks = <&aess_fclk>; + ti,bit-shift = <24>; + reg = <0x0528>; + ti,dividers = <2>, <1>; }; abe_lp_clk_div: abe_lp_clk_div { @@ -164,10 +163,8 @@ compatible = "ti,divider-clock"; clocks = <&dpll_abe_x2_ck>; ti,max-div = <31>; - ti,autoidle-shift = <8>; reg = <0x01f4>; ti,index-starts-at-one; - ti,invert-autoidle-bit; }; dpll_core_ck: dpll_core_ck { @@ -188,10 +185,8 @@ compatible = "ti,divider-clock"; clocks = <&dpll_core_x2_ck>; ti,max-div = <63>; - ti,autoidle-shift = <8>; reg = <0x0150>; ti,index-starts-at-one; - ti,invert-autoidle-bit; }; c2c_fclk: c2c_fclk { @@ -215,10 +210,8 @@ compatible = "ti,divider-clock"; clocks = <&dpll_core_x2_ck>; ti,max-div = <63>; - ti,autoidle-shift = <8>; reg = <0x0138>; ti,index-starts-at-one; - ti,invert-autoidle-bit; }; dpll_core_h12x2_ck: dpll_core_h12x2_ck { @@ -226,10 +219,8 @@ compatible = "ti,divider-clock"; clocks = <&dpll_core_x2_ck>; ti,max-div = <63>; - ti,autoidle-shift = <8>; reg = <0x013c>; ti,index-starts-at-one; - ti,invert-autoidle-bit; }; dpll_core_h13x2_ck: dpll_core_h13x2_ck { @@ -237,10 +228,8 @@ compatible = "ti,divider-clock"; clocks = <&dpll_core_x2_ck>; ti,max-div = <63>; - ti,autoidle-shift = <8>; reg = <0x0140>; ti,index-starts-at-one; - ti,invert-autoidle-bit; }; dpll_core_h14x2_ck: dpll_core_h14x2_ck { @@ -248,10 +237,8 @@ compatible = "ti,divider-clock"; clocks = <&dpll_core_x2_ck>; ti,max-div = <63>; - ti,autoidle-shift = <8>; reg = <0x0144>; ti,index-starts-at-one; - ti,invert-autoidle-bit; }; dpll_core_h22x2_ck: dpll_core_h22x2_ck { @@ -259,10 +246,8 @@ compatible = "ti,divider-clock"; clocks = <&dpll_core_x2_ck>; ti,max-div = <63>; - ti,autoidle-shift = <8>; reg = <0x0154>; ti,index-starts-at-one; - ti,invert-autoidle-bit; }; dpll_core_h23x2_ck: dpll_core_h23x2_ck { @@ -270,10 +255,8 @@ compatible = "ti,divider-clock"; clocks = <&dpll_core_x2_ck>; ti,max-div = <63>; - ti,autoidle-shift = <8>; reg = <0x0158>; ti,index-starts-at-one; - ti,invert-autoidle-bit; }; dpll_core_h24x2_ck: dpll_core_h24x2_ck { @@ -281,10 +264,8 @@ compatible = "ti,divider-clock"; clocks = <&dpll_core_x2_ck>; ti,max-div = <63>; - ti,autoidle-shift = <8>; reg = <0x015c>; ti,index-starts-at-one; - ti,invert-autoidle-bit; }; dpll_core_m2_ck: dpll_core_m2_ck { @@ -292,10 +273,8 @@ compatible = "ti,divider-clock"; clocks = <&dpll_core_ck>; ti,max-div = <31>; - ti,autoidle-shift = <8>; reg = <0x0130>; ti,index-starts-at-one; - ti,invert-autoidle-bit; }; dpll_core_m3x2_ck: dpll_core_m3x2_ck { @@ -303,10 +282,8 @@ compatible = "ti,divider-clock"; clocks = <&dpll_core_x2_ck>; ti,max-div = <31>; - ti,autoidle-shift = <8>; reg = <0x0134>; ti,index-starts-at-one; - ti,invert-autoidle-bit; }; iva_dpll_hs_clk_div: iva_dpll_hs_clk_div { @@ -335,10 +312,8 @@ compatible = "ti,divider-clock"; clocks = <&dpll_iva_x2_ck>; ti,max-div = <63>; - ti,autoidle-shift = <8>; reg = <0x01b8>; ti,index-starts-at-one; - ti,invert-autoidle-bit; }; dpll_iva_h12x2_ck: dpll_iva_h12x2_ck { @@ -346,10 +321,8 @@ compatible = "ti,divider-clock"; clocks = <&dpll_iva_x2_ck>; ti,max-div = <63>; - ti,autoidle-shift = <8>; reg = <0x01bc>; ti,index-starts-at-one; - ti,invert-autoidle-bit; }; mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div { @@ -372,10 +345,8 @@ compatible = "ti,divider-clock"; clocks = <&dpll_mpu_ck>; ti,max-div = <31>; - ti,autoidle-shift = <8>; reg = <0x0170>; ti,index-starts-at-one; - ti,invert-autoidle-bit; }; per_dpll_hs_clk_div: per_dpll_hs_clk_div { @@ -642,10 +613,8 @@ compatible = "ti,divider-clock"; clocks = <&dpll_per_x2_ck>; ti,max-div = <63>; - ti,autoidle-shift = <8>; reg = <0x0158>; ti,index-starts-at-one; - ti,invert-autoidle-bit; }; dpll_per_h12x2_ck: dpll_per_h12x2_ck { @@ -653,10 +622,8 @@ compatible = "ti,divider-clock"; clocks = <&dpll_per_x2_ck>; ti,max-div = <63>; - ti,autoidle-shift = <8>; reg = <0x015c>; ti,index-starts-at-one; - ti,invert-autoidle-bit; }; dpll_per_h14x2_ck: dpll_per_h14x2_ck { @@ -664,10 +631,8 @@ compatible = "ti,divider-clock"; clocks = <&dpll_per_x2_ck>; ti,max-div = <63>; - ti,autoidle-shift = <8>; reg = <0x0164>; ti,index-starts-at-one; - ti,invert-autoidle-bit; }; dpll_per_m2_ck: dpll_per_m2_ck { @@ -675,10 +640,8 @@ compatible = "ti,divider-clock"; clocks = <&dpll_per_ck>; ti,max-div = <31>; - ti,autoidle-shift = <8>; reg = <0x0150>; ti,index-starts-at-one; - ti,invert-autoidle-bit; }; dpll_per_m2x2_ck: dpll_per_m2x2_ck { @@ -686,10 +649,8 @@ compatible = "ti,divider-clock"; clocks = <&dpll_per_x2_ck>; ti,max-div = <31>; - ti,autoidle-shift = <8>; reg = <0x0150>; ti,index-starts-at-one; - ti,invert-autoidle-bit; }; dpll_per_m3x2_ck: dpll_per_m3x2_ck { @@ -697,10 +658,8 @@ compatible = "ti,divider-clock"; clocks = <&dpll_per_x2_ck>; ti,max-div = <31>; - ti,autoidle-shift = <8>; reg = <0x0154>; ti,index-starts-at-one; - ti,invert-autoidle-bit; }; dpll_unipro1_ck: dpll_unipro1_ck { @@ -723,10 +682,8 @@ compatible = "ti,divider-clock"; clocks = <&dpll_unipro1_ck>; ti,max-div = <127>; - ti,autoidle-shift = <8>; reg = <0x0210>; ti,index-starts-at-one; - ti,invert-autoidle-bit; }; dpll_unipro2_ck: dpll_unipro2_ck { @@ -749,10 +706,8 @@ compatible = "ti,divider-clock"; clocks = <&dpll_unipro2_ck>; ti,max-div = <127>; - ti,autoidle-shift = <8>; reg = <0x01d0>; ti,index-starts-at-one; - ti,invert-autoidle-bit; }; dpll_usb_ck: dpll_usb_ck { @@ -775,10 +730,8 @@ compatible = "ti,divider-clock"; clocks = <&dpll_usb_ck>; ti,max-div = <127>; - ti,autoidle-shift = <8>; reg = <0x0190>; ti,index-starts-at-one; - ti,invert-autoidle-bit; }; func_128m_clk: func_128m_clk { @@ -851,6 +804,7 @@ clocks = <&dpll_per_h12x2_ck>; ti,bit-shift = <8>; reg = <0x1420>; + ti,set-rate-parent; }; dss_sys_clk: dss_sys_clk { diff --git a/arch/arm/boot/dts/orion5x-lacie-d2-network.dts b/arch/arm/boot/dts/orion5x-lacie-d2-network.dts new file mode 100644 index 000000000000..c701e8d16bbb --- /dev/null +++ b/arch/arm/boot/dts/orion5x-lacie-d2-network.dts @@ -0,0 +1,236 @@ +/* + * Copyright (C) 2014 Thomas Petazzoni <thomas.petazzoni@free-electrons.com> + * Copyright (C) 2009 Simon Guinot <sguinot@lacie.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include "orion5x-mv88f5182.dtsi" + +/ { + model = "LaCie d2 Network"; + compatible = "lacie,d2-network", "marvell,orion5x-88f5182", "marvell,orion5x"; + + memory { + reg = <0x00000000 0x4000000>; /* 64 MB */ + }; + + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk"; + linux,stdout-path = &uart0; + }; + + soc { + ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>, + <MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>, + <MBUS_ID(0x01, 0x0f) 0 0xfff80000 0x80000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = <&pmx_buttons>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + front_button { + label = "Front Push Button"; + linux,code = <KEY_POWER>; + gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>; + }; + + power_rocker_sw_on { + label = "Power rocker switch (on|auto)"; + linux,input-type = <5>; /* EV_SW */ + linux,code = <1>; /* D2NET_SWITCH_POWER_ON */ + gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>; + }; + + power_rocker_sw_off { + label = "Power rocker switch (auto|off)"; + linux,input-type = <5>; /* EV_SW */ + linux,code = <2>; /* D2NET_SWITCH_POWER_OFF */ + gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pmx_sata0_power &pmx_sata1_power>; + pinctrl-names = "default"; + + sata0_power: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "SATA0 Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio0 3 GPIO_ACTIVE_HIGH>; + }; + + sata1_power: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "SATA1 Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&devbus_bootcs { + status = "okay"; + + devbus,keep-config; + + /* + * Currently the MTD code does not recognize the MX29LV400CBCT + * as a bottom-type device. This could cause risks of + * accidentally erasing critical flash sectors. We thus define + * a single, write-protected partition covering the whole + * flash. TODO: once the flash part TOP/BOTTOM detection + * issue is sorted out in the MTD code, break this into at + * least three partitions: 'u-boot code', 'u-boot environment' + * and 'whatever is left'. + */ + flash@0 { + compatible = "cfi-flash"; + reg = <0 0x80000>; + bank-width = <1>; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "Full512Kb"; + reg = <0 0x80000>; + read-only; + }; + }; +}; + +&mdio { + status = "okay"; + + ethphy: ethernet-phy { + reg = <8>; + }; +}; + +&ehci0 { + status = "okay"; +}; + +ð { + status = "okay"; + + ethernet-port@0 { + phy-handle = <ðphy>; + }; +}; + +&i2c { + status = "okay"; + clock-frequency = <100000>; + #address-cells = <1>; + + rtc@32 { + compatible = "ricoh,rs5c372b"; + reg = <0x32>; + }; + + fan@3e { + compatible = "gmt,g762"; + reg = <0x3e>; + + /* Not enough HW info */ + status = "disabled"; + }; + + eeprom@50 { + compatible = "atmel,24c08"; + reg = <0x50>; + }; +}; + +&pinctrl { + pinctrl-0 = <&pmx_leds &pmx_board_id &pmx_fan_fail>; + pinctrl-names = "default"; + + pmx_board_id: pmx-board-id { + marvell,pins = "mpp0", "mpp1", "mpp2"; + marvell,function = "gpio"; + }; + + pmx_buttons: pmx-buttons { + marvell,pins = "mpp8", "mpp9", "mpp18"; + marvell,function = "gpio"; + }; + + pmx_fan_fail: pmx-fan-fail { + marvell,pins = "mpp5"; + marvell,function = "gpio"; + }; + + /* + * MPP6: Red front LED + * MPP16: Blue front LED blink control + */ + pmx_leds: pmx-leds { + marvell,pins = "mpp6", "mpp16"; + marvell,function = "gpio"; + }; + + pmx_sata0_led_active: pmx-sata0-led-active { + marvell,pins = "mpp14"; + marvell,function = "sata0"; + }; + + pmx_sata0_power: pmx-sata0-power { + marvell,pins = "mpp3"; + marvell,function = "gpio"; + }; + + pmx_sata1_led_active: pmx-sata1-led-active { + marvell,pins = "mpp15"; + marvell,function = "sata1"; + }; + + pmx_sata1_power: pmx-sata1-power { + marvell,pins = "mpp12"; + marvell,function = "gpio"; + }; + + /* + * Non MPP GPIOs: + * GPIO 22: USB port 1 fuse (0 = Fail, 1 = Ok) + * GPIO 23: Blue front LED off + * GPIO 24: Inhibit board power off (0 = Disabled, 1 = Enabled) + */ +}; + +&sata { + pinctrl-0 = <&pmx_sata0_led_active + &pmx_sata1_led_active>; + pinctrl-names = "default"; + status = "okay"; + nr-ports = <2>; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts index 5ed6c1376901..89ff404a528c 100644 --- a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts +++ b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts @@ -6,8 +6,19 @@ * warranty of any kind, whether express or implied. */ +/* + * TODO: add Orion USB device port init when kernel.org support is added. + * TODO: add flash write support: see below. + * TODO: add power-off support. + * TODO: add I2C EEPROM support. + */ + /dts-v1/; -/include/ "orion5x.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include "orion5x-mv88f5182.dtsi" / { model = "LaCie Ethernet Disk mini V2"; @@ -19,49 +30,84 @@ chosen { bootargs = "console=ttyS0,115200n8 earlyprintk"; + linux,stdout-path = &uart0; }; - ocp@f1000000 { - serial@12000 { - clock-frequency = <166666667>; - status = "okay"; - }; - - sata@80000 { - status = "okay"; - nr-ports = <2>; - }; + soc { + ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>, + <MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>, + <MBUS_ID(0x01, 0x0f) 0 0xfff80000 0x80000>; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; + pinctrl-0 = <&pmx_power_button>; + pinctrl-names = "default"; #address-cells = <1>; #size-cells = <0>; button@1 { label = "Power-on Switch"; - linux,code = <116>; /* KEY_POWER */ - gpios = <&gpio0 18 0>; + linux,code = <KEY_POWER>; + gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>; }; }; - gpio_leds { + gpio-leds { compatible = "gpio-leds"; + pinctrl-0 = <&pmx_power_led>; + pinctrl-names = "default"; led@1 { label = "power:blue"; - gpios = <&gpio0 16 1>; + gpios = <&gpio0 16 GPIO_ACTIVE_LOW>; }; }; }; -&mdio { +&devbus_bootcs { status = "okay"; - ethphy: ethernet-phy { - reg = <8>; + /* Read parameters */ + devbus,bus-width = <8>; + devbus,turn-off-ps = <90000>; + devbus,badr-skew-ps = <0>; + devbus,acc-first-ps = <186000>; + devbus,acc-next-ps = <186000>; + + /* Write parameters */ + devbus,wr-high-ps = <90000>; + devbus,wr-low-ps = <90000>; + devbus,ale-wr-ps = <90000>; + + /* + * Currently the MTD code does not recognize the MX29LV400CBCT + * as a bottom-type device. This could cause risks of + * accidentally erasing critical flash sectors. We thus define + * a single, write-protected partition covering the whole + * flash. TODO: once the flash part TOP/BOTTOM detection + * issue is sorted out in the MTD code, break this into at + * least three partitions: 'u-boot code', 'u-boot environment' + * and 'whatever is left'. + */ + flash@0 { + compatible = "cfi-flash"; + reg = <0 0x80000>; + bank-width = <1>; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "Full512Kb"; + reg = <0 0x80000>; + read-only; + }; }; }; +&ehci0 { + status = "okay"; +}; + ð { status = "okay"; @@ -69,3 +115,60 @@ phy-handle = <ðphy>; }; }; + +&i2c { + status = "okay"; + clock-frequency = <100000>; + #address-cells = <1>; + + rtc@32 { + compatible = "ricoh,rs5c372a"; + reg = <0x32>; + interrupt-parent = <&gpio0>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&mdio { + status = "okay"; + + ethphy: ethernet-phy { + reg = <8>; + }; +}; + +&pinctrl { + pinctrl-0 = <&pmx_rtc &pmx_power_led_ctrl>; + pinctrl-names = "default"; + + pmx_power_button: pmx-power-button { + marvell,pins = "mpp18"; + marvell,function = "gpio"; + }; + + pmx_power_led: pmx-power-led { + marvell,pins = "mpp16"; + marvell,function = "gpio"; + }; + + pmx_power_led_ctrl: pmx-power-led-ctrl { + marvell,pins = "mpp17"; + marvell,function = "gpio"; + }; + + pmx_rtc: pmx-rtc { + marvell,pins = "mpp3"; + marvell,function = "gpio"; + }; +}; + +&sata { + pinctrl-0 = <&pmx_sata0 &pmx_sata1>; + pinctrl-names = "default"; + status = "okay"; + nr-ports = <2>; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/orion5x-maxtor-shared-storage-2.dts b/arch/arm/boot/dts/orion5x-maxtor-shared-storage-2.dts new file mode 100644 index 000000000000..ff3484904294 --- /dev/null +++ b/arch/arm/boot/dts/orion5x-maxtor-shared-storage-2.dts @@ -0,0 +1,178 @@ +/* + * Copyright (C) 2014 Thomas Petazzoni <thomas.petazzoni@free-electrons.com> + * Copyright (C) Sylver Bruneau <sylver.bruneau@googlemail.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include "orion5x-mv88f5182.dtsi" + +/ { + model = "Maxtor Shared Storage II"; + compatible = "maxtor,shared-storage-2", "marvell,orion5x-88f5182", "marvell,orion5x"; + + memory { + reg = <0x00000000 0x4000000>; /* 64 MB */ + }; + + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk"; + linux,stdout-path = &uart0; + }; + + soc { + ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>, + <MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>, + <MBUS_ID(0x01, 0x0f) 0 0xff800000 0x40000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = <&pmx_buttons>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + power { + label = "Power"; + linux,code = <KEY_POWER>; + gpios = <&gpio0 11 GPIO_ACTIVE_LOW>; + }; + + reset { + label = "Reset"; + linux,code = <KEY_RESTART>; + gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&devbus_bootcs { + status = "okay"; + + devbus,keep-config; + + /* + * Currently the MTD code does not recognize the MX29LV400CBCT + * as a bottom-type device. This could cause risks of + * accidentally erasing critical flash sectors. We thus define + * a single, write-protected partition covering the whole + * flash. TODO: once the flash part TOP/BOTTOM detection + * issue is sorted out in the MTD code, break this into at + * least three partitions: 'u-boot code', 'u-boot environment' + * and 'whatever is left'. + */ + flash@0 { + compatible = "cfi-flash"; + reg = <0 0x40000>; + bank-width = <1>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +&mdio { + status = "okay"; + + ethphy: ethernet-phy { + reg = <8>; + }; +}; + +&ehci0 { + status = "okay"; +}; + +ð { + status = "okay"; + + ethernet-port@0 { + phy-handle = <ðphy>; + }; +}; + +&i2c { + status = "okay"; + clock-frequency = <100000>; + #address-cells = <1>; + + rtc@68 { + compatible = "st,m41t81"; + reg = <0x68>; + pinctrl-0 = <&pmx_rtc>; + pinctrl-names = "default"; + interrupt-parent = <&gpio0>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&pinctrl { + pinctrl-0 = <&pmx_leds &pmx_misc>; + pinctrl-names = "default"; + + pmx_buttons: pmx-buttons { + marvell,pins = "mpp11", "mpp12"; + marvell,function = "gpio"; + }; + + /* + * MPP0: Power LED + * MPP1: Error LED + */ + pmx_leds: pmx-leds { + marvell,pins = "mpp0", "mpp1"; + marvell,function = "gpio"; + }; + + /* + * MPP4: HDD ind. (Single/Dual) + * MPP5: HD0 5V control + * MPP6: HD0 12V control + * MPP7: HD1 5V control + * MPP8: HD1 12V control + */ + pmx_misc: pmx-misc { + marvell,pins = "mpp4", "mpp5", "mpp6", "mpp7", "mpp8", "mpp10"; + marvell,function = "gpio"; + }; + + pmx_rtc: pmx-rtc { + marvell,pins = "mpp3"; + marvell,function = "gpio"; + }; + + pmx_sata0_led_active: pmx-sata0-led-active { + marvell,pins = "mpp14"; + marvell,function = "sata0"; + }; + + pmx_sata1_led_active: pmx-sata1-led-active { + marvell,pins = "mpp15"; + marvell,function = "sata1"; + }; + + /* + * Non MPP GPIOs: + * GPIO 22: USB port 1 fuse (0 = Fail, 1 = Ok) + * GPIO 23: Blue front LED off + * GPIO 24: Inhibit board power off (0 = Disabled, 1 = Enabled) + */ +}; + +&sata { + pinctrl-0 = <&pmx_sata0_led_active + &pmx_sata1_led_active>; + pinctrl-names = "default"; + status = "okay"; + nr-ports = <2>; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/orion5x-mv88f5182.dtsi b/arch/arm/boot/dts/orion5x-mv88f5182.dtsi new file mode 100644 index 000000000000..d1ed71c60209 --- /dev/null +++ b/arch/arm/boot/dts/orion5x-mv88f5182.dtsi @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2014 Thomas Petazzoni <thomas.petazzoni@free-electrons.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include "orion5x.dtsi" + +/ { + compatible = "marvell,orion5x-88f5182", "marvell,orion5x"; + + soc { + compatible = "marvell,orion5x-88f5182-mbus", "simple-bus"; + + internal-regs { + pinctrl: pinctrl@10000 { + compatible = "marvell,88f5182-pinctrl"; + reg = <0x10000 0x8>, <0x10050 0x4>; + + pmx_sata0: pmx-sata0 { + marvell,pins = "mpp12", "mpp14"; + marvell,function = "sata0"; + }; + + pmx_sata1: pmx-sata1 { + marvell,pins = "mpp13", "mpp15"; + marvell,function = "sata1"; + }; + }; + + core_clk: core-clocks@10030 { + compatible = "marvell,mv88f5182-core-clock"; + reg = <0x10010 0x4>; + #clock-cells = <1>; + }; + + mbusc: mbus-controller@20000 { + compatible = "marvell,mbus-controller"; + reg = <0x20000 0x100>, <0x1500 0x20>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/orion5x-rd88f5182-nas.dts b/arch/arm/boot/dts/orion5x-rd88f5182-nas.dts new file mode 100644 index 000000000000..6fb052507b36 --- /dev/null +++ b/arch/arm/boot/dts/orion5x-rd88f5182-nas.dts @@ -0,0 +1,177 @@ +/* + * Copyright (C) 2014 Thomas Petazzoni <thomas.petazzoni@free-electrons.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include "orion5x-mv88f5182.dtsi" + +/ { + model = "Marvell Reference Design 88F5182 NAS"; + compatible = "marvell,rd-88f5182-nas", "marvell,orion5x-88f5182", "marvell,orion5x"; + + memory { + reg = <0x00000000 0x4000000>; /* 64 MB */ + }; + + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk"; + linux,stdout-path = &uart0; + }; + + soc { + ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>, + <MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>, + <MBUS_ID(0x01, 0x0f) 0 0xf4000000 0x80000>, + <MBUS_ID(0x01, 0x1d) 0 0xfc000000 0x1000000>; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = <&pmx_debug_led>; + pinctrl-names = "default"; + + led@0 { + label = "rd88f5182:cpu"; + linux,default-trigger = "heartbeat"; + gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&devbus_bootcs { + status = "okay"; + + /* Read parameters */ + devbus,bus-width = <8>; + devbus,turn-off-ps = <90000>; + devbus,badr-skew-ps = <0>; + devbus,acc-first-ps = <186000>; + devbus,acc-next-ps = <186000>; + + /* Write parameters */ + devbus,wr-high-ps = <90000>; + devbus,wr-low-ps = <90000>; + devbus,ale-wr-ps = <90000>; + + flash@0 { + compatible = "cfi-flash"; + reg = <0 0x80000>; + bank-width = <1>; + }; +}; + +&devbus_cs1 { + status = "okay"; + + /* Read parameters */ + devbus,bus-width = <8>; + devbus,turn-off-ps = <90000>; + devbus,badr-skew-ps = <0>; + devbus,acc-first-ps = <186000>; + devbus,acc-next-ps = <186000>; + + /* Write parameters */ + devbus,wr-high-ps = <90000>; + devbus,wr-low-ps = <90000>; + devbus,ale-wr-ps = <90000>; + + flash@0 { + compatible = "cfi-flash"; + reg = <0 0x1000000>; + bank-width = <1>; + }; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +ð { + status = "okay"; + + ethernet-port@0 { + phy-handle = <ðphy>; + }; +}; + +&i2c { + status = "okay"; + clock-frequency = <100000>; + #address-cells = <1>; + + rtc@68 { + pinctrl-0 = <&pmx_rtc>; + pinctrl-names = "default"; + compatible = "dallas,ds1338"; + reg = <0x68>; + }; +}; + +&mdio { + status = "okay"; + + ethphy: ethernet-phy { + reg = <8>; + }; +}; + +&pinctrl { + pinctrl-0 = <&pmx_reset_switch &pmx_misc_gpios + &pmx_pci_gpios>; + pinctrl-names = "default"; + + /* + * MPP[20] PCI Clock to MV88F5182 + * MPP[21] PCI Clock to mini PCI CON11 + * MPP[22] USB 0 over current indication + * MPP[23] USB 1 over current indication + * MPP[24] USB 1 over current enable + * MPP[25] USB 0 over current enable + */ + + pmx_debug_led: pmx-debug_led { + marvell,pins = "mpp0"; + marvell,function = "gpio"; + }; + + pmx_reset_switch: pmx-reset-switch { + marvell,pins = "mpp1"; + marvell,function = "gpio"; + }; + + pmx_rtc: pmx-rtc { + marvell,pins = "mpp3"; + marvell,function = "gpio"; + }; + + pmx_misc_gpios: pmx-misc-gpios { + marvell,pins = "mpp4", "mpp5"; + marvell,function = "gpio"; + }; + + pmx_pci_gpios: pmx-pci-gpios { + marvell,pins = "mpp6", "mpp7"; + marvell,function = "gpio"; + }; +}; + +&sata { + pinctrl-0 = <&pmx_sata0 &pmx_sata1>; + pinctrl-names = "default"; + status = "okay"; + nr-ports = <2>; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/orion5x.dtsi b/arch/arm/boot/dts/orion5x.dtsi index 174d89241f70..75cd01bd6024 100644 --- a/arch/arm/boot/dts/orion5x.dtsi +++ b/arch/arm/boot/dts/orion5x.dtsi @@ -6,7 +6,9 @@ * warranty of any kind, whether express or implied. */ -/include/ "skeleton.dtsi" +#include "skeleton.dtsi" + +#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) / { model = "Marvell Orion5x SoC"; @@ -17,149 +19,214 @@ gpio0 = &gpio0; }; - intc: interrupt-controller { - compatible = "marvell,orion-intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0xf1020200 0x08>; - }; - - ocp@f1000000 { - compatible = "simple-bus"; - ranges = <0x00000000 0xf1000000 0x4000000 - 0xf2200000 0xf2200000 0x0000800>; - #address-cells = <1>; + soc { + #address-cells = <2>; #size-cells = <1>; + controller = <&mbusc>; - gpio0: gpio@10100 { - compatible = "marvell,orion-gpio"; - #gpio-cells = <2>; - gpio-controller; - reg = <0x10100 0x40>; - ngpios = <32>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <6>, <7>, <8>, <9>; - }; - - spi@10600 { - compatible = "marvell,orion-spi"; + devbus_bootcs: devbus-bootcs { + compatible = "marvell,orion-devbus"; + reg = <MBUS_ID(0xf0, 0x01) 0x1046C 0x4>; + ranges = <0 MBUS_ID(0x01, 0x0f) 0 0xffffffff>; #address-cells = <1>; - #size-cells = <0>; - cell-index = <0>; - reg = <0x10600 0x28>; + #size-cells = <1>; + clocks = <&core_clk 0>; status = "disabled"; }; - i2c@11000 { - compatible = "marvell,mv64xxx-i2c"; - reg = <0x11000 0x20>; + devbus_cs0: devbus-cs0 { + compatible = "marvell,orion-devbus"; + reg = <MBUS_ID(0xf0, 0x01) 0x1045C 0x4>; + ranges = <0 MBUS_ID(0x01, 0x1e) 0 0xffffffff>; #address-cells = <1>; - #size-cells = <0>; - interrupts = <5>; - clock-frequency = <100000>; + #size-cells = <1>; + clocks = <&core_clk 0>; status = "disabled"; }; - serial@12000 { - compatible = "ns16550a"; - reg = <0x12000 0x100>; - reg-shift = <2>; - interrupts = <3>; - /* set clock-frequency in board dts */ + devbus_cs1: devbus-cs1 { + compatible = "marvell,orion-devbus"; + reg = <MBUS_ID(0xf0, 0x01) 0x10460 0x4>; + ranges = <0 MBUS_ID(0x01, 0x1d) 0 0xffffffff>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&core_clk 0>; status = "disabled"; }; - serial@12100 { - compatible = "ns16550a"; - reg = <0x12100 0x100>; - reg-shift = <2>; - interrupts = <4>; - /* set clock-frequency in board dts */ + devbus_cs2: devbus-cs2 { + compatible = "marvell,orion-devbus"; + reg = <MBUS_ID(0xf0, 0x01) 0x10464 0x4>; + ranges = <0 MBUS_ID(0x01, 0x1b) 0 0xffffffff>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&core_clk 0>; status = "disabled"; }; - wdt@20300 { - compatible = "marvell,orion-wdt"; - reg = <0x20300 0x28>; - status = "okay"; - }; + internal-regs { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; + + gpio0: gpio@10100 { + compatible = "marvell,orion-gpio"; + #gpio-cells = <2>; + gpio-controller; + reg = <0x10100 0x40>; + ngpios = <32>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <6>, <7>, <8>, <9>; + }; - ehci@50000 { - compatible = "marvell,orion-ehci"; - reg = <0x50000 0x1000>; - interrupts = <17>; - status = "disabled"; - }; + spi: spi@10600 { + compatible = "marvell,orion-spi"; + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + reg = <0x10600 0x28>; + status = "disabled"; + }; - xor@60900 { - compatible = "marvell,orion-xor"; - reg = <0x60900 0x100 - 0x60b00 0x100>; - status = "okay"; + i2c: i2c@11000 { + compatible = "marvell,mv64xxx-i2c"; + reg = <0x11000 0x20>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <5>; + clocks = <&core_clk 0>; + status = "disabled"; + }; - xor00 { - interrupts = <30>; - dmacap,memcpy; - dmacap,xor; + uart0: serial@12000 { + compatible = "ns16550a"; + reg = <0x12000 0x100>; + reg-shift = <2>; + interrupts = <3>; + clocks = <&core_clk 0>; + status = "disabled"; }; - xor01 { - interrupts = <31>; - dmacap,memcpy; - dmacap,xor; - dmacap,memset; + + uart1: serial@12100 { + compatible = "ns16550a"; + reg = <0x12100 0x100>; + reg-shift = <2>; + interrupts = <4>; + clocks = <&core_clk 0>; + status = "disabled"; }; - }; - eth: ethernet-controller@72000 { - compatible = "marvell,orion-eth"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x72000 0x4000>; - marvell,tx-checksum-limit = <1600>; - status = "disabled"; + bridge_intc: bridge-interrupt-ctrl@20110 { + compatible = "marvell,orion-bridge-intc"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x20110 0x8>; + interrupts = <0>; + marvell,#interrupts = <4>; + }; - ethernet-port@0 { - compatible = "marvell,orion-eth-port"; - reg = <0>; - /* overwrite MAC address in bootloader */ - local-mac-address = [00 00 00 00 00 00]; - /* set phy-handle property in board file */ + intc: interrupt-controller@20200 { + compatible = "marvell,orion-intc"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x20200 0x08>; }; - }; - mdio: mdio-bus@72004 { - compatible = "marvell,orion-mdio"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x72004 0x84>; - interrupts = <22>; - status = "disabled"; + timer: timer@20300 { + compatible = "marvell,orion-timer"; + reg = <0x20300 0x20>; + interrupt-parent = <&bridge_intc>; + interrupts = <1>, <2>; + clocks = <&core_clk 0>; + }; - /* add phy nodes in board file */ - }; + wdt: wdt@20300 { + compatible = "marvell,orion-wdt"; + reg = <0x20300 0x28>; + interrupt-parent = <&bridge_intc>; + interrupts = <3>; + status = "okay"; + }; - sata@80000 { - compatible = "marvell,orion-sata"; - reg = <0x80000 0x5000>; - interrupts = <29>; - status = "disabled"; + ehci0: ehci@50000 { + compatible = "marvell,orion-ehci"; + reg = <0x50000 0x1000>; + interrupts = <17>; + status = "disabled"; + }; + + xor: dma-controller@60900 { + compatible = "marvell,orion-xor"; + reg = <0x60900 0x100 + 0x60b00 0x100>; + status = "okay"; + + xor00 { + interrupts = <30>; + dmacap,memcpy; + dmacap,xor; + }; + xor01 { + interrupts = <31>; + dmacap,memcpy; + dmacap,xor; + dmacap,memset; + }; + }; + + eth: ethernet-controller@72000 { + compatible = "marvell,orion-eth"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x72000 0x4000>; + marvell,tx-checksum-limit = <1600>; + status = "disabled"; + + ethport: ethernet-port@0 { + compatible = "marvell,orion-eth-port"; + reg = <0>; + interrupts = <21>; + /* overwrite MAC address in bootloader */ + local-mac-address = [00 00 00 00 00 00]; + /* set phy-handle property in board file */ + }; + }; + + mdio: mdio-bus@72004 { + compatible = "marvell,orion-mdio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x72004 0x84>; + interrupts = <22>; + status = "disabled"; + + /* add phy nodes in board file */ + }; + + sata: sata@80000 { + compatible = "marvell,orion-sata"; + reg = <0x80000 0x5000>; + interrupts = <29>; + status = "disabled"; + }; + + ehci1: ehci@a0000 { + compatible = "marvell,orion-ehci"; + reg = <0xa0000 0x1000>; + interrupts = <12>; + status = "disabled"; + }; }; - crypto@90000 { + cesa: crypto@90000 { compatible = "marvell,orion-crypto"; - reg = <0x90000 0x10000>, - <0xf2200000 0x800>; + reg = <MBUS_ID(0xf0, 0x01) 0x90000 0x10000>, + <MBUS_ID(0x09, 0x00) 0x0 0x800>; reg-names = "regs", "sram"; interrupts = <28>; status = "okay"; }; - - ehci@a0000 { - compatible = "marvell,orion-ehci"; - reg = <0xa0000 0x1000>; - interrupts = <12>; - status = "disabled"; - }; }; }; diff --git a/arch/arm/boot/dts/prima2.dtsi b/arch/arm/boot/dts/prima2.dtsi index 1e82571d6823..963b7e54ab15 100644 --- a/arch/arm/boot/dts/prima2.dtsi +++ b/arch/arm/boot/dts/prima2.dtsi @@ -48,7 +48,7 @@ ranges = <0x40000000 0x40000000 0x80000000>; l2-cache-controller@80040000 { - compatible = "arm,pl310-cache", "sirf,prima2-pl310-cache"; + compatible = "arm,pl310-cache"; reg = <0x80040000 0x1000>; interrupts = <59>; arm,tag-latency = <1 1 1>; @@ -201,6 +201,7 @@ compatible = "sirf,prima2-tick"; reg = <0xb0020000 0x1000>; interrupts = <0>; + clocks = <&clks 11>; }; nand@b0030000 { @@ -313,8 +314,9 @@ reg = <0xb00d0000 0x10000>; interrupts = <15>; sirf,spi-num-chipselects = <1>; - sirf,spi-dma-rx-channel = <25>; - sirf,spi-dma-tx-channel = <20>; + dmas = <&dmac1 9>, + <&dmac1 4>; + dma-names = "rx", "tx"; #address-cells = <1>; #size-cells = <0>; clocks = <&clks 19>; @@ -327,8 +329,9 @@ reg = <0xb0170000 0x10000>; interrupts = <16>; sirf,spi-num-chipselects = <1>; - sirf,spi-dma-rx-channel = <12>; - sirf,spi-dma-tx-channel = <13>; + dmas = <&dmac0 12>, + <&dmac0 13>; + dma-names = "rx", "tx"; #address-cells = <1>; #size-cells = <0>; clocks = <&clks 20>; diff --git a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts new file mode 100644 index 000000000000..7c2441d526bc --- /dev/null +++ b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts @@ -0,0 +1,16 @@ +#include "qcom-apq8064-v2.0.dtsi" + +/ { + model = "Qualcomm APQ8064/IFC6410"; + compatible = "qcom,apq8064-ifc6410", "qcom,apq8064"; + + soc { + gsbi@16600000 { + status = "ok"; + qcom,mode = <GSBI_PROT_I2C_UART>; + serial@16640000 { + status = "ok"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom-apq8064-v2.0.dtsi b/arch/arm/boot/dts/qcom-apq8064-v2.0.dtsi new file mode 100644 index 000000000000..935c3945fc5e --- /dev/null +++ b/arch/arm/boot/dts/qcom-apq8064-v2.0.dtsi @@ -0,0 +1 @@ +#include "qcom-apq8064.dtsi" diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi new file mode 100644 index 000000000000..92bf793622c3 --- /dev/null +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -0,0 +1,170 @@ +/dts-v1/; + +#include "skeleton.dtsi" +#include <dt-bindings/clock/qcom,gcc-msm8960.h> +#include <dt-bindings/soc/qcom,gsbi.h> + +/ { + model = "Qualcomm APQ8064"; + compatible = "qcom,apq8064"; + interrupt-parent = <&intc>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "qcom,krait"; + enable-method = "qcom,kpss-acc-v1"; + device_type = "cpu"; + reg = <0>; + next-level-cache = <&L2>; + qcom,acc = <&acc0>; + qcom,saw = <&saw0>; + }; + + cpu@1 { + compatible = "qcom,krait"; + enable-method = "qcom,kpss-acc-v1"; + device_type = "cpu"; + reg = <1>; + next-level-cache = <&L2>; + qcom,acc = <&acc1>; + qcom,saw = <&saw1>; + }; + + cpu@2 { + compatible = "qcom,krait"; + enable-method = "qcom,kpss-acc-v1"; + device_type = "cpu"; + reg = <2>; + next-level-cache = <&L2>; + qcom,acc = <&acc2>; + qcom,saw = <&saw2>; + }; + + cpu@3 { + compatible = "qcom,krait"; + enable-method = "qcom,kpss-acc-v1"; + device_type = "cpu"; + reg = <3>; + next-level-cache = <&L2>; + qcom,acc = <&acc3>; + qcom,saw = <&saw3>; + }; + + L2: l2-cache { + compatible = "cache"; + cache-level = <2>; + }; + }; + + cpu-pmu { + compatible = "qcom,krait-pmu"; + interrupts = <1 10 0x304>; + }; + + soc: soc { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "simple-bus"; + + intc: interrupt-controller@2000000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x02000000 0x1000>, + <0x02002000 0x1000>; + }; + + timer@200a000 { + compatible = "qcom,kpss-timer", "qcom,msm-timer"; + interrupts = <1 1 0x301>, + <1 2 0x301>, + <1 3 0x301>; + reg = <0x0200a000 0x100>; + clock-frequency = <27000000>, + <32768>; + cpu-offset = <0x80000>; + }; + + acc0: clock-controller@2088000 { + compatible = "qcom,kpss-acc-v1"; + reg = <0x02088000 0x1000>, <0x02008000 0x1000>; + }; + + acc1: clock-controller@2098000 { + compatible = "qcom,kpss-acc-v1"; + reg = <0x02098000 0x1000>, <0x02008000 0x1000>; + }; + + acc2: clock-controller@20a8000 { + compatible = "qcom,kpss-acc-v1"; + reg = <0x020a8000 0x1000>, <0x02008000 0x1000>; + }; + + acc3: clock-controller@20b8000 { + compatible = "qcom,kpss-acc-v1"; + reg = <0x020b8000 0x1000>, <0x02008000 0x1000>; + }; + + saw0: regulator@2089000 { + compatible = "qcom,saw2"; + reg = <0x02089000 0x1000>, <0x02009000 0x1000>; + regulator; + }; + + saw1: regulator@2099000 { + compatible = "qcom,saw2"; + reg = <0x02099000 0x1000>, <0x02009000 0x1000>; + regulator; + }; + + saw2: regulator@20a9000 { + compatible = "qcom,saw2"; + reg = <0x020a9000 0x1000>, <0x02009000 0x1000>; + regulator; + }; + + saw3: regulator@20b9000 { + compatible = "qcom,saw2"; + reg = <0x020b9000 0x1000>, <0x02009000 0x1000>; + regulator; + }; + + gsbi7: gsbi@16600000 { + status = "disabled"; + compatible = "qcom,gsbi-v1.0.0"; + reg = <0x16600000 0x100>; + clocks = <&gcc GSBI7_H_CLK>; + clock-names = "iface"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + serial@16640000 { + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; + reg = <0x16640000 0x1000>, + <0x16600000 0x1000>; + interrupts = <0 158 0x0>; + clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + }; + + qcom,ssbi@500000 { + compatible = "qcom,ssbi"; + reg = <0x00500000 0x1000>; + qcom,controller-type = "pmic-arbiter"; + }; + + gcc: clock-controller@900000 { + compatible = "qcom,gcc-apq8064"; + reg = <0x00900000 0x4000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts index 13ac3e222495..b4dfb01fe6fb 100644 --- a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts +++ b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts @@ -3,4 +3,43 @@ / { model = "Qualcomm APQ8074 Dragonboard"; compatible = "qcom,apq8074-dragonboard", "qcom,apq8074"; + + soc { + serial@f991e000 { + status = "ok"; + }; + + sdhci@f9824900 { + bus-width = <8>; + non-removable; + status = "ok"; + }; + + sdhci@f98a4900 { + cd-gpios = <&msmgpio 62 0x1>; + bus-width = <4>; + }; + + + pinctrl@fd510000 { + spi8_default: spi8_default { + mosi { + pins = "gpio45"; + function = "blsp_spi8"; + }; + miso { + pins = "gpio46"; + function = "blsp_spi8"; + }; + cs { + pins = "gpio47"; + function = "blsp_spi8"; + }; + clk { + pins = "gpio48"; + function = "blsp_spi8"; + }; + }; + }; + }; }; diff --git a/arch/arm/boot/dts/qcom-apq8084-mtp.dts b/arch/arm/boot/dts/qcom-apq8084-mtp.dts new file mode 100644 index 000000000000..9dae3878b71d --- /dev/null +++ b/arch/arm/boot/dts/qcom-apq8084-mtp.dts @@ -0,0 +1,6 @@ +#include "qcom-apq8084.dtsi" + +/ { + model = "Qualcomm APQ 8084-MTP"; + compatible = "qcom,apq8084-mtp", "qcom,apq8084"; +}; diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi new file mode 100644 index 000000000000..e3e009a5912b --- /dev/null +++ b/arch/arm/boot/dts/qcom-apq8084.dtsi @@ -0,0 +1,179 @@ +/dts-v1/; + +#include "skeleton.dtsi" + +/ { + model = "Qualcomm APQ 8084"; + compatible = "qcom,apq8084"; + interrupt-parent = <&intc>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "qcom,krait"; + reg = <0>; + enable-method = "qcom,kpss-acc-v2"; + next-level-cache = <&L2>; + qcom,acc = <&acc0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "qcom,krait"; + reg = <1>; + enable-method = "qcom,kpss-acc-v2"; + next-level-cache = <&L2>; + qcom,acc = <&acc1>; + }; + + cpu@2 { + device_type = "cpu"; + compatible = "qcom,krait"; + reg = <2>; + enable-method = "qcom,kpss-acc-v2"; + next-level-cache = <&L2>; + qcom,acc = <&acc2>; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "qcom,krait"; + reg = <3>; + enable-method = "qcom,kpss-acc-v2"; + next-level-cache = <&L2>; + qcom,acc = <&acc3>; + }; + + L2: l2-cache { + compatible = "qcom,arch-cache"; + cache-level = <2>; + qcom,saw = <&saw_l2>; + }; + }; + + cpu-pmu { + compatible = "qcom,krait-pmu"; + interrupts = <1 7 0xf04>; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <1 2 0xf08>, + <1 3 0xf08>, + <1 4 0xf08>, + <1 1 0xf08>; + clock-frequency = <19200000>; + }; + + soc: soc { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "simple-bus"; + + intc: interrupt-controller@f9000000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0xf9000000 0x1000>, + <0xf9002000 0x1000>; + }; + + timer@f9020000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0xf9020000 0x1000>; + clock-frequency = <19200000>; + + frame@f9021000 { + frame-number = <0>; + interrupts = <0 8 0x4>, + <0 7 0x4>; + reg = <0xf9021000 0x1000>, + <0xf9022000 0x1000>; + }; + + frame@f9023000 { + frame-number = <1>; + interrupts = <0 9 0x4>; + reg = <0xf9023000 0x1000>; + status = "disabled"; + }; + + frame@f9024000 { + frame-number = <2>; + interrupts = <0 10 0x4>; + reg = <0xf9024000 0x1000>; + status = "disabled"; + }; + + frame@f9025000 { + frame-number = <3>; + interrupts = <0 11 0x4>; + reg = <0xf9025000 0x1000>; + status = "disabled"; + }; + + frame@f9026000 { + frame-number = <4>; + interrupts = <0 12 0x4>; + reg = <0xf9026000 0x1000>; + status = "disabled"; + }; + + frame@f9027000 { + frame-number = <5>; + interrupts = <0 13 0x4>; + reg = <0xf9027000 0x1000>; + status = "disabled"; + }; + + frame@f9028000 { + frame-number = <6>; + interrupts = <0 14 0x4>; + reg = <0xf9028000 0x1000>; + status = "disabled"; + }; + }; + + saw_l2: regulator@f9012000 { + compatible = "qcom,saw2"; + reg = <0xf9012000 0x1000>; + regulator; + }; + + acc0: clock-controller@f9088000 { + compatible = "qcom,kpss-acc-v2"; + reg = <0xf9088000 0x1000>, + <0xf9008000 0x1000>; + }; + + acc1: clock-controller@f9098000 { + compatible = "qcom,kpss-acc-v2"; + reg = <0xf9098000 0x1000>, + <0xf9008000 0x1000>; + }; + + acc2: clock-controller@f90a8000 { + compatible = "qcom,kpss-acc-v2"; + reg = <0xf90a8000 0x1000>, + <0xf9008000 0x1000>; + }; + + acc3: clock-controller@f90b8000 { + compatible = "qcom,kpss-acc-v2"; + reg = <0xf90b8000 0x1000>, + <0xf9008000 0x1000>; + }; + + restart@fc4ab000 { + compatible = "qcom,pshold"; + reg = <0xfc4ab000 0x4>; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom-msm8660-surf.dts b/arch/arm/boot/dts/qcom-msm8660-surf.dts index 169bad90dac9..45180adfadf1 100644 --- a/arch/arm/boot/dts/qcom-msm8660-surf.dts +++ b/arch/arm/boot/dts/qcom-msm8660-surf.dts @@ -3,4 +3,14 @@ / { model = "Qualcomm MSM8660 SURF"; compatible = "qcom,msm8660-surf", "qcom,msm8660"; + + soc { + gsbi@19c00000 { + status = "ok"; + qcom,mode = <GSBI_PROT_I2C_UART>; + serial@19c40000 { + status = "ok"; + }; + }; + }; }; diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi index c52a9e964a44..53837aaa2f72 100644 --- a/arch/arm/boot/dts/qcom-msm8660.dtsi +++ b/arch/arm/boot/dts/qcom-msm8660.dtsi @@ -3,6 +3,7 @@ /include/ "skeleton.dtsi" #include <dt-bindings/clock/qcom,gcc-msm8660.h> +#include <dt-bindings/soc/qcom,gsbi.h> / { model = "Qualcomm MSM8660"; @@ -12,16 +13,18 @@ cpus { #address-cells = <1>; #size-cells = <0>; - compatible = "qcom,scorpion"; - enable-method = "qcom,gcc-msm8660"; cpu@0 { + compatible = "qcom,scorpion"; + enable-method = "qcom,gcc-msm8660"; device_type = "cpu"; reg = <0>; next-level-cache = <&L2>; }; cpu@1 { + compatible = "qcom,scorpion"; + enable-method = "qcom,gcc-msm8660"; device_type = "cpu"; reg = <1>; next-level-cache = <&L2>; @@ -33,55 +36,73 @@ }; }; - intc: interrupt-controller@2080000 { - compatible = "qcom,msm-8660-qgic"; - interrupt-controller; - #interrupt-cells = <3>; - reg = < 0x02080000 0x1000 >, - < 0x02081000 0x1000 >; - }; + soc: soc { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "simple-bus"; - timer@2000000 { - compatible = "qcom,scss-timer", "qcom,msm-timer"; - interrupts = <1 0 0x301>, - <1 1 0x301>, - <1 2 0x301>; - reg = <0x02000000 0x100>; - clock-frequency = <27000000>, - <32768>; - cpu-offset = <0x40000>; - }; + intc: interrupt-controller@2080000 { + compatible = "qcom,msm-8660-qgic"; + interrupt-controller; + #interrupt-cells = <3>; + reg = < 0x02080000 0x1000 >, + < 0x02081000 0x1000 >; + }; - msmgpio: gpio@800000 { - compatible = "qcom,msm-gpio"; - reg = <0x00800000 0x4000>; - gpio-controller; - #gpio-cells = <2>; - ngpio = <173>; - interrupts = <0 16 0x4>; - interrupt-controller; - #interrupt-cells = <2>; - }; + timer@2000000 { + compatible = "qcom,scss-timer", "qcom,msm-timer"; + interrupts = <1 0 0x301>, + <1 1 0x301>, + <1 2 0x301>; + reg = <0x02000000 0x100>; + clock-frequency = <27000000>, + <32768>; + cpu-offset = <0x40000>; + }; - gcc: clock-controller@900000 { - compatible = "qcom,gcc-msm8660"; - #clock-cells = <1>; - #reset-cells = <1>; - reg = <0x900000 0x4000>; - }; + msmgpio: gpio@800000 { + compatible = "qcom,msm-gpio"; + reg = <0x00800000 0x4000>; + gpio-controller; + #gpio-cells = <2>; + ngpio = <173>; + interrupts = <0 16 0x4>; + interrupt-controller; + #interrupt-cells = <2>; + }; - serial@19c40000 { - compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; - reg = <0x19c40000 0x1000>, - <0x19c00000 0x1000>; - interrupts = <0 195 0x0>; - clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>; - clock-names = "core", "iface"; - }; + gcc: clock-controller@900000 { + compatible = "qcom,gcc-msm8660"; + #clock-cells = <1>; + #reset-cells = <1>; + reg = <0x900000 0x4000>; + }; + + gsbi12: gsbi@19c00000 { + compatible = "qcom,gsbi-v1.0.0"; + reg = <0x19c00000 0x100>; + clocks = <&gcc GSBI12_H_CLK>; + clock-names = "iface"; + #address-cells = <1>; + #size-cells = <1>; + ranges; - qcom,ssbi@500000 { - compatible = "qcom,ssbi"; - reg = <0x500000 0x1000>; - qcom,controller-type = "pmic-arbiter"; + serial@19c40000 { + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; + reg = <0x19c40000 0x1000>, + <0x19c00000 0x1000>; + interrupts = <0 195 0x0>; + clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + }; + + qcom,ssbi@500000 { + compatible = "qcom,ssbi"; + reg = <0x500000 0x1000>; + qcom,controller-type = "pmic-arbiter"; + }; }; }; diff --git a/arch/arm/boot/dts/qcom-msm8960-cdp.dts b/arch/arm/boot/dts/qcom-msm8960-cdp.dts index a58fb88315f6..8f75cc4c8340 100644 --- a/arch/arm/boot/dts/qcom-msm8960-cdp.dts +++ b/arch/arm/boot/dts/qcom-msm8960-cdp.dts @@ -3,4 +3,14 @@ / { model = "Qualcomm MSM8960 CDP"; compatible = "qcom,msm8960-cdp", "qcom,msm8960"; + + soc { + gsbi@16400000 { + status = "ok"; + qcom,mode = <GSBI_PROT_I2C_UART>; + serial@16440000 { + status = "ok"; + }; + }; + }; }; diff --git a/arch/arm/boot/dts/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom-msm8960.dtsi index 997b7b94e117..5303e53e34dc 100644 --- a/arch/arm/boot/dts/qcom-msm8960.dtsi +++ b/arch/arm/boot/dts/qcom-msm8960.dtsi @@ -3,6 +3,7 @@ /include/ "skeleton.dtsi" #include <dt-bindings/clock/qcom,gcc-msm8960.h> +#include <dt-bindings/soc/qcom,gsbi.h> / { model = "Qualcomm MSM8960"; @@ -13,10 +14,10 @@ #address-cells = <1>; #size-cells = <0>; interrupts = <1 14 0x304>; - compatible = "qcom,krait"; - enable-method = "qcom,kpss-acc-v1"; cpu@0 { + compatible = "qcom,krait"; + enable-method = "qcom,kpss-acc-v1"; device_type = "cpu"; reg = <0>; next-level-cache = <&L2>; @@ -25,6 +26,8 @@ }; cpu@1 { + compatible = "qcom,krait"; + enable-method = "qcom,kpss-acc-v1"; device_type = "cpu"; reg = <1>; next-level-cache = <&L2>; @@ -35,7 +38,6 @@ L2: l2-cache { compatible = "cache"; cache-level = <2>; - interrupts = <0 2 0x4>; }; }; @@ -45,91 +47,109 @@ qcom,no-pc-write; }; - intc: interrupt-controller@2000000 { - compatible = "qcom,msm-qgic2"; - interrupt-controller; - #interrupt-cells = <3>; - reg = < 0x02000000 0x1000 >, - < 0x02002000 0x1000 >; - }; + soc: soc { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "simple-bus"; + + intc: interrupt-controller@2000000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x02000000 0x1000>, + <0x02002000 0x1000>; + }; - timer@200a000 { - compatible = "qcom,kpss-timer", "qcom,msm-timer"; - interrupts = <1 1 0x301>, - <1 2 0x301>, - <1 3 0x301>; - reg = <0x0200a000 0x100>; - clock-frequency = <27000000>, - <32768>; - cpu-offset = <0x80000>; - }; + timer@200a000 { + compatible = "qcom,kpss-timer", "qcom,msm-timer"; + interrupts = <1 1 0x301>, + <1 2 0x301>, + <1 3 0x301>; + reg = <0x0200a000 0x100>; + clock-frequency = <27000000>, + <32768>; + cpu-offset = <0x80000>; + }; - msmgpio: gpio@800000 { - compatible = "qcom,msm-gpio"; - gpio-controller; - #gpio-cells = <2>; - ngpio = <150>; - interrupts = <0 16 0x4>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x800000 0x4000>; - }; + msmgpio: gpio@800000 { + compatible = "qcom,msm-gpio"; + gpio-controller; + #gpio-cells = <2>; + ngpio = <150>; + interrupts = <0 16 0x4>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x800000 0x4000>; + }; - gcc: clock-controller@900000 { - compatible = "qcom,gcc-msm8960"; - #clock-cells = <1>; - #reset-cells = <1>; - reg = <0x900000 0x4000>; - }; + gcc: clock-controller@900000 { + compatible = "qcom,gcc-msm8960"; + #clock-cells = <1>; + #reset-cells = <1>; + reg = <0x900000 0x4000>; + }; - clock-controller@4000000 { - compatible = "qcom,mmcc-msm8960"; - reg = <0x4000000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; + clock-controller@4000000 { + compatible = "qcom,mmcc-msm8960"; + reg = <0x4000000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; - acc0: clock-controller@2088000 { - compatible = "qcom,kpss-acc-v1"; - reg = <0x02088000 0x1000>, <0x02008000 0x1000>; - }; + acc0: clock-controller@2088000 { + compatible = "qcom,kpss-acc-v1"; + reg = <0x02088000 0x1000>, <0x02008000 0x1000>; + }; - acc1: clock-controller@2098000 { - compatible = "qcom,kpss-acc-v1"; - reg = <0x02098000 0x1000>, <0x02008000 0x1000>; - }; + acc1: clock-controller@2098000 { + compatible = "qcom,kpss-acc-v1"; + reg = <0x02098000 0x1000>, <0x02008000 0x1000>; + }; - saw0: regulator@2089000 { - compatible = "qcom,saw2"; - reg = <0x02089000 0x1000>, <0x02009000 0x1000>; - regulator; - }; + saw0: regulator@2089000 { + compatible = "qcom,saw2"; + reg = <0x02089000 0x1000>, <0x02009000 0x1000>; + regulator; + }; - saw1: regulator@2099000 { - compatible = "qcom,saw2"; - reg = <0x02099000 0x1000>, <0x02009000 0x1000>; - regulator; - }; + saw1: regulator@2099000 { + compatible = "qcom,saw2"; + reg = <0x02099000 0x1000>, <0x02009000 0x1000>; + regulator; + }; - serial@16440000 { - compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; - reg = <0x16440000 0x1000>, - <0x16400000 0x1000>; - interrupts = <0 154 0x0>; - clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; - clock-names = "core", "iface"; - }; + gsbi5: gsbi@16400000 { + compatible = "qcom,gsbi-v1.0.0"; + reg = <0x16400000 0x100>; + clocks = <&gcc GSBI5_H_CLK>; + clock-names = "iface"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + serial@16440000 { + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; + reg = <0x16440000 0x1000>, + <0x16400000 0x1000>; + interrupts = <0 154 0x0>; + clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + }; - qcom,ssbi@500000 { - compatible = "qcom,ssbi"; - reg = <0x500000 0x1000>; - qcom,controller-type = "pmic-arbiter"; - }; + qcom,ssbi@500000 { + compatible = "qcom,ssbi"; + reg = <0x500000 0x1000>; + qcom,controller-type = "pmic-arbiter"; + }; - rng@1a500000 { - compatible = "qcom,prng"; - reg = <0x1a500000 0x200>; - clocks = <&gcc PRNG_CLK>; - clock-names = "core"; + rng@1a500000 { + compatible = "qcom,prng"; + reg = <0x1a500000 0x200>; + clocks = <&gcc PRNG_CLK>; + clock-names = "core"; + }; }; }; diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index f68723918b3f..69dca2aca25a 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -13,10 +13,10 @@ #address-cells = <1>; #size-cells = <0>; interrupts = <1 9 0xf04>; - compatible = "qcom,krait"; - enable-method = "qcom,kpss-acc-v2"; cpu@0 { + compatible = "qcom,krait"; + enable-method = "qcom,kpss-acc-v2"; device_type = "cpu"; reg = <0>; next-level-cache = <&L2>; @@ -24,6 +24,8 @@ }; cpu@1 { + compatible = "qcom,krait"; + enable-method = "qcom,kpss-acc-v2"; device_type = "cpu"; reg = <1>; next-level-cache = <&L2>; @@ -31,6 +33,8 @@ }; cpu@2 { + compatible = "qcom,krait"; + enable-method = "qcom,kpss-acc-v2"; device_type = "cpu"; reg = <2>; next-level-cache = <&L2>; @@ -38,6 +42,8 @@ }; cpu@3 { + compatible = "qcom,krait"; + enable-method = "qcom,kpss-acc-v2"; device_type = "cpu"; reg = <3>; next-level-cache = <&L2>; @@ -47,7 +53,6 @@ L2: l2-cache { compatible = "cache"; cache-level = <2>; - interrupts = <0 2 0x4>; qcom,saw = <&saw_l2>; }; }; @@ -57,6 +62,15 @@ interrupts = <1 7 0xf04>; }; + timer { + compatible = "arm,armv7-timer"; + interrupts = <1 2 0xf08>, + <1 3 0xf08>, + <1 4 0xf08>, + <1 1 0xf08>; + clock-frequency = <19200000>; + }; + soc: soc { #address-cells = <1>; #size-cells = <1>; @@ -71,15 +85,6 @@ <0xf9002000 0x1000>; }; - timer { - compatible = "arm,armv7-timer"; - interrupts = <1 2 0xf08>, - <1 3 0xf08>, - <1 4 0xf08>, - <1 1 0xf08>; - clock-frequency = <19200000>; - }; - timer@f9020000 { #address-cells = <1>; #size-cells = <1>; @@ -190,6 +195,29 @@ interrupts = <0 108 0x0>; clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; + status = "disabled"; + }; + + sdhci@f9824900 { + compatible = "qcom,sdhci-msm-v4"; + reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; + reg-names = "hc_mem", "core_mem"; + interrupts = <0 123 0>, <0 138 0>; + interrupt-names = "hc_irq", "pwr_irq"; + clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + + sdhci@f98a4900 { + compatible = "qcom,sdhci-msm-v4"; + reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; + reg-names = "hc_mem", "core_mem"; + interrupts = <0 125 0>, <0 221 0>; + interrupt-names = "hc_irq", "pwr_irq"; + clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>; + clock-names = "core", "iface"; + status = "disabled"; }; rng@f9bff000 { @@ -198,5 +226,15 @@ clocks = <&gcc GCC_PRNG_AHB_CLK>; clock-names = "core"; }; + + msmgpio: pinctrl@fd510000 { + compatible = "qcom,msm8974-pinctrl"; + reg = <0xfd510000 0x4000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 208 0>; + }; }; }; diff --git a/arch/arm/boot/dts/r7s72100-genmai-reference.dts b/arch/arm/boot/dts/r7s72100-genmai-reference.dts deleted file mode 100644 index e664611a47c8..000000000000 --- a/arch/arm/boot/dts/r7s72100-genmai-reference.dts +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Device Tree Source for the Genmai board - * - * Copyright (C) 2013 Renesas Solutions Corp. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -/dts-v1/; -#include "r7s72100.dtsi" - -/ { - model = "Genmai"; - compatible = "renesas,genmai-reference", "renesas,r7s72100"; - - chosen { - bootargs = "console=ttySC2,115200 ignore_loglevel rw root=/dev/nfs ip=dhcp"; - }; - - memory { - device_type = "memory"; - reg = <0x08000000 0x08000000>; - }; - - lbsc { - #address-cells = <1>; - #size-cells = <1>; - }; -}; - -&i2c2 { - status = "okay"; - clock-frequency = <400000>; - - eeprom@50 { - compatible = "renesas,24c128"; - reg = <0x50>; - pagesize = <64>; - }; -}; diff --git a/arch/arm/boot/dts/r7s72100-genmai.dts b/arch/arm/boot/dts/r7s72100-genmai.dts index b1deaf7e2e06..56849b55e1c2 100644 --- a/arch/arm/boot/dts/r7s72100-genmai.dts +++ b/arch/arm/boot/dts/r7s72100-genmai.dts @@ -1,7 +1,8 @@ /* * Device Tree Source for the Genmai board * - * Copyright (C) 2013 Renesas Solutions Corp. + * Copyright (C) 2013-14 Renesas Solutions Corp. + * Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com> * * This file is licensed under the terms of the GNU General Public License * version 2. This program is licensed "as is" without any warranty of any @@ -15,6 +16,10 @@ model = "Genmai"; compatible = "renesas,genmai", "renesas,r7s72100"; + aliases { + serial2 = &scif2; + }; + chosen { bootargs = "console=ttySC2,115200 ignore_loglevel rw root=/dev/nfs ip=dhcp"; }; @@ -29,3 +34,26 @@ #size-cells = <1>; }; }; + +&extal_clk { + clock-frequency = <13330000>; +}; + +&usb_x1_clk { + clock-frequency = <48000000>; +}; + +&i2c2 { + status = "okay"; + clock-frequency = <400000>; + + eeprom@50 { + compatible = "renesas,24c128"; + reg = <0x50>; + pagesize = <64>; + }; +}; + +&scif2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi index ee700717a34b..f50fbc8f3bd9 100644 --- a/arch/arm/boot/dts/r7s72100.dtsi +++ b/arch/arm/boot/dts/r7s72100.dtsi @@ -1,13 +1,15 @@ /* * Device Tree Source for the r7s72100 SoC * - * Copyright (C) 2013 Renesas Solutions Corp. + * Copyright (C) 2013-14 Renesas Solutions Corp. + * Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com> * * This file is licensed under the terms of the GNU General Public License * version 2. This program is licensed "as is" without any warranty of any * kind, whether express or implied. */ +#include <dt-bindings/clock/r7s72100-clock.h> #include <dt-bindings/interrupt-controller/irq.h> / { @@ -28,6 +30,112 @@ spi4 = &spi4; }; + clocks { + ranges; + #address-cells = <1>; + #size-cells = <1>; + + /* External clocks */ + extal_clk: extal_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + /* If clk present, value must be set by board */ + clock-frequency = <0>; + clock-output-names = "extal"; + }; + + usb_x1_clk: usb_x1_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + /* If clk present, value must be set by board */ + clock-frequency = <0>; + clock-output-names = "usb_x1"; + }; + + /* Special CPG clocks */ + cpg_clocks: cpg_clocks@fcfe0000 { + #clock-cells = <1>; + compatible = "renesas,r7s72100-cpg-clocks", + "renesas,rz-cpg-clocks"; + reg = <0xfcfe0000 0x18>; + clocks = <&extal_clk>, <&usb_x1_clk>; + clock-output-names = "pll", "i", "g"; + }; + + /* Fixed factor clocks */ + b_clk: b_clk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R7S72100_CLK_PLL>; + clock-mult = <1>; + clock-div = <3>; + clock-output-names = "b"; + }; + p1_clk: p1_clk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R7S72100_CLK_PLL>; + clock-mult = <1>; + clock-div = <6>; + clock-output-names = "p1"; + }; + p0_clk: p0_clk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R7S72100_CLK_PLL>; + clock-mult = <1>; + clock-div = <12>; + clock-output-names = "p0"; + }; + + /* MSTP clocks */ + mstp3_clks: mstp3_clks@fcfe0420 { + #clock-cells = <1>; + compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0xfcfe0420 4>; + clocks = <&p0_clk>; + clock-indices = <R7S72100_CLK_MTU2>; + clock-output-names = "mtu2"; + }; + + mstp4_clks: mstp4_clks@fcfe0424 { + #clock-cells = <1>; + compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0xfcfe0424 4>; + clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>, + <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>; + clock-indices = < + R7S72100_CLK_SCIF0 R7S72100_CLK_SCIF1 R7S72100_CLK_SCIF2 R7S72100_CLK_SCIF3 + R7S72100_CLK_SCIF4 R7S72100_CLK_SCIF5 R7S72100_CLK_SCIF6 R7S72100_CLK_SCIF7 + >; + clock-output-names = "scif0", "scif1", "scif2", "scif3", "scif4", "scif5", "scif6", "scif7"; + }; + + mstp9_clks: mstp9_clks@fcfe0438 { + #clock-cells = <1>; + compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0xfcfe0438 4>; + clocks = <&p0_clk>, <&p0_clk>, <&p0_clk>, <&p0_clk>; + clock-indices = < + R7S72100_CLK_I2C0 R7S72100_CLK_I2C1 R7S72100_CLK_I2C2 R7S72100_CLK_I2C3 + >; + clock-output-names = "i2c0", "i2c1", "i2c2", "i2c3"; + }; + + mstp10_clks: mstp10_clks@fcfe043c { + #clock-cells = <1>; + compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0xfcfe043c 4>; + clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>, + <&p1_clk>; + clock-indices = < + R7S72100_CLK_SPI0 R7S72100_CLK_SPI1 R7S72100_CLK_SPI2 R7S72100_CLK_SPI3 + R7S72100_CLK_SPI4 + >; + clock-output-names = "spi0", "spi1", "spi2", "spi3", "spi4"; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -61,6 +169,7 @@ <0 162 IRQ_TYPE_LEVEL_HIGH>, <0 163 IRQ_TYPE_LEVEL_HIGH>, <0 164 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R7S72100_CLK_I2C0>; clock-frequency = <100000>; status = "disabled"; }; @@ -78,6 +187,7 @@ <0 170 IRQ_TYPE_LEVEL_HIGH>, <0 171 IRQ_TYPE_LEVEL_HIGH>, <0 172 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R7S72100_CLK_I2C1>; clock-frequency = <100000>; status = "disabled"; }; @@ -95,6 +205,7 @@ <0 178 IRQ_TYPE_LEVEL_HIGH>, <0 179 IRQ_TYPE_LEVEL_HIGH>, <0 180 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R7S72100_CLK_I2C2>; clock-frequency = <100000>; status = "disabled"; }; @@ -112,10 +223,107 @@ <0 186 IRQ_TYPE_LEVEL_HIGH>, <0 187 IRQ_TYPE_LEVEL_HIGH>, <0 188 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R7S72100_CLK_I2C3>; clock-frequency = <100000>; status = "disabled"; }; + scif0: serial@e8007000 { + compatible = "renesas,scif-r7s72100", "renesas,scif"; + reg = <0xe8007000 64>; + interrupts = <0 190 IRQ_TYPE_LEVEL_HIGH>, + <0 191 IRQ_TYPE_LEVEL_HIGH>, + <0 192 IRQ_TYPE_LEVEL_HIGH>, + <0 189 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp4_clks R7S72100_CLK_SCIF0>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + scif1: serial@e8007800 { + compatible = "renesas,scif-r7s72100", "renesas,scif"; + reg = <0xe8007800 64>; + interrupts = <0 194 IRQ_TYPE_LEVEL_HIGH>, + <0 195 IRQ_TYPE_LEVEL_HIGH>, + <0 196 IRQ_TYPE_LEVEL_HIGH>, + <0 193 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp4_clks R7S72100_CLK_SCIF1>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + scif2: serial@e8008000 { + compatible = "renesas,scif-r7s72100", "renesas,scif"; + reg = <0xe8008000 64>; + interrupts = <0 198 IRQ_TYPE_LEVEL_HIGH>, + <0 199 IRQ_TYPE_LEVEL_HIGH>, + <0 200 IRQ_TYPE_LEVEL_HIGH>, + <0 197 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp4_clks R7S72100_CLK_SCIF2>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + scif3: serial@e8008800 { + compatible = "renesas,scif-r7s72100", "renesas,scif"; + reg = <0xe8008800 64>; + interrupts = <0 202 IRQ_TYPE_LEVEL_HIGH>, + <0 203 IRQ_TYPE_LEVEL_HIGH>, + <0 204 IRQ_TYPE_LEVEL_HIGH>, + <0 201 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp4_clks R7S72100_CLK_SCIF3>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + scif4: serial@e8009000 { + compatible = "renesas,scif-r7s72100", "renesas,scif"; + reg = <0xe8009000 64>; + interrupts = <0 206 IRQ_TYPE_LEVEL_HIGH>, + <0 207 IRQ_TYPE_LEVEL_HIGH>, + <0 208 IRQ_TYPE_LEVEL_HIGH>, + <0 205 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp4_clks R7S72100_CLK_SCIF4>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + scif5: serial@e8009800 { + compatible = "renesas,scif-r7s72100", "renesas,scif"; + reg = <0xe8009800 64>; + interrupts = <0 210 IRQ_TYPE_LEVEL_HIGH>, + <0 211 IRQ_TYPE_LEVEL_HIGH>, + <0 212 IRQ_TYPE_LEVEL_HIGH>, + <0 209 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp4_clks R7S72100_CLK_SCIF5>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + scif6: serial@e800a000 { + compatible = "renesas,scif-r7s72100", "renesas,scif"; + reg = <0xe800a000 64>; + interrupts = <0 214 IRQ_TYPE_LEVEL_HIGH>, + <0 215 IRQ_TYPE_LEVEL_HIGH>, + <0 216 IRQ_TYPE_LEVEL_HIGH>, + <0 213 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp4_clks R7S72100_CLK_SCIF6>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + scif7: serial@e800a800 { + compatible = "renesas,scif-r7s72100", "renesas,scif"; + reg = <0xe800a800 64>; + interrupts = <0 218 IRQ_TYPE_LEVEL_HIGH>, + <0 219 IRQ_TYPE_LEVEL_HIGH>, + <0 220 IRQ_TYPE_LEVEL_HIGH>, + <0 217 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp4_clks R7S72100_CLK_SCIF7>; + clock-names = "sci_ick"; + status = "disabled"; + }; + spi0: spi@e800c800 { compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; reg = <0xe800c800 0x24>; @@ -123,6 +331,7 @@ <0 239 IRQ_TYPE_LEVEL_HIGH>, <0 240 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "error", "rx", "tx"; + clocks = <&mstp10_clks R7S72100_CLK_SPI0>; num-cs = <1>; #address-cells = <1>; #size-cells = <0>; @@ -136,6 +345,7 @@ <0 242 IRQ_TYPE_LEVEL_HIGH>, <0 243 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "error", "rx", "tx"; + clocks = <&mstp10_clks R7S72100_CLK_SPI1>; num-cs = <1>; #address-cells = <1>; #size-cells = <0>; @@ -149,6 +359,7 @@ <0 245 IRQ_TYPE_LEVEL_HIGH>, <0 246 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "error", "rx", "tx"; + clocks = <&mstp10_clks R7S72100_CLK_SPI2>; num-cs = <1>; #address-cells = <1>; #size-cells = <0>; @@ -162,6 +373,7 @@ <0 248 IRQ_TYPE_LEVEL_HIGH>, <0 249 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "error", "rx", "tx"; + clocks = <&mstp10_clks R7S72100_CLK_SPI3>; num-cs = <1>; #address-cells = <1>; #size-cells = <0>; @@ -175,6 +387,7 @@ <0 251 IRQ_TYPE_LEVEL_HIGH>, <0 252 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "error", "rx", "tx"; + clocks = <&mstp10_clks R7S72100_CLK_SPI4>; num-cs = <1>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi index 62d0211bd192..82c5ac825386 100644 --- a/arch/arm/boot/dts/r8a73a4.dtsi +++ b/arch/arm/boot/dts/r8a73a4.dtsi @@ -55,7 +55,6 @@ #interrupt-cells = <2>; interrupt-controller; reg = <0 0xe61c0000 0 0x200>; - interrupt-parent = <&gic>; interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>, <0 1 IRQ_TYPE_LEVEL_HIGH>, <0 2 IRQ_TYPE_LEVEL_HIGH>, @@ -95,7 +94,6 @@ #interrupt-cells = <2>; interrupt-controller; reg = <0 0xe61c0200 0 0x200>; - interrupt-parent = <&gic>; interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>, <0 33 IRQ_TYPE_LEVEL_HIGH>, <0 34 IRQ_TYPE_LEVEL_HIGH>, @@ -136,7 +134,6 @@ dma0: dma-controller@e6700020 { compatible = "renesas,shdma-r8a73a4"; reg = <0 0xe6700020 0 0x89e0>; - interrupt-parent = <&gic>; interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH 0 200 IRQ_TYPE_LEVEL_HIGH 0 201 IRQ_TYPE_LEVEL_HIGH @@ -171,7 +168,6 @@ compatible = "renesas,rcar-thermal"; reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>, <0 0xe61f0200 0 0x38>, <0 0xe61f0300 0 0x38>; - interrupt-parent = <&gic>; interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>; }; @@ -180,7 +176,6 @@ #size-cells = <0>; compatible = "renesas,rmobile-iic"; reg = <0 0xe6500000 0 0x428>; - interrupt-parent = <&gic>; interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -190,7 +185,6 @@ #size-cells = <0>; compatible = "renesas,rmobile-iic"; reg = <0 0xe6510000 0 0x428>; - interrupt-parent = <&gic>; interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -200,7 +194,6 @@ #size-cells = <0>; compatible = "renesas,rmobile-iic"; reg = <0 0xe6520000 0 0x428>; - interrupt-parent = <&gic>; interrupts = <0 176 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -210,7 +203,6 @@ #size-cells = <0>; compatible = "renesas,rmobile-iic"; reg = <0 0xe6530000 0 0x428>; - interrupt-parent = <&gic>; interrupts = <0 177 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -220,7 +212,6 @@ #size-cells = <0>; compatible = "renesas,rmobile-iic"; reg = <0 0xe6540000 0 0x428>; - interrupt-parent = <&gic>; interrupts = <0 178 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -230,7 +221,6 @@ #size-cells = <0>; compatible = "renesas,rmobile-iic"; reg = <0 0xe60b0000 0 0x428>; - interrupt-parent = <&gic>; interrupts = <0 179 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -240,7 +230,6 @@ #size-cells = <0>; compatible = "renesas,rmobile-iic"; reg = <0 0xe6550000 0 0x428>; - interrupt-parent = <&gic>; interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -250,7 +239,6 @@ #size-cells = <0>; compatible = "renesas,rmobile-iic"; reg = <0 0xe6560000 0 0x428>; - interrupt-parent = <&gic>; interrupts = <0 185 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -260,7 +248,6 @@ #size-cells = <0>; compatible = "renesas,rmobile-iic"; reg = <0 0xe6570000 0 0x428>; - interrupt-parent = <&gic>; interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -268,7 +255,6 @@ mmcif0: mmc@ee200000 { compatible = "renesas,sh-mmcif"; reg = <0 0xee200000 0 0x80>; - interrupt-parent = <&gic>; interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>; reg-io-width = <4>; status = "disabled"; @@ -277,7 +263,6 @@ mmcif1: mmc@ee220000 { compatible = "renesas,sh-mmcif"; reg = <0 0xee220000 0 0x80>; - interrupt-parent = <&gic>; interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>; reg-io-width = <4>; status = "disabled"; @@ -309,7 +294,6 @@ sdhi0: sd@ee100000 { compatible = "renesas,sdhi-r8a73a4"; reg = <0 0xee100000 0 0x100>; - interrupt-parent = <&gic>; interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>; cap-sd-highspeed; status = "disabled"; @@ -318,7 +302,6 @@ sdhi1: sd@ee120000 { compatible = "renesas,sdhi-r8a73a4"; reg = <0 0xee120000 0 0x100>; - interrupt-parent = <&gic>; interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>; cap-sd-highspeed; status = "disabled"; @@ -327,7 +310,6 @@ sdhi2: sd@ee140000 { compatible = "renesas,sdhi-r8a73a4"; reg = <0 0xee140000 0 0x100>; - interrupt-parent = <&gic>; interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>; cap-sd-highspeed; status = "disabled"; diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts index 95a849bf921f..486007d7ffe4 100644 --- a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts +++ b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts @@ -11,6 +11,7 @@ /dts-v1/; #include "r8a7740.dtsi" #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/pwm/pwm.h> @@ -77,26 +78,26 @@ power-key { gpios = <&pfc 99 GPIO_ACTIVE_LOW>; - linux,code = <116>; + linux,code = <KEY_POWER>; label = "SW3"; gpio-key,wakeup; }; back-key { gpios = <&pfc 100 GPIO_ACTIVE_LOW>; - linux,code = <158>; + linux,code = <KEY_BACK>; label = "SW4"; }; menu-key { gpios = <&pfc 97 GPIO_ACTIVE_LOW>; - linux,code = <139>; + linux,code = <KEY_MENU>; label = "SW5"; }; home-key { gpios = <&pfc 98 GPIO_ACTIVE_LOW>; - linux,code = <102>; + linux,code = <KEY_HOME>; label = "SW6"; }; }; @@ -117,6 +118,16 @@ }; }; + i2c2: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "i2c-gpio"; + gpios = <&pfc 208 GPIO_ACTIVE_HIGH /* sda */ + &pfc 91 GPIO_ACTIVE_HIGH /* scl */ + >; + i2c-gpio,delay-us = <5>; + }; + backlight { compatible = "pwm-backlight"; pwms = <&tpu 2 33333 PWM_POLARITY_INVERTED>; @@ -147,6 +158,18 @@ }; }; +ðer { + pinctrl-0 = <ðer_pins>; + pinctrl-names = "default"; + + phy-handle = <&phy0>; + status = "ok"; + + phy0: ethernet-phy@0 { + reg = <0>; + }; +}; + &i2c0 { status = "okay"; touchscreen@55 { @@ -166,10 +189,23 @@ }; }; +&i2c2 { + status = "okay"; + rtc@30 { + compatible = "sii,s35390a"; + reg = <0x30>; + }; +}; + &pfc { pinctrl-0 = <&scifa1_pins>; pinctrl-names = "default"; + ether_pins: ether { + renesas,groups = "gether_mii", "gether_int"; + renesas,function = "gether"; + }; + scifa1_pins: serial1 { renesas,groups = "scifa1_data"; renesas,function = "scifa1"; diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi index 2551e9438d35..55d29f4d2ed6 100644 --- a/arch/arm/boot/dts/r8a7740.dtsi +++ b/arch/arm/boot/dts/r8a7740.dtsi @@ -14,6 +14,7 @@ / { compatible = "renesas,r8a7740"; + interrupt-parent = <&gic>; cpus { #address-cells = <1>; @@ -22,6 +23,7 @@ compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <0x0>; + clock-frequency = <800000000>; }; }; @@ -48,7 +50,6 @@ <0xe6900020 1>, <0xe6900040 1>, <0xe6900060 1>; - interrupt-parent = <&gic>; interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH 0 149 IRQ_TYPE_LEVEL_HIGH 0 149 IRQ_TYPE_LEVEL_HIGH @@ -69,7 +70,6 @@ <0xe6900024 1>, <0xe6900044 1>, <0xe6900064 1>; - interrupt-parent = <&gic>; interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH 0 149 IRQ_TYPE_LEVEL_HIGH 0 149 IRQ_TYPE_LEVEL_HIGH @@ -90,7 +90,6 @@ <0xe6900028 1>, <0xe6900048 1>, <0xe6900068 1>; - interrupt-parent = <&gic>; interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH 0 149 IRQ_TYPE_LEVEL_HIGH 0 149 IRQ_TYPE_LEVEL_HIGH @@ -111,7 +110,6 @@ <0xe690002c 1>, <0xe690004c 1>, <0xe690006c 1>; - interrupt-parent = <&gic>; interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH 0 149 IRQ_TYPE_LEVEL_HIGH 0 149 IRQ_TYPE_LEVEL_HIGH @@ -122,12 +120,23 @@ 0 149 IRQ_TYPE_LEVEL_HIGH>; }; + ether: ethernet@e9a00000 { + compatible = "renesas,gether-r8a7740"; + reg = <0xe9a00000 0x800>, + <0xe9a01800 0x800>; + interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>; + /* clocks = <&mstp3_clks R8A7740_CLK_GETHER>; */ + phy-mode = "mii"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + i2c0: i2c@fff20000 { #address-cells = <1>; #size-cells = <0>; - compatible = "renesas,rmobile-iic"; + compatible = "renesas,iic-r8a7740", "renesas,rmobile-iic"; reg = <0xfff20000 0x425>; - interrupt-parent = <&gic>; interrupts = <0 201 IRQ_TYPE_LEVEL_HIGH 0 202 IRQ_TYPE_LEVEL_HIGH 0 203 IRQ_TYPE_LEVEL_HIGH @@ -138,9 +147,8 @@ i2c1: i2c@e6c20000 { #address-cells = <1>; #size-cells = <0>; - compatible = "renesas,rmobile-iic"; + compatible = "renesas,iic-r8a7740", "renesas,rmobile-iic"; reg = <0xe6c20000 0x425>; - interrupt-parent = <&gic>; interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH 0 71 IRQ_TYPE_LEVEL_HIGH 0 72 IRQ_TYPE_LEVEL_HIGH @@ -173,9 +181,8 @@ }; mmcif0: mmc@e6bd0000 { - compatible = "renesas,sh-mmcif"; + compatible = "renesas,mmcif-r8a7740", "renesas,sh-mmcif"; reg = <0xe6bd0000 0x100>; - interrupt-parent = <&gic>; interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH 0 57 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; @@ -184,7 +191,6 @@ sdhi0: sd@e6850000 { compatible = "renesas,sdhi-r8a7740"; reg = <0xe6850000 0x100>; - interrupt-parent = <&gic>; interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH 0 118 IRQ_TYPE_LEVEL_HIGH 0 119 IRQ_TYPE_LEVEL_HIGH>; @@ -196,7 +202,6 @@ sdhi1: sd@e6860000 { compatible = "renesas,sdhi-r8a7740"; reg = <0xe6860000 0x100>; - interrupt-parent = <&gic>; interrupts = <0 121 IRQ_TYPE_LEVEL_HIGH 0 122 IRQ_TYPE_LEVEL_HIGH 0 123 IRQ_TYPE_LEVEL_HIGH>; @@ -208,7 +213,6 @@ sdhi2: sd@e6870000 { compatible = "renesas,sdhi-r8a7740"; reg = <0xe6870000 0x100>; - interrupt-parent = <&gic>; interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH 0 126 IRQ_TYPE_LEVEL_HIGH 0 127 IRQ_TYPE_LEVEL_HIGH>; @@ -219,9 +223,8 @@ sh_fsi2: sound@fe1f0000 { #sound-dai-cells = <1>; - compatible = "renesas,sh_fsi2"; + compatible = "renesas,fsi2-r8a7740", "renesas,sh_fsi2"; reg = <0xfe1f0000 0x400>; - interrupt-parent = <&gic>; interrupts = <0 9 0x4>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/r8a7778-bockw-reference.dts b/arch/arm/boot/dts/r8a7778-bockw-reference.dts index 06cda19dac6a..f76f6ec01e19 100644 --- a/arch/arm/boot/dts/r8a7778-bockw-reference.dts +++ b/arch/arm/boot/dts/r8a7778-bockw-reference.dts @@ -109,4 +109,18 @@ pinctrl-0 = <&hspi0_pins>; pinctrl-names = "default"; status = "okay"; + + flash: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spansion,s25fl008k"; + reg = <0>; + spi-max-frequency = <104000000>; + m25p,fast-read; + + partition@0 { + label = "data(spi)"; + reg = <0x00000000 0x00100000>; + }; + }; }; diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi index 85c5b3b99f5e..3af0a2187493 100644 --- a/arch/arm/boot/dts/r8a7778.dtsi +++ b/arch/arm/boot/dts/r8a7778.dtsi @@ -20,6 +20,7 @@ / { compatible = "renesas,r8a7778"; + interrupt-parent = <&gic>; cpus { cpu@0 { @@ -52,7 +53,6 @@ <0xfe780024 4>, <0xfe780044 4>, <0xfe780064 4>; - interrupt-parent = <&gic>; interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH 0 28 IRQ_TYPE_LEVEL_HIGH 0 29 IRQ_TYPE_LEVEL_HIGH @@ -63,7 +63,6 @@ gpio0: gpio@ffc40000 { compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar"; reg = <0xffc40000 0x2c>; - interrupt-parent = <&gic>; interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; @@ -75,7 +74,6 @@ gpio1: gpio@ffc41000 { compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar"; reg = <0xffc41000 0x2c>; - interrupt-parent = <&gic>; interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; @@ -87,7 +85,6 @@ gpio2: gpio@ffc42000 { compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar"; reg = <0xffc42000 0x2c>; - interrupt-parent = <&gic>; interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; @@ -99,7 +96,6 @@ gpio3: gpio@ffc43000 { compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar"; reg = <0xffc43000 0x2c>; - interrupt-parent = <&gic>; interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; @@ -111,7 +107,6 @@ gpio4: gpio@ffc44000 { compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar"; reg = <0xffc44000 0x2c>; - interrupt-parent = <&gic>; interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; @@ -130,7 +125,6 @@ #size-cells = <0>; compatible = "renesas,i2c-r8a7778"; reg = <0xffc70000 0x1000>; - interrupt-parent = <&gic>; interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -140,7 +134,6 @@ #size-cells = <0>; compatible = "renesas,i2c-r8a7778"; reg = <0xffc71000 0x1000>; - interrupt-parent = <&gic>; interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -150,7 +143,6 @@ #size-cells = <0>; compatible = "renesas,i2c-r8a7778"; reg = <0xffc72000 0x1000>; - interrupt-parent = <&gic>; interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -160,7 +152,6 @@ #size-cells = <0>; compatible = "renesas,i2c-r8a7778"; reg = <0xffc73000 0x1000>; - interrupt-parent = <&gic>; interrupts = <0 77 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -168,7 +159,6 @@ mmcif: mmc@ffe4e000 { compatible = "renesas,sh-mmcif"; reg = <0xffe4e000 0x100>; - interrupt-parent = <&gic>; interrupts = <0 61 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -176,7 +166,6 @@ sdhi0: sd@ffe4c000 { compatible = "renesas,sdhi-r8a7778"; reg = <0xffe4c000 0x100>; - interrupt-parent = <&gic>; interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>; cap-sd-highspeed; cap-sdio-irq; @@ -186,7 +175,6 @@ sdhi1: sd@ffe4d000 { compatible = "renesas,sdhi-r8a7778"; reg = <0xffe4d000 0x100>; - interrupt-parent = <&gic>; interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>; cap-sd-highspeed; cap-sdio-irq; @@ -196,7 +184,6 @@ sdhi2: sd@ffe4f000 { compatible = "renesas,sdhi-r8a7778"; reg = <0xffe4f000 0x100>; - interrupt-parent = <&gic>; interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; cap-sd-highspeed; cap-sdio-irq; @@ -204,26 +191,29 @@ }; hspi0: spi@fffc7000 { - compatible = "renesas,hspi"; + compatible = "renesas,hspi-r8a7778", "renesas,hspi"; reg = <0xfffc7000 0x18>; - interrupt-controller = <&gic>; interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; }; hspi1: spi@fffc8000 { - compatible = "renesas,hspi"; + compatible = "renesas,hspi-r8a7778", "renesas,hspi"; reg = <0xfffc8000 0x18>; - interrupt-controller = <&gic>; interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; }; hspi2: spi@fffc6000 { - compatible = "renesas,hspi"; + compatible = "renesas,hspi-r8a7778", "renesas,hspi"; reg = <0xfffc6000 0x18>; - interrupt-controller = <&gic>; interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/r8a7779-marzen-reference.dts b/arch/arm/boot/dts/r8a7779-marzen-reference.dts index 76f5eef7d1cc..b27c6373ff4d 100644 --- a/arch/arm/boot/dts/r8a7779-marzen-reference.dts +++ b/arch/arm/boot/dts/r8a7779-marzen-reference.dts @@ -45,6 +45,7 @@ phy-mode = "mii"; interrupt-parent = <&irqpin0>; interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + smsc,irq-push-pull; reg-io-width = <4>; vddvario-supply = <&fixedregulator3v3>; vdd33a-supply = <&fixedregulator3v3>; diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi index d0561d4c7c46..b517c8e6b420 100644 --- a/arch/arm/boot/dts/r8a7779.dtsi +++ b/arch/arm/boot/dts/r8a7779.dtsi @@ -15,6 +15,7 @@ / { compatible = "renesas,r8a7779"; + interrupt-parent = <&gic>; cpus { #address-cells = <1>; @@ -59,7 +60,6 @@ gpio0: gpio@ffc40000 { compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; reg = <0xffc40000 0x2c>; - interrupt-parent = <&gic>; interrupts = <0 141 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; @@ -71,7 +71,6 @@ gpio1: gpio@ffc41000 { compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; reg = <0xffc41000 0x2c>; - interrupt-parent = <&gic>; interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; @@ -83,7 +82,6 @@ gpio2: gpio@ffc42000 { compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; reg = <0xffc42000 0x2c>; - interrupt-parent = <&gic>; interrupts = <0 143 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; @@ -95,7 +93,6 @@ gpio3: gpio@ffc43000 { compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; reg = <0xffc43000 0x2c>; - interrupt-parent = <&gic>; interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; @@ -107,7 +104,6 @@ gpio4: gpio@ffc44000 { compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; reg = <0xffc44000 0x2c>; - interrupt-parent = <&gic>; interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; @@ -119,7 +115,6 @@ gpio5: gpio@ffc45000 { compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; reg = <0xffc45000 0x2c>; - interrupt-parent = <&gic>; interrupts = <0 146 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; @@ -131,7 +126,6 @@ gpio6: gpio@ffc46000 { compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; reg = <0xffc46000 0x2c>; - interrupt-parent = <&gic>; interrupts = <0 147 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; @@ -150,7 +144,6 @@ <0xfe780024 4>, <0xfe780044 4>, <0xfe780064 4>; - interrupt-parent = <&gic>; interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH 0 28 IRQ_TYPE_LEVEL_HIGH 0 29 IRQ_TYPE_LEVEL_HIGH @@ -163,7 +156,6 @@ #size-cells = <0>; compatible = "renesas,i2c-r8a7779"; reg = <0xffc70000 0x1000>; - interrupt-parent = <&gic>; interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -173,7 +165,6 @@ #size-cells = <0>; compatible = "renesas,i2c-r8a7779"; reg = <0xffc71000 0x1000>; - interrupt-parent = <&gic>; interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -183,7 +174,6 @@ #size-cells = <0>; compatible = "renesas,i2c-r8a7779"; reg = <0xffc72000 0x1000>; - interrupt-parent = <&gic>; interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -193,7 +183,6 @@ #size-cells = <0>; compatible = "renesas,i2c-r8a7779"; reg = <0xffc73000 0x1000>; - interrupt-parent = <&gic>; interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -211,14 +200,12 @@ sata: sata@fc600000 { compatible = "renesas,rcar-sata"; reg = <0xfc600000 0x2000>; - interrupt-parent = <&gic>; interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>; }; sdhi0: sd@ffe4c000 { compatible = "renesas,sdhi-r8a7779"; reg = <0xffe4c000 0x100>; - interrupt-parent = <&gic>; interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>; cap-sd-highspeed; cap-sdio-irq; @@ -228,7 +215,6 @@ sdhi1: sd@ffe4d000 { compatible = "renesas,sdhi-r8a7779"; reg = <0xffe4d000 0x100>; - interrupt-parent = <&gic>; interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; cap-sd-highspeed; cap-sdio-irq; @@ -238,7 +224,6 @@ sdhi2: sd@ffe4e000 { compatible = "renesas,sdhi-r8a7779"; reg = <0xffe4e000 0x100>; - interrupt-parent = <&gic>; interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>; cap-sd-highspeed; cap-sdio-irq; @@ -248,7 +233,6 @@ sdhi3: sd@ffe4f000 { compatible = "renesas,sdhi-r8a7779"; reg = <0xffe4f000 0x100>; - interrupt-parent = <&gic>; interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; cap-sd-highspeed; cap-sdio-irq; @@ -256,26 +240,29 @@ }; hspi0: spi@fffc7000 { - compatible = "renesas,hspi"; + compatible = "renesas,hspi-r8a7779", "renesas,hspi"; reg = <0xfffc7000 0x18>; - interrupt-controller = <&gic>; interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; }; hspi1: spi@fffc8000 { - compatible = "renesas,hspi"; + compatible = "renesas,hspi-r8a7779", "renesas,hspi"; reg = <0xfffc8000 0x18>; - interrupt-controller = <&gic>; interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; }; hspi2: spi@fffc6000 { - compatible = "renesas,hspi"; + compatible = "renesas,hspi-r8a7779", "renesas,hspi"; reg = <0xfffc6000 0x18>; - interrupt-controller = <&gic>; interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts index d01048ab3e77..dd2fe46073f2 100644 --- a/arch/arm/boot/dts/r8a7790-lager.dts +++ b/arch/arm/boot/dts/r8a7790-lager.dts @@ -12,11 +12,17 @@ /dts-v1/; #include "r8a7790.dtsi" #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> / { model = "Lager"; compatible = "renesas,lager", "renesas,r8a7790"; + aliases { + serial6 = &scif0; + serial7 = &scif1; + }; + chosen { bootargs = "console=ttySC6,115200 ignore_loglevel rw root=/dev/nfs ip=dhcp"; }; @@ -36,6 +42,39 @@ #size-cells = <1>; }; + gpio_keys { + compatible = "gpio-keys"; + + button@1 { + linux,code = <KEY_1>; + label = "SW2-1"; + gpio-key,wakeup; + debounce-interval = <20>; + gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; + }; + button@2 { + linux,code = <KEY_2>; + label = "SW2-2"; + gpio-key,wakeup; + debounce-interval = <20>; + gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; + }; + button@3 { + linux,code = <KEY_3>; + label = "SW2-3"; + gpio-key,wakeup; + debounce-interval = <20>; + gpios = <&gpio1 26 GPIO_ACTIVE_LOW>; + }; + button@4 { + linux,code = <KEY_4>; + label = "SW2-4"; + gpio-key,wakeup; + debounce-interval = <20>; + gpios = <&gpio1 28 GPIO_ACTIVE_LOW>; + }; + }; + leds { compatible = "gpio-leds"; led6 { @@ -112,7 +151,7 @@ }; &pfc { - pinctrl-0 = <&du_pins &scif0_pins &scif1_pins>; + pinctrl-0 = <&du_pins>; pinctrl-names = "default"; du_pins: du { @@ -155,10 +194,16 @@ renesas,function = "mmc1"; }; - qspi_pins: spi { + qspi_pins: spi0 { renesas,groups = "qspi_ctrl", "qspi_data4"; renesas,function = "qspi"; }; + + msiof1_pins: spi2 { + renesas,groups = "msiof1_clk", "msiof1_sync", "msiof1_rx", + "msiof1_tx"; + renesas,function = "msiof1"; + }; }; ðer { @@ -173,6 +218,7 @@ reg = <1>; interrupt-parent = <&irqc0>; interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + micrel,led-mode = <1>; }; }; @@ -190,7 +236,7 @@ status = "okay"; }; -&spi { +&qspi { pinctrl-0 = <&qspi_pins>; pinctrl-names = "default"; @@ -202,6 +248,8 @@ compatible = "spansion,s25fl512s"; reg = <0>; spi-max-frequency = <30000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; m25p,fast-read; partition@0 { @@ -221,6 +269,35 @@ }; }; +&scif0 { + pinctrl-0 = <&scif0_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&scif1 { + pinctrl-0 = <&scif1_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&msiof1 { + pinctrl-0 = <&msiof1_pins>; + pinctrl-names = "default"; + + status = "okay"; + + pmic: pmic@0 { + compatible = "renesas,r2a11302ft"; + reg = <0>; + spi-max-frequency = <6000000>; + spi-cpol; + spi-cpha; + }; +}; + &sdhi0 { pinctrl-0 = <&sdhi0_pins>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 618e5b537eaf..7ff29601f962 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -24,6 +24,15 @@ i2c1 = &i2c1; i2c2 = &i2c2; i2c3 = &i2c3; + i2c4 = &iic0; + i2c5 = &iic1; + i2c6 = &iic2; + i2c7 = &iic3; + spi0 = &qspi; + spi1 = &msiof0; + spi2 = &msiof1; + spi3 = &msiof2; + spi4 = &msiof3; }; cpus { @@ -108,6 +117,7 @@ gpio-ranges = <&pfc 0 0 32>; #interrupt-cells = <2>; interrupt-controller; + clocks = <&mstp9_clks R8A7790_CLK_GPIO0>; }; gpio1: gpio@e6051000 { @@ -119,6 +129,7 @@ gpio-ranges = <&pfc 0 32 32>; #interrupt-cells = <2>; interrupt-controller; + clocks = <&mstp9_clks R8A7790_CLK_GPIO1>; }; gpio2: gpio@e6052000 { @@ -130,6 +141,7 @@ gpio-ranges = <&pfc 0 64 32>; #interrupt-cells = <2>; interrupt-controller; + clocks = <&mstp9_clks R8A7790_CLK_GPIO2>; }; gpio3: gpio@e6053000 { @@ -141,6 +153,7 @@ gpio-ranges = <&pfc 0 96 32>; #interrupt-cells = <2>; interrupt-controller; + clocks = <&mstp9_clks R8A7790_CLK_GPIO3>; }; gpio4: gpio@e6054000 { @@ -152,6 +165,7 @@ gpio-ranges = <&pfc 0 128 32>; #interrupt-cells = <2>; interrupt-controller; + clocks = <&mstp9_clks R8A7790_CLK_GPIO4>; }; gpio5: gpio@e6055000 { @@ -163,6 +177,7 @@ gpio-ranges = <&pfc 0 160 32>; #interrupt-cells = <2>; interrupt-controller; + clocks = <&mstp9_clks R8A7790_CLK_GPIO5>; }; thermal@e61f0000 { @@ -231,6 +246,46 @@ status = "disabled"; }; + iic0: i2c@e6500000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic"; + reg = <0 0xe6500000 0 0x425>; + interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7790_CLK_IIC0>; + status = "disabled"; + }; + + iic1: i2c@e6510000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic"; + reg = <0 0xe6510000 0 0x425>; + interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7790_CLK_IIC1>; + status = "disabled"; + }; + + iic2: i2c@e6520000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic"; + reg = <0 0xe6520000 0 0x425>; + interrupts = <0 176 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7790_CLK_IIC2>; + status = "disabled"; + }; + + iic3: i2c@e60b0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic"; + reg = <0 0xe60b0000 0 0x425>; + interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R8A7790_CLK_IICDVFS>; + status = "disabled"; + }; + mmcif0: mmcif@ee200000 { compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif"; reg = <0 0xee200000 0 0x80>; @@ -673,7 +728,7 @@ renesas,clock-indices = < R8A7790_CLK_TMU1 R8A7790_CLK_TMU3 R8A7790_CLK_TMU2 R8A7790_CLK_CMT0 R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1 - R8A7790_CLK_VSP1_DU0 R8A7790_CLK_VSP1_RT R8A7790_CLK_VSP1_SY + R8A7790_CLK_VSP1_DU0 R8A7790_CLK_VSP1_R R8A7790_CLK_VSP1_S >; clock-output-names = "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1", @@ -697,18 +752,19 @@ mstp3_clks: mstp3_clks@e615013c { compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; - clocks = <&cp_clk>, <&mmc1_clk>, <&sd3_clk>, <&sd2_clk>, - <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, - <&mmc0_clk>, <&rclk_clk>; + clocks = <&hp_clk>, <&cp_clk>, <&mmc1_clk>, <&sd3_clk>, + <&sd2_clk>, <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, <&mmc0_clk>, + <&hp_clk>, <&hp_clk>, <&rclk_clk>; #clock-cells = <1>; renesas,clock-indices = < - R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3 - R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 - R8A7790_CLK_MMCIF0 R8A7790_CLK_CMT1 + R8A7790_CLK_IIC2 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3 + R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 R8A7790_CLK_MMCIF0 + R8A7790_CLK_IIC0 R8A7790_CLK_IIC1 R8A7790_CLK_CMT1 >; clock-output-names = - "tpu0", "mmcif1", "sdhi3", "sdhi2", - "sdhi1", "sdhi0", "mmcif0", "cmt1"; + "iic2", "tpu0", "mmcif1", "sdhi3", + "sdhi2", "sdhi1", "sdhi0", "mmcif0", + "iic0", "iic1", "cmt1"; }; mstp5_clks: mstp5_clks@e6150144 { compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; @@ -752,20 +808,25 @@ mstp9_clks: mstp9_clks@e6150994 { compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>; - clocks = <&p_clk>, <&p_clk>, <&cpg_clocks R8A7790_CLK_QSPI>, - <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>; + clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, + <&cp_clk>, <&cp_clk>, <&cp_clk>, + <&p_clk>, <&p_clk>, <&cpg_clocks R8A7790_CLK_QSPI>, <&cp_clk>, + <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>; #clock-cells = <1>; renesas,clock-indices = < - R8A7790_CLK_RCAN1 R8A7790_CLK_RCAN0 R8A7790_CLK_QSPI_MOD - R8A7790_CLK_I2C3 R8A7790_CLK_I2C2 R8A7790_CLK_I2C1 - R8A7790_CLK_I2C0 + R8A7790_CLK_GPIO5 R8A7790_CLK_GPIO4 R8A7790_CLK_GPIO3 + R8A7790_CLK_GPIO2 R8A7790_CLK_GPIO1 R8A7790_CLK_GPIO0 + R8A7790_CLK_RCAN1 R8A7790_CLK_RCAN0 R8A7790_CLK_QSPI_MOD R8A7790_CLK_IICDVFS + R8A7790_CLK_I2C3 R8A7790_CLK_I2C2 R8A7790_CLK_I2C1 R8A7790_CLK_I2C0 >; clock-output-names = - "rcan1", "rcan0", "qspi_mod", "i2c3", "i2c2", "i2c1", "i2c0"; + "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0", + "rcan1", "rcan0", "qspi_mod", "iic3", + "i2c3", "i2c2", "i2c1", "i2c0"; }; }; - spi: spi@e6b10000 { + qspi: spi@e6b10000 { compatible = "renesas,qspi-r8a7790", "renesas,qspi"; reg = <0 0xe6b10000 0 0x2c>; interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>; @@ -775,4 +836,44 @@ #size-cells = <0>; status = "disabled"; }; + + msiof0: spi@e6e20000 { + compatible = "renesas,msiof-r8a7790"; + reg = <0 0xe6e20000 0 0x0064>; + interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp0_clks R8A7790_CLK_MSIOF0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof1: spi@e6e10000 { + compatible = "renesas,msiof-r8a7790"; + reg = <0 0xe6e10000 0 0x0064>; + interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A7790_CLK_MSIOF1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof2: spi@e6e00000 { + compatible = "renesas,msiof-r8a7790"; + reg = <0 0xe6e00000 0 0x0064>; + interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A7790_CLK_MSIOF2>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof3: spi@e6c90000 { + compatible = "renesas,msiof-r8a7790"; + reg = <0 0xe6c90000 0 0x0064>; + interrupts = <0 159 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A7790_CLK_MSIOF3>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; diff --git a/arch/arm/boot/dts/r8a7791-henninger.dts b/arch/arm/boot/dts/r8a7791-henninger.dts new file mode 100644 index 000000000000..cc6d992e8db2 --- /dev/null +++ b/arch/arm/boot/dts/r8a7791-henninger.dts @@ -0,0 +1,219 @@ +/* + * Device Tree Source for the Henninger board + * + * Copyright (C) 2014 Renesas Solutions Corp. + * Copyright (C) 2014 Cogent Embedded, Inc. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/dts-v1/; +#include "r8a7791.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "Henninger"; + compatible = "renesas,henninger", "renesas,r8a7791"; + + aliases { + serial0 = &scif0; + }; + + chosen { + bootargs = "console=ttySC0,38400 ignore_loglevel rw root=/dev/nfs ip=dhcp"; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x40000000>; + }; + + memory@200000000 { + device_type = "memory"; + reg = <2 0x00000000 0 0x40000000>; + }; + + vcc_sdhi0: regulator@0 { + compatible = "regulator-fixed"; + + regulator-name = "SDHI0 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vccq_sdhi0: regulator@1 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI0 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 1 + 1800000 0>; + }; + + vcc_sdhi2: regulator@2 { + compatible = "regulator-fixed"; + + regulator-name = "SDHI2 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vccq_sdhi2: regulator@3 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI2 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 1 + 1800000 0>; + }; +}; + +&extal_clk { + clock-frequency = <20000000>; +}; + +&pfc { + scif0_pins: serial0 { + renesas,groups = "scif0_data_d"; + renesas,function = "scif0"; + }; + + ether_pins: ether { + renesas,groups = "eth_link", "eth_mdio", "eth_rmii"; + renesas,function = "eth"; + }; + + phy1_pins: phy1 { + renesas,groups = "intc_irq0"; + renesas,function = "intc"; + }; + + sdhi0_pins: sd0 { + renesas,groups = "sdhi0_data4", "sdhi0_ctrl"; + renesas,function = "sdhi0"; + }; + + sdhi2_pins: sd2 { + renesas,groups = "sdhi2_data4", "sdhi2_ctrl"; + renesas,function = "sdhi2"; + }; + + qspi_pins: spi0 { + renesas,groups = "qspi_ctrl", "qspi_data4"; + renesas,function = "qspi"; + }; + + msiof0_pins: spi1 { + renesas,groups = "msiof0_clk", "msiof0_sync", "msiof0_rx", + "msiof0_tx"; + renesas,function = "msiof0"; + }; +}; + +&scif0 { + pinctrl-0 = <&scif0_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +ðer { + pinctrl-0 = <ðer_pins &phy1_pins>; + pinctrl-names = "default"; + + phy-handle = <&phy1>; + renesas,ether-link-active-low; + status = "ok"; + + phy1: ethernet-phy@1 { + reg = <1>; + interrupt-parent = <&irqc0>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + micrel,led-mode = <1>; + }; +}; + +&sata0 { + status = "okay"; +}; + +&sdhi0 { + pinctrl-0 = <&sdhi0_pins>; + pinctrl-names = "default"; + + vmmc-supply = <&vcc_sdhi0>; + vqmmc-supply = <&vccq_sdhi0>; + cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&sdhi2 { + pinctrl-0 = <&sdhi2_pins>; + pinctrl-names = "default"; + + vmmc-supply = <&vcc_sdhi2>; + vqmmc-supply = <&vccq_sdhi2>; + cd-gpios = <&gpio6 22 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&qspi { + pinctrl-0 = <&qspi_pins>; + pinctrl-names = "default"; + + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spansion,s25fl512s"; + reg = <0>; + spi-max-frequency = <30000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + m25p,fast-read; + + partition@0 { + label = "loader_prg"; + reg = <0x00000000 0x00040000>; + read-only; + }; + partition@40000 { + label = "user_prg"; + reg = <0x00040000 0x00400000>; + read-only; + }; + partition@440000 { + label = "flash_fs"; + reg = <0x00440000 0x03bc0000>; + }; + }; +}; + +&msiof0 { + pinctrl-0 = <&msiof0_pins>; + pinctrl-names = "default"; + + status = "okay"; + + pmic@0 { + compatible = "renesas,r2a11302ft"; + reg = <0>; + spi-max-frequency = <6000000>; + spi-cpol; + spi-cpha; + }; +}; diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts index de1b6977c69a..05d44f9b202f 100644 --- a/arch/arm/boot/dts/r8a7791-koelsch.dts +++ b/arch/arm/boot/dts/r8a7791-koelsch.dts @@ -13,11 +13,17 @@ /dts-v1/; #include "r8a7791.dtsi" #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> / { model = "Koelsch"; compatible = "renesas,koelsch", "renesas,r8a7791"; + aliases { + serial6 = &scif0; + serial7 = &scif1; + }; + chosen { bootargs = "console=ttySC6,115200 ignore_loglevel rw root=/dev/nfs ip=dhcp"; }; @@ -40,51 +46,79 @@ gpio-keys { compatible = "gpio-keys"; + key-1 { + gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + linux,code = <KEY_1>; + label = "SW2-1"; + gpio-key,wakeup; + debounce-interval = <20>; + }; + key-2 { + gpios = <&gpio5 1 GPIO_ACTIVE_LOW>; + linux,code = <KEY_2>; + label = "SW2-2"; + gpio-key,wakeup; + debounce-interval = <20>; + }; + key-3 { + gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; + linux,code = <KEY_3>; + label = "SW2-3"; + gpio-key,wakeup; + debounce-interval = <20>; + }; + key-4 { + gpios = <&gpio5 3 GPIO_ACTIVE_LOW>; + linux,code = <KEY_4>; + label = "SW2-4"; + gpio-key,wakeup; + debounce-interval = <20>; + }; key-a { gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; - linux,code = <30>; + linux,code = <KEY_A>; label = "SW30"; gpio-key,wakeup; debounce-interval = <20>; }; key-b { gpios = <&gpio7 1 GPIO_ACTIVE_LOW>; - linux,code = <48>; + linux,code = <KEY_B>; label = "SW31"; gpio-key,wakeup; debounce-interval = <20>; }; key-c { gpios = <&gpio7 2 GPIO_ACTIVE_LOW>; - linux,code = <46>; + linux,code = <KEY_C>; label = "SW32"; gpio-key,wakeup; debounce-interval = <20>; }; key-d { gpios = <&gpio7 3 GPIO_ACTIVE_LOW>; - linux,code = <32>; + linux,code = <KEY_D>; label = "SW33"; gpio-key,wakeup; debounce-interval = <20>; }; key-e { gpios = <&gpio7 4 GPIO_ACTIVE_LOW>; - linux,code = <18>; + linux,code = <KEY_E>; label = "SW34"; gpio-key,wakeup; debounce-interval = <20>; }; key-f { gpios = <&gpio7 5 GPIO_ACTIVE_LOW>; - linux,code = <33>; + linux,code = <KEY_F>; label = "SW35"; gpio-key,wakeup; debounce-interval = <20>; }; key-g { gpios = <&gpio7 6 GPIO_ACTIVE_LOW>; - linux,code = <34>; + linux,code = <KEY_G>; label = "SW36"; gpio-key,wakeup; debounce-interval = <20>; @@ -195,11 +229,16 @@ }; }; +&i2c6 { + status = "okay"; + clock-frequency = <100000>; +}; + &pfc { - pinctrl-0 = <&du_pins &scif0_pins &scif1_pins>; + pinctrl-0 = <&du_pins>; pinctrl-names = "default"; - i2c2_pins: i2c { + i2c2_pins: i2c2 { renesas,groups = "i2c2"; renesas,function = "i2c2"; }; @@ -244,10 +283,16 @@ renesas,function = "sdhi2"; }; - qspi_pins: spi { + qspi_pins: spi0 { renesas,groups = "qspi_ctrl", "qspi_data4"; renesas,function = "qspi"; }; + + msiof0_pins: spi1 { + renesas,groups = "msiof0_clk", "msiof0_sync", "msiof0_rx", + "msiof0_tx"; + renesas,function = "msiof0"; + }; }; ðer { @@ -262,6 +307,7 @@ reg = <1>; interrupt-parent = <&irqc0>; interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + micrel,led-mode = <1>; }; }; @@ -269,6 +315,20 @@ status = "okay"; }; +&scif0 { + pinctrl-0 = <&scif0_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&scif1 { + pinctrl-0 = <&scif1_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + &sdhi0 { pinctrl-0 = <&sdhi0_pins>; pinctrl-names = "default"; @@ -301,7 +361,7 @@ status = "okay"; }; -&spi { +&qspi { pinctrl-0 = <&qspi_pins>; pinctrl-names = "default"; @@ -313,6 +373,8 @@ compatible = "spansion,s25fl512s"; reg = <0>; spi-max-frequency = <30000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; m25p,fast-read; partition@0 { @@ -331,3 +393,18 @@ }; }; }; + +&msiof0 { + pinctrl-0 = <&msiof0_pins>; + pinctrl-names = "default"; + + status = "okay"; + + pmic: pmic@0 { + compatible = "renesas,r2a11302ft"; + reg = <0>; + spi-max-frequency = <6000000>; + spi-cpol; + spi-cpha; + }; +}; diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index 46181708e59c..8d7ffaeff6e0 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -27,6 +27,13 @@ i2c3 = &i2c3; i2c4 = &i2c4; i2c5 = &i2c5; + i2c6 = &i2c6; + i2c7 = &i2c7; + i2c8 = &i2c8; + spi0 = &qspi; + spi1 = &msiof0; + spi2 = &msiof1; + spi3 = &msiof2; }; cpus { @@ -37,14 +44,14 @@ device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0>; - clock-frequency = <1300000000>; + clock-frequency = <1500000000>; }; cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <1>; - clock-frequency = <1300000000>; + clock-frequency = <1500000000>; }; }; @@ -69,6 +76,7 @@ gpio-ranges = <&pfc 0 0 32>; #interrupt-cells = <2>; interrupt-controller; + clocks = <&mstp9_clks R8A7791_CLK_GPIO0>; }; gpio1: gpio@e6051000 { @@ -80,6 +88,7 @@ gpio-ranges = <&pfc 0 32 32>; #interrupt-cells = <2>; interrupt-controller; + clocks = <&mstp9_clks R8A7791_CLK_GPIO1>; }; gpio2: gpio@e6052000 { @@ -91,6 +100,7 @@ gpio-ranges = <&pfc 0 64 32>; #interrupt-cells = <2>; interrupt-controller; + clocks = <&mstp9_clks R8A7791_CLK_GPIO2>; }; gpio3: gpio@e6053000 { @@ -102,6 +112,7 @@ gpio-ranges = <&pfc 0 96 32>; #interrupt-cells = <2>; interrupt-controller; + clocks = <&mstp9_clks R8A7791_CLK_GPIO3>; }; gpio4: gpio@e6054000 { @@ -113,6 +124,7 @@ gpio-ranges = <&pfc 0 128 32>; #interrupt-cells = <2>; interrupt-controller; + clocks = <&mstp9_clks R8A7791_CLK_GPIO4>; }; gpio5: gpio@e6055000 { @@ -124,6 +136,7 @@ gpio-ranges = <&pfc 0 160 32>; #interrupt-cells = <2>; interrupt-controller; + clocks = <&mstp9_clks R8A7791_CLK_GPIO5>; }; gpio6: gpio@e6055400 { @@ -135,6 +148,7 @@ gpio-ranges = <&pfc 0 192 32>; #interrupt-cells = <2>; interrupt-controller; + clocks = <&mstp9_clks R8A7791_CLK_GPIO6>; }; gpio7: gpio@e6055800 { @@ -146,6 +160,7 @@ gpio-ranges = <&pfc 0 224 26>; #interrupt-cells = <2>; interrupt-controller; + clocks = <&mstp9_clks R8A7791_CLK_GPIO7>; }; thermal@e61f0000 { @@ -180,6 +195,7 @@ <0 17 IRQ_TYPE_LEVEL_HIGH>; }; + /* The memory map in the User's Manual maps the cores to bus numbers */ i2c0: i2c@e6508000 { #address-cells = <1>; #size-cells = <0>; @@ -231,6 +247,7 @@ }; i2c5: i2c@e6528000 { + /* doesn't need pinmux */ #address-cells = <1>; #size-cells = <0>; compatible = "renesas,i2c-r8a7791"; @@ -240,6 +257,37 @@ status = "disabled"; }; + i2c6: i2c@e60b0000 { + /* doesn't need pinmux */ + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic"; + reg = <0 0xe60b0000 0 0x425>; + interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R8A7791_CLK_IICDVFS>; + status = "disabled"; + }; + + i2c7: i2c@e6500000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic"; + reg = <0 0xe6500000 0 0x425>; + interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7791_CLK_IIC0>; + status = "disabled"; + }; + + i2c8: i2c@e6510000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic"; + reg = <0 0xe6510000 0 0x425>; + interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7791_CLK_IIC1>; + status = "disabled"; + }; + pfc: pfc@e6060000 { compatible = "renesas,pfc-r8a7791"; reg = <0 0xe6060000 0 0x250>; @@ -249,7 +297,6 @@ sdhi0: sd@ee100000 { compatible = "renesas,sdhi-r8a7791"; reg = <0 0xee100000 0 0x200>; - interrupt-parent = <&gic>; interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7791_CLK_SDHI0>; status = "disabled"; @@ -258,7 +305,6 @@ sdhi1: sd@ee140000 { compatible = "renesas,sdhi-r8a7791"; reg = <0 0xee140000 0 0x100>; - interrupt-parent = <&gic>; interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7791_CLK_SDHI1>; status = "disabled"; @@ -267,7 +313,6 @@ sdhi2: sd@ee160000 { compatible = "renesas,sdhi-r8a7791"; reg = <0 0xee160000 0 0x100>; - interrupt-parent = <&gic>; interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7791_CLK_SDHI2>; status = "disabled"; @@ -688,7 +733,7 @@ renesas,clock-indices = < R8A7791_CLK_TMU1 R8A7791_CLK_TMU3 R8A7791_CLK_TMU2 R8A7791_CLK_CMT0 R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1 - R8A7791_CLK_VSP1_DU0 R8A7791_CLK_VSP1_SY + R8A7791_CLK_VSP1_DU0 R8A7791_CLK_VSP1_S >; clock-output-names = "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1", @@ -712,15 +757,16 @@ mstp3_clks: mstp3_clks@e615013c { compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; - clocks = <&cp_clk>, <&sd2_clk>, <&sd1_clk>, - <&cpg_clocks R8A7791_CLK_SD0>, <&mmc0_clk>, <&rclk_clk>; + clocks = <&cp_clk>, <&sd2_clk>, <&sd1_clk>, <&cpg_clocks R8A7791_CLK_SD0>, + <&mmc0_clk>, <&hp_clk>, <&hp_clk>, <&rclk_clk>; #clock-cells = <1>; renesas,clock-indices = < - R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1 - R8A7791_CLK_SDHI0 R8A7791_CLK_MMCIF0 R8A7791_CLK_CMT1 + R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1 R8A7791_CLK_SDHI0 + R8A7791_CLK_MMCIF0 R8A7791_CLK_IIC0 R8A7791_CLK_IIC1 R8A7791_CLK_CMT1 >; clock-output-names = - "tpu0", "sdhi2", "sdhi1", "sdhi0", "mmcif0", "cmt1"; + "tpu0", "sdhi2", "sdhi1", "sdhi0", + "mmcif0", "i2c7", "i2c8", "cmt1"; }; mstp5_clks: mstp5_clks@e6150144 { compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; @@ -733,19 +779,19 @@ mstp7_clks: mstp7_clks@e615014c { compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; - clocks = <&mp_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>, + clocks = <&mp_clk>, <&mp_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>; #clock-cells = <1>; renesas,clock-indices = < - R8A7791_CLK_HSUSB R8A7791_CLK_HSCIF2 R8A7791_CLK_SCIF5 + R8A7791_CLK_EHCI R8A7791_CLK_HSUSB R8A7791_CLK_HSCIF2 R8A7791_CLK_SCIF5 R8A7791_CLK_SCIF4 R8A7791_CLK_HSCIF1 R8A7791_CLK_HSCIF0 R8A7791_CLK_SCIF3 R8A7791_CLK_SCIF2 R8A7791_CLK_SCIF1 R8A7791_CLK_SCIF0 R8A7791_CLK_DU1 R8A7791_CLK_DU0 R8A7791_CLK_LVDS0 >; clock-output-names = - "hsusb", "hscif2", "scif5", "scif4", "hscif1", "hscif0", + "ehci", "hsusb", "hscif2", "scif5", "scif4", "hscif1", "hscif0", "scif3", "scif2", "scif1", "scif0", "du1", "du0", "lvds0"; }; mstp8_clks: mstp8_clks@e6150990 { @@ -764,18 +810,23 @@ mstp9_clks: mstp9_clks@e6150994 { compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>; - clocks = <&p_clk>, <&p_clk>, <&cpg_clocks R8A7791_CLK_QSPI>, - <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, - <&p_clk>; + clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, + <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, + <&p_clk>, <&p_clk>, <&cpg_clocks R8A7791_CLK_QSPI>, <&hp_clk>, + <&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>, + <&hp_clk>, <&hp_clk>; #clock-cells = <1>; renesas,clock-indices = < - R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD - R8A7791_CLK_I2C5 R8A7791_CLK_I2C4 R8A7791_CLK_I2C3 - R8A7791_CLK_I2C2 R8A7791_CLK_I2C1 R8A7791_CLK_I2C0 + R8A7791_CLK_GPIO7 R8A7791_CLK_GPIO6 R8A7791_CLK_GPIO5 R8A7791_CLK_GPIO4 + R8A7791_CLK_GPIO3 R8A7791_CLK_GPIO2 R8A7791_CLK_GPIO1 R8A7791_CLK_GPIO0 + R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD R8A7791_CLK_I2C5 + R8A7791_CLK_IICDVFS R8A7791_CLK_I2C4 R8A7791_CLK_I2C3 R8A7791_CLK_I2C2 + R8A7791_CLK_I2C1 R8A7791_CLK_I2C0 >; clock-output-names = - "rcan1", "rcan0", "qspi_mod", "i2c5", "i2c4", "i2c3", - "i2c2", "i2c1", "i2c0"; + "gpio7", "gpio6", "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0", + "rcan1", "rcan0", "qspi_mod", "i2c5", "i2c6", "i2c4", "i2c3", "i2c2", + "i2c1", "i2c0"; }; mstp11_clks: mstp11_clks@e615099c { compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; @@ -789,7 +840,7 @@ }; }; - spi: spi@e6b10000 { + qspi: spi@e6b10000 { compatible = "renesas,qspi-r8a7791", "renesas,qspi"; reg = <0 0xe6b10000 0 0x2c>; interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>; @@ -799,4 +850,34 @@ #size-cells = <0>; status = "disabled"; }; + + msiof0: spi@e6e20000 { + compatible = "renesas,msiof-r8a7791"; + reg = <0 0xe6e20000 0 0x0064>; + interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof1: spi@e6e10000 { + compatible = "renesas,msiof-r8a7791"; + reg = <0 0xe6e10000 0 0x0064>; + interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A7791_CLK_MSIOF1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof2: spi@e6e00000 { + compatible = "renesas,msiof-r8a7791"; + reg = <0 0xe6e00000 0 0x0064>; + interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A7791_CLK_MSIOF2>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; diff --git a/arch/arm/boot/dts/rk3066a-bqcurie2.dts b/arch/arm/boot/dts/rk3066a-bqcurie2.dts index 035df4053c21..afb327322a4a 100644 --- a/arch/arm/boot/dts/rk3066a-bqcurie2.dts +++ b/arch/arm/boot/dts/rk3066a-bqcurie2.dts @@ -18,6 +18,7 @@ / { model = "bq Curie 2"; + compatible = "mundoreader,bq-curie2", "rockchip,rk3066a"; memory { reg = <0x60000000 0x40000000>; diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi index 4d4dfbb59f4b..4387cfd420ba 100644 --- a/arch/arm/boot/dts/rk3066a.dtsi +++ b/arch/arm/boot/dts/rk3066a.dtsi @@ -24,6 +24,7 @@ cpus { #address-cells = <1>; #size-cells = <0>; + enable-method = "rockchip,rk3066-smp"; cpu@0 { device_type = "cpu"; @@ -79,7 +80,7 @@ pinctrl@20008000 { compatible = "rockchip,rk3066a-pinctrl"; - reg = <0x20008000 0x150>; + rockchip,grf = <&grf>; #address-cells = <1>; #size-cells = <1>; ranges; diff --git a/arch/arm/boot/dts/rk3188-radxarock.dts b/arch/arm/boot/dts/rk3188-radxarock.dts index 3ba1968a70ab..a5eee55079cb 100644 --- a/arch/arm/boot/dts/rk3188-radxarock.dts +++ b/arch/arm/boot/dts/rk3188-radxarock.dts @@ -17,6 +17,7 @@ / { model = "Radxa Rock"; + compatible = "radxa,rock", "rockchip,rk3188"; memory { reg = <0x60000000 0x80000000>; diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi index ed9a70af3e3f..238c996d4a7f 100644 --- a/arch/arm/boot/dts/rk3188.dtsi +++ b/arch/arm/boot/dts/rk3188.dtsi @@ -24,6 +24,7 @@ cpus { #address-cells = <1>; #size-cells = <0>; + enable-method = "rockchip,rk3066-smp"; cpu@0 { device_type = "cpu"; @@ -75,17 +76,16 @@ pinctrl@20008000 { compatible = "rockchip,rk3188-pinctrl"; - reg = <0x20008000 0xa0>, - <0x20008164 0x1a0>; - reg-names = "base", "pull"; + rockchip,grf = <&grf>; + rockchip,pmu = <&pmu>; + #address-cells = <1>; #size-cells = <1>; ranges; gpio0: gpio0@0x2000a000 { compatible = "rockchip,rk3188-gpio-bank0"; - reg = <0x2000a000 0x100>, - <0x20004064 0x8>; + reg = <0x2000a000 0x100>; interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk_gates8 9>; diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi index 26e5a968d49d..2adf1cc9e85d 100644 --- a/arch/arm/boot/dts/rk3xxx.dtsi +++ b/arch/arm/boot/dts/rk3xxx.dtsi @@ -31,11 +31,16 @@ reg = <0x1013c000 0x100>; }; - pmu@20004000 { - compatible = "rockchip,rk3066-pmu"; + pmu: pmu@20004000 { + compatible = "rockchip,rk3066-pmu", "syscon"; reg = <0x20004000 0x100>; }; + grf: grf@20008000 { + compatible = "syscon"; + reg = <0x20008000 0x200>; + }; + gic: interrupt-controller@1013d000 { compatible = "arm,cortex-a9-gic"; interrupt-controller; diff --git a/arch/arm/boot/dts/s3c2416-smdk2416.dts b/arch/arm/boot/dts/s3c2416-smdk2416.dts index 59594cf15998..ea92fd69529a 100644 --- a/arch/arm/boot/dts/s3c2416-smdk2416.dts +++ b/arch/arm/boot/dts/s3c2416-smdk2416.dts @@ -19,6 +19,19 @@ reg = <0x30000000 0x4000000>; }; + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + xti: xti { + compatible = "fixed-clock"; + clock-frequency = <12000000>; + clock-output-names = "xti"; + #clock-cells = <0>; + }; + }; + serial@50000000 { status = "okay"; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/s3c2416.dtsi b/arch/arm/boot/dts/s3c2416.dtsi index e6555bdd81b8..955e4a4f8c31 100644 --- a/arch/arm/boot/dts/s3c2416.dtsi +++ b/arch/arm/boot/dts/s3c2416.dtsi @@ -8,6 +8,7 @@ * published by the Free Software Foundation. */ +#include <dt-bindings/clock/s3c2443.h> #include "s3c24xx.dtsi" #include "s3c2416-pinctrl.dtsi" @@ -28,26 +29,53 @@ compatible = "samsung,s3c2416-irq"; }; + clocks: clock-controller@0x4c000000 { + compatible = "samsung,s3c2416-clock"; + reg = <0x4c000000 0x40>; + #clock-cells = <1>; + }; + pinctrl@56000000 { compatible = "samsung,s3c2416-pinctrl"; }; + timer@51000000 { + clocks = <&clocks PCLK_PWM>; + clock-names = "timers"; + }; + serial@50000000 { compatible = "samsung,s3c2440-uart"; + clock-names = "uart", "clk_uart_baud2", + "clk_uart_baud3"; + clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>, + <&clocks SCLK_UART>; }; serial@50004000 { compatible = "samsung,s3c2440-uart"; + clock-names = "uart", "clk_uart_baud2", + "clk_uart_baud3"; + clocks = <&clocks PCLK_UART1>, <&clocks PCLK_UART1>, + <&clocks SCLK_UART>; }; serial@50008000 { compatible = "samsung,s3c2440-uart"; + clock-names = "uart", "clk_uart_baud2", + "clk_uart_baud3"; + clocks = <&clocks PCLK_UART2>, <&clocks PCLK_UART2>, + <&clocks SCLK_UART>; }; serial@5000C000 { compatible = "samsung,s3c2440-uart"; reg = <0x5000C000 0x4000>; interrupts = <1 18 24 4>, <1 18 25 4>; + clock-names = "uart", "clk_uart_baud2", + "clk_uart_baud3"; + clocks = <&clocks PCLK_UART3>, <&clocks PCLK_UART3>, + <&clocks SCLK_UART>; status = "disabled"; }; @@ -55,6 +83,10 @@ compatible = "samsung,s3c6410-sdhci"; reg = <0x4AC00000 0x100>; interrupts = <0 0 21 3>; + clock-names = "hsmmc", "mmc_busclk.0", + "mmc_busclk.2"; + clocks = <&clocks HCLK_HSMMC0>, <&clocks HCLK_HSMMC0>, + <&clocks MUX_HSMMC0>; status = "disabled"; }; @@ -62,18 +94,28 @@ compatible = "samsung,s3c6410-sdhci"; reg = <0x4A800000 0x100>; interrupts = <0 0 20 3>; + clock-names = "hsmmc", "mmc_busclk.0", + "mmc_busclk.2"; + clocks = <&clocks HCLK_HSMMC1>, <&clocks HCLK_HSMMC1>, + <&clocks MUX_HSMMC1>; status = "disabled"; }; watchdog@53000000 { interrupts = <1 9 27 3>; + clocks = <&clocks PCLK_WDT>; + clock-names = "watchdog"; }; rtc@57000000 { compatible = "samsung,s3c2416-rtc"; + clocks = <&clocks PCLK_RTC>; + clock-names = "rtc"; }; i2c@54000000 { compatible = "samsung,s3c2440-i2c"; + clocks = <&clocks PCLK_I2C0>; + clock-names = "i2c"; }; }; diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi index a106b0872910..e0b15a6e8897 100644 --- a/arch/arm/boot/dts/sama5d3.dtsi +++ b/arch/arm/boot/dts/sama5d3.dtsi @@ -58,6 +58,18 @@ reg = <0x20000000 0x8000000>; }; + slow_xtal: slow_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + main_xtal: main_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + clocks { adc_op_clk: adc_op_clk{ compatible = "fixed-clock"; @@ -113,6 +125,9 @@ compatible = "atmel,at91sam9g45-ssc"; reg = <0xf0008000 0x4000>; interrupts = <38 IRQ_TYPE_LEVEL_HIGH 4>; + dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(13)>, + <&dma0 2 AT91_DMA_CFG_PER_ID(14)>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; clocks = <&ssc0_clk>; @@ -231,6 +246,9 @@ compatible = "atmel,at91sam9g45-ssc"; reg = <0xf800c000 0x4000>; interrupts = <39 IRQ_TYPE_LEVEL_HIGH 4>; + dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(3)>, + <&dma1 2 AT91_DMA_CFG_PER_ID(4)>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; clocks = <&ssc1_clk>; @@ -577,6 +595,84 @@ }; }; + pwm0 { + pinctrl_pwm0_pwmh0_0: pwm0_pwmh0-0 { + atmel,pins = + <AT91_PIOA 20 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with ISI_D4 and LCDDAT20 */ + }; + pinctrl_pwm0_pwmh0_1: pwm0_pwmh0-1 { + atmel,pins = + <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GTX0 */ + }; + pinctrl_pwm0_pwml0_0: pwm0_pwml0-0 { + atmel,pins = + <AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with ISI_D5 and LCDDAT21 */ + }; + pinctrl_pwm0_pwml0_1: pwm0_pwml0-1 { + atmel,pins = + <AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GTX1 */ + }; + + pinctrl_pwm0_pwmh1_0: pwm0_pwmh1-0 { + atmel,pins = + <AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with ISI_D6 and LCDDAT22 */ + }; + pinctrl_pwm0_pwmh1_1: pwm0_pwmh1-1 { + atmel,pins = + <AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GRX0 */ + }; + pinctrl_pwm0_pwmh1_2: pwm0_pwmh1-2 { + atmel,pins = + <AT91_PIOB 27 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with G125CKO and RTS1 */ + }; + pinctrl_pwm0_pwml1_0: pwm0_pwml1-0 { + atmel,pins = + <AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with ISI_D7 and LCDDAT23 */ + }; + pinctrl_pwm0_pwml1_1: pwm0_pwml1-1 { + atmel,pins = + <AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GRX1 */ + }; + pinctrl_pwm0_pwml1_2: pwm0_pwml1-2 { + atmel,pins = + <AT91_PIOE 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with IRQ */ + }; + + pinctrl_pwm0_pwmh2_0: pwm0_pwmh2-0 { + atmel,pins = + <AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GTXCK */ + }; + pinctrl_pwm0_pwmh2_1: pwm0_pwmh2-1 { + atmel,pins = + <AT91_PIOD 5 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with MCI0_DA4 and TIOA0 */ + }; + pinctrl_pwm0_pwml2_0: pwm0_pwml2-0 { + atmel,pins = + <AT91_PIOB 9 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GTXEN */ + }; + pinctrl_pwm0_pwml2_1: pwm0_pwml2-1 { + atmel,pins = + <AT91_PIOD 6 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with MCI0_DA5 and TIOB0 */ + }; + + pinctrl_pwm0_pwmh3_0: pwm0_pwmh3-0 { + atmel,pins = + <AT91_PIOB 12 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GRXDV */ + }; + pinctrl_pwm0_pwmh3_1: pwm0_pwmh3-1 { + atmel,pins = + <AT91_PIOD 7 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with MCI0_DA6 and TCLK0 */ + }; + pinctrl_pwm0_pwml3_0: pwm0_pwml3-0 { + atmel,pins = + <AT91_PIOB 13 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GRXER */ + }; + pinctrl_pwm0_pwml3_1: pwm0_pwml3-1 { + atmel,pins = + <AT91_PIOD 8 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with MCI0_DA7 */ + }; + }; + spi0 { pinctrl_spi0: spi0-0 { atmel,pins = @@ -749,18 +845,29 @@ #size-cells = <0>; #interrupt-cells = <1>; - clk32k: slck { - compatible = "fixed-clock"; + main_rc_osc: main_rc_osc { + compatible = "atmel,at91sam9x5-clk-main-rc-osc"; #clock-cells = <0>; - clock-frequency = <32768>; + interrupt-parent = <&pmc>; + interrupts = <AT91_PMC_MOSCRCS>; + clock-frequency = <12000000>; + clock-accuracy = <50000000>; }; - main: mainck { - compatible = "atmel,at91rm9200-clk-main"; + main_osc: main_osc { + compatible = "atmel,at91rm9200-clk-main-osc"; #clock-cells = <0>; interrupt-parent = <&pmc>; interrupts = <AT91_PMC_MOSCS>; - clocks = <&clk32k>; + clocks = <&main_xtal>; + }; + + main: mainck { + compatible = "atmel,at91sam9x5-clk-main"; + #clock-cells = <0>; + interrupt-parent = <&pmc>; + interrupts = <AT91_PMC_MOSCSELS>; + clocks = <&main_rc_osc &main_osc>; }; plla: pllack { @@ -1089,6 +1196,32 @@ status = "disabled"; }; + sckc@fffffe50 { + compatible = "atmel,at91sam9x5-sckc"; + reg = <0xfffffe50 0x4>; + + slow_rc_osc: slow_rc_osc { + compatible = "atmel,at91sam9x5-clk-slow-rc-osc"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-accuracy = <50000000>; + atmel,startup-time-usec = <75>; + }; + + slow_osc: slow_osc { + compatible = "atmel,at91sam9x5-clk-slow-osc"; + #clock-cells = <0>; + clocks = <&slow_xtal>; + atmel,startup-time-usec = <1200000>; + }; + + clk32k: slowck { + compatible = "atmel,at91sam9x5-clk-slow"; + #clock-cells = <0>; + clocks = <&slow_rc_osc &slow_osc>; + }; + }; + rtc@fffffeb0 { compatible = "atmel,at91rm9200-rtc"; reg = <0xfffffeb0 0x30>; diff --git a/arch/arm/boot/dts/sama5d3xcm.dtsi b/arch/arm/boot/dts/sama5d3xcm.dtsi index f55ed072c8e6..b0b1331c1974 100644 --- a/arch/arm/boot/dts/sama5d3xcm.dtsi +++ b/arch/arm/boot/dts/sama5d3xcm.dtsi @@ -18,6 +18,14 @@ reg = <0x20000000 0x20000000>; }; + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <12000000>; + }; + ahb { apb { spi0: spi@f0004000 { diff --git a/arch/arm/boot/dts/sama5d3xmb.dtsi b/arch/arm/boot/dts/sama5d3xmb.dtsi index dba739b6ef36..306eef0f97ef 100644 --- a/arch/arm/boot/dts/sama5d3xmb.dtsi +++ b/arch/arm/boot/dts/sama5d3xmb.dtsi @@ -32,6 +32,10 @@ }; }; + ssc0: ssc@f0008000 { + atmel,clk-from-rk-pin; + }; + /* * i2c0 conflicts with ISI: * disable it to allow the use of ISI @@ -156,7 +160,7 @@ }; sound { - compatible = "atmel,sama5d3ek-wm8904"; + compatible = "atmel,asoc-wm8904"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pck0_as_audio_mck>; @@ -166,9 +170,12 @@ "Headphone Jack", "HPOUTR", "IN2L", "Line In Jack", "IN2R", "Line In Jack", + "MICBIAS", "IN1L", "IN1L", "Mic"; atmel,ssc-controller = <&ssc0>; atmel,audio-codec = <&wm8904>; + + status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts index eb8886b535e4..a99171c8a782 100644 --- a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts +++ b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts @@ -14,6 +14,7 @@ /dts-v1/; #include "sh73a0.dtsi" #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> #include <dt-bindings/interrupt-controller/irq.h> / { @@ -112,43 +113,43 @@ back-key { gpios = <&pcf8575 8 GPIO_ACTIVE_LOW>; - linux,code = <158>; + linux,code = <KEY_BACK>; label = "SW3"; }; right-key { gpios = <&pcf8575 9 GPIO_ACTIVE_LOW>; - linux,code = <106>; + linux,code = <KEY_RIGHT>; label = "SW2-R"; }; left-key { gpios = <&pcf8575 10 GPIO_ACTIVE_LOW>; - linux,code = <105>; + linux,code = <KEY_LEFT>; label = "SW2-L"; }; enter-key { gpios = <&pcf8575 11 GPIO_ACTIVE_LOW>; - linux,code = <28>; + linux,code = <KEY_ENTER>; label = "SW2-P"; }; up-key { gpios = <&pcf8575 12 GPIO_ACTIVE_LOW>; - linux,code = <103>; + linux,code = <KEY_UP>; label = "SW2-U"; }; down-key { gpios = <&pcf8575 13 GPIO_ACTIVE_LOW>; - linux,code = <108>; + linux,code = <KEY_DOWN>; label = "SW2-D"; }; home-key { gpios = <&pcf8575 14 GPIO_ACTIVE_LOW>; - linux,code = <102>; + linux,code = <KEY_HOME>; label = "SW1"; }; }; diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index 56fc214e6d2c..4676f25e87a7 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -15,7 +15,8 @@ * along with this program. If not, see <http://www.gnu.org/licenses/>. */ -/include/ "skeleton.dtsi" +#include "skeleton.dtsi" +#include <dt-bindings/reset/altr,rst-mgr.h> / { #address-cells = <1>; @@ -75,7 +76,14 @@ pdma: pdma@ffe01000 { compatible = "arm,pl330", "arm,primecell"; reg = <0xffe01000 0x1000>; - interrupts = <0 180 4>; + interrupts = <0 104 4>, + <0 105 4>, + <0 106 4>, + <0 107 4>, + <0 108 4>, + <0 109 4>, + <0 110 4>, + <0 111 4>; #dma-cells = <1>; #dma-channels = <8>; #dma-requests = <32>; @@ -84,6 +92,22 @@ }; }; + can0: can@ffc00000 { + compatible = "bosch,d_can"; + reg = <0xffc00000 0x1000>; + interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>; + clocks = <&can0_clk>; + status = "disabled"; + }; + + can1: can@ffc01000 { + compatible = "bosch,d_can"; + reg = <0xffc01000 0x1000>; + interrupts = <0 135 4>, <0 136 4>, <0 137 4>, <0 138 4>; + clocks = <&can1_clk>; + status = "disabled"; + }; + clkmgr@ffd04000 { compatible = "altr,clk-mgr"; reg = <0xffd04000 0x1000>; @@ -124,7 +148,7 @@ #clock-cells = <0>; compatible = "altr,socfpga-perip-clk"; clocks = <&main_pll>; - fixed-divider = <2>; + div-reg = <0xe0 0 9>; reg = <0x48>; }; @@ -132,7 +156,7 @@ #clock-cells = <0>; compatible = "altr,socfpga-perip-clk"; clocks = <&main_pll>; - fixed-divider = <4>; + div-reg = <0xe4 0 9>; reg = <0x4C>; }; @@ -140,7 +164,7 @@ #clock-cells = <0>; compatible = "altr,socfpga-perip-clk"; clocks = <&main_pll>; - fixed-divider = <4>; + div-reg = <0xe8 0 9>; reg = <0x50>; }; @@ -460,6 +484,8 @@ mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */ clocks = <&emac0_clk>; clock-names = "stmmaceth"; + resets = <&rst EMAC0_RESET>; + reset-names = "stmmaceth"; status = "disabled"; }; @@ -472,9 +498,111 @@ mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */ clocks = <&emac1_clk>; clock-names = "stmmaceth"; + resets = <&rst EMAC1_RESET>; + reset-names = "stmmaceth"; + status = "disabled"; + }; + + i2c0: i2c@ffc04000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xffc04000 0x1000>; + clocks = <&l4_sp_clk>; + interrupts = <0 158 0x4>; + status = "disabled"; + }; + + i2c1: i2c@ffc05000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xffc05000 0x1000>; + clocks = <&l4_sp_clk>; + interrupts = <0 159 0x4>; status = "disabled"; }; + i2c2: i2c@ffc06000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xffc06000 0x1000>; + clocks = <&l4_sp_clk>; + interrupts = <0 160 0x4>; + status = "disabled"; + }; + + i2c3: i2c@ffc07000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xffc07000 0x1000>; + clocks = <&l4_sp_clk>; + interrupts = <0 161 0x4>; + status = "disabled"; + }; + + gpio@ff708000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-gpio"; + reg = <0xff708000 0x1000>; + clocks = <&per_base_clk>; + status = "disabled"; + + gpio0: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <29>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 164 4>; + }; + }; + + gpio@ff709000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-gpio"; + reg = <0xff709000 0x1000>; + clocks = <&per_base_clk>; + status = "disabled"; + + gpio1: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <29>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 165 4>; + }; + }; + + gpio@ff70a000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-gpio"; + reg = <0xff70a000 0x1000>; + clocks = <&per_base_clk>; + status = "disabled"; + + gpio2: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <27>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 166 4>; + }; + }; + L2: l2-cache@fffef000 { compatible = "arm,pl310-cache"; reg = <0xfffef000 0x1000>; @@ -508,24 +636,32 @@ compatible = "snps,dw-apb-timer"; interrupts = <0 167 4>; reg = <0xffc08000 0x1000>; + clocks = <&l4_sp_clk>; + clock-names = "timer"; }; timer1: timer1@ffc09000 { compatible = "snps,dw-apb-timer"; interrupts = <0 168 4>; reg = <0xffc09000 0x1000>; + clocks = <&l4_sp_clk>; + clock-names = "timer"; }; timer2: timer2@ffd00000 { compatible = "snps,dw-apb-timer"; interrupts = <0 169 4>; reg = <0xffd00000 0x1000>; + clocks = <&osc1>; + clock-names = "timer"; }; timer3: timer3@ffd01000 { compatible = "snps,dw-apb-timer"; interrupts = <0 170 4>; reg = <0xffd01000 0x1000>; + clocks = <&osc1>; + clock-names = "timer"; }; uart0: serial0@ffc02000 { @@ -534,6 +670,7 @@ interrupts = <0 162 4>; reg-shift = <2>; reg-io-width = <4>; + clocks = <&l4_sp_clk>; }; uart1: serial1@ffc03000 { @@ -542,13 +679,58 @@ interrupts = <0 163 4>; reg-shift = <2>; reg-io-width = <4>; + clocks = <&l4_sp_clk>; }; - rstmgr@ffd05000 { + rst: rstmgr@ffd05000 { compatible = "altr,rst-mgr"; reg = <0xffd05000 0x1000>; }; + usbphy0: usbphy@0 { + #phy-cells = <0>; + compatible = "usb-nop-xceiv"; + status = "okay"; + }; + + usb0: usb@ffb00000 { + compatible = "snps,dwc2"; + reg = <0xffb00000 0xffff>; + interrupts = <0 125 4>; + clocks = <&usb_mp_clk>; + clock-names = "otg"; + phys = <&usbphy0>; + phy-names = "usb2-phy"; + status = "disabled"; + }; + + usb1: usb@ffb40000 { + compatible = "snps,dwc2"; + reg = <0xffb40000 0xffff>; + interrupts = <0 128 4>; + clocks = <&usb_mp_clk>; + clock-names = "otg"; + phys = <&usbphy0>; + phy-names = "usb2-phy"; + status = "disabled"; + }; + + watchdog0: watchdog@ffd02000 { + compatible = "snps,dw-wdt"; + reg = <0xffd02000 0x1000>; + interrupts = <0 171 4>; + clocks = <&osc1>; + status = "disabled"; + }; + + watchdog1: watchdog@ffd03000 { + compatible = "snps,dw-wdt"; + reg = <0xffd03000 0x1000>; + interrupts = <0 172 4>; + clocks = <&osc1>; + status = "disabled"; + }; + sysmgr: sysmgr@ffd08000 { compatible = "altr,sys-mgr", "syscon"; reg = <0xffd08000 0x4000>; diff --git a/arch/arm/boot/dts/socfpga_arria5.dtsi b/arch/arm/boot/dts/socfpga_arria5.dtsi index 6c87b7070ca7..12d1c2ccaf5b 100644 --- a/arch/arm/boot/dts/socfpga_arria5.dtsi +++ b/arch/arm/boot/dts/socfpga_arria5.dtsi @@ -15,7 +15,7 @@ */ /dts-v1/; -/include/ "socfpga.dtsi" +#include "socfpga.dtsi" / { soc { @@ -38,32 +38,8 @@ }; }; - serial0@ffc02000 { - clock-frequency = <100000000>; - }; - - serial1@ffc03000 { - clock-frequency = <100000000>; - }; - sysmgr@ffd08000 { cpu1-start-addr = <0xffd080c4>; }; - - timer0@ffc08000 { - clock-frequency = <100000000>; - }; - - timer1@ffc09000 { - clock-frequency = <100000000>; - }; - - timer2@ffd00000 { - clock-frequency = <25000000>; - }; - - timer3@ffd01000 { - clock-frequency = <25000000>; - }; }; }; diff --git a/arch/arm/boot/dts/socfpga_arria5_socdk.dts b/arch/arm/boot/dts/socfpga_arria5_socdk.dts index a87ee1c07661..d532d171e391 100644 --- a/arch/arm/boot/dts/socfpga_arria5_socdk.dts +++ b/arch/arm/boot/dts/socfpga_arria5_socdk.dts @@ -15,7 +15,7 @@ * along with this program. If not, see <http://www.gnu.org/licenses/>. */ -/include/ "socfpga_arria5.dtsi" +#include "socfpga_arria5.dtsi" / { model = "Altera SOCFPGA Arria V SoC Development Kit"; @@ -59,3 +59,22 @@ rxdv-skew-ps = <0>; rxc-skew-ps = <2000>; }; + +&i2c0 { + status = "okay"; + + eeprom@51 { + compatible = "atmel,24c32"; + reg = <0x51>; + pagesize = <32>; + }; + + rtc@68 { + compatible = "dallas,ds1339"; + reg = <0x68>; + }; +}; + +&usb1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dtsi b/arch/arm/boot/dts/socfpga_cyclone5.dtsi index ca41b0ebf461..bf511828729f 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5.dtsi +++ b/arch/arm/boot/dts/socfpga_cyclone5.dtsi @@ -16,7 +16,7 @@ */ /dts-v1/; -/include/ "socfpga.dtsi" +#include "socfpga.dtsi" / { soc { @@ -45,30 +45,6 @@ status = "okay"; }; - timer0@ffc08000 { - clock-frequency = <100000000>; - }; - - timer1@ffc09000 { - clock-frequency = <100000000>; - }; - - timer2@ffd00000 { - clock-frequency = <25000000>; - }; - - timer3@ffd01000 { - clock-frequency = <25000000>; - }; - - serial0@ffc02000 { - clock-frequency = <100000000>; - }; - - serial1@ffc03000 { - clock-frequency = <100000000>; - }; - sysmgr@ffd08000 { cpu1-start-addr = <0xffd080c4>; }; diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts index ae16d975196d..45de1514af0a 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts @@ -15,7 +15,7 @@ * along with this program. If not, see <http://www.gnu.org/licenses/>. */ -/include/ "socfpga_cyclone5.dtsi" +#include "socfpga_cyclone5.dtsi" / { model = "Altera SOCFPGA Cyclone V SoC Development Kit"; @@ -52,3 +52,22 @@ rxdv-skew-ps = <0>; rxc-skew-ps = <2000>; }; + +&i2c0 { + status = "okay"; + + eeprom@51 { + compatible = "atmel,24c32"; + reg = <0x51>; + pagesize = <32>; + }; + + rtc@68 { + compatible = "dallas,ds1339"; + reg = <0x68>; + }; +}; + +&usb1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts b/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts index b79e2a2bf175..d26f155f5fd9 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts @@ -15,7 +15,7 @@ * along with this program. If not, see <http://www.gnu.org/licenses/>. */ -/include/ "socfpga_cyclone5.dtsi" +#include "socfpga_cyclone5.dtsi" / { model = "Terasic SoCkit"; @@ -52,3 +52,7 @@ rxdv-skew-ps = <0>; rxc-skew-ps = <2000>; }; + +&usb1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts b/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts new file mode 100644 index 000000000000..a1814b457450 --- /dev/null +++ b/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include "socfpga_cyclone5.dtsi" + +/ { + model = "EBV SOCrates"; + compatible = "ebv,socrates", "altr,socfpga-cyclone5", "altr,socfpga"; + + chosen { + bootargs = "console=ttyS0,115200"; + }; + + memory { + name = "memory"; + device_type = "memory"; + reg = <0x0 0x40000000>; /* 1GB */ + }; +}; + +&gmac1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + rtc: rtc@68 { + compatible = "stm,m41t82"; + reg = <0x68>; + }; +}; + +&mmc { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/socfpga_vt.dts b/arch/arm/boot/dts/socfpga_vt.dts index 87d6f759a9c1..09792b411110 100644 --- a/arch/arm/boot/dts/socfpga_vt.dts +++ b/arch/arm/boot/dts/socfpga_vt.dts @@ -16,7 +16,7 @@ */ /dts-v1/; -/include/ "socfpga.dtsi" +#include "socfpga.dtsi" / { model = "Altera SOCFPGA VT"; diff --git a/arch/arm/boot/dts/ste-ccu9540.dts b/arch/arm/boot/dts/ste-ccu9540.dts index 229508750890..651c56d400a4 100644 --- a/arch/arm/boot/dts/ste-ccu9540.dts +++ b/arch/arm/boot/dts/ste-ccu9540.dts @@ -38,8 +38,8 @@ arm,primecell-periphid = <0x10480180>; max-frequency = <100000000>; bus-width = <4>; - mmc-cap-sd-highspeed; - mmc-cap-mmc-highspeed; + cap-sd-highspeed; + cap-mmc-highspeed; vmmc-supply = <&ab8500_ldo_aux3_reg>; cd-gpios = <&gpio7 6 0x4>; // 230 @@ -63,7 +63,7 @@ arm,primecell-periphid = <0x10480180>; max-frequency = <100000000>; bus-width = <8>; - mmc-cap-mmc-highspeed; + cap-mmc-highspeed; vmmc-supply = <&ab8500_ldo_aux2_reg>; status = "okay"; diff --git a/arch/arm/boot/dts/ste-href.dtsi b/arch/arm/boot/dts/ste-href.dtsi index 6cb9b68e2188..bf8f0eddc2c0 100644 --- a/arch/arm/boot/dts/ste-href.dtsi +++ b/arch/arm/boot/dts/ste-href.dtsi @@ -116,8 +116,15 @@ arm,primecell-periphid = <0x10480180>; max-frequency = <100000000>; bus-width = <4>; - mmc-cap-sd-highspeed; - mmc-cap-mmc-highspeed; + cap-sd-highspeed; + cap-mmc-highspeed; + sd-uhs-sdr12; + sd-uhs-sdr25; + full-pwr-cycle; + st,sig-dir-dat0; + st,sig-dir-dat2; + st,sig-dir-cmd; + st,sig-pin-fbclk; vmmc-supply = <&ab8500_ldo_aux3_reg>; vqmmc-supply = <&vmmci>; pinctrl-names = "default", "sleep"; @@ -132,6 +139,7 @@ arm,primecell-periphid = <0x10480180>; max-frequency = <100000000>; bus-width = <4>; + non-removable; pinctrl-names = "default", "sleep"; pinctrl-0 = <&sdi1_default_mode>; pinctrl-1 = <&sdi1_sleep_mode>; @@ -144,7 +152,9 @@ arm,primecell-periphid = <0x10480180>; max-frequency = <100000000>; bus-width = <8>; - mmc-cap-mmc-highspeed; + cap-mmc-highspeed; + non-removable; + vmmc-supply = <&db8500_vsmps2_reg>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&sdi2_default_mode>; pinctrl-1 = <&sdi2_sleep_mode>; @@ -157,7 +167,8 @@ arm,primecell-periphid = <0x10480180>; max-frequency = <100000000>; bus-width = <8>; - mmc-cap-mmc-highspeed; + cap-mmc-highspeed; + non-removable; vmmc-supply = <&ab8500_ldo_aux2_reg>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&sdi4_default_mode>; diff --git a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi index 5acc0449676a..d316c955bd5f 100644 --- a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi +++ b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi @@ -840,8 +840,8 @@ interrupts = <22>; max-frequency = <48000000>; bus-width = <4>; - mmc-cap-mmc-highspeed; - mmc-cap-sd-highspeed; + cap-mmc-highspeed; + cap-sd-highspeed; cd-gpios = <&gpio3 15 0x1>; cd-inverted; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/ste-snowball.dts b/arch/arm/boot/dts/ste-snowball.dts index a2f632d0be2a..474ef83229cd 100644 --- a/arch/arm/boot/dts/ste-snowball.dts +++ b/arch/arm/boot/dts/ste-snowball.dts @@ -156,7 +156,7 @@ arm,primecell-periphid = <0x10480180>; max-frequency = <100000000>; bus-width = <4>; - mmc-cap-mmc-highspeed; + cap-mmc-highspeed; vmmc-supply = <&ab8500_ldo_aux3_reg>; vqmmc-supply = <&vmmci>; pinctrl-names = "default", "sleep"; @@ -195,7 +195,7 @@ arm,primecell-periphid = <0x10480180>; max-frequency = <100000000>; bus-width = <8>; - mmc-cap-mmc-highspeed; + cap-mmc-highspeed; vmmc-supply = <&ab8500_ldo_aux2_reg>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&sdi4_default_mode>; diff --git a/arch/arm/boot/dts/ste-u300.dts b/arch/arm/boot/dts/ste-u300.dts index 6fe688e9e4da..82a661677e97 100644 --- a/arch/arm/boot/dts/ste-u300.dts +++ b/arch/arm/boot/dts/ste-u300.dts @@ -442,8 +442,8 @@ clock-names = "apb_pclk", "mclk"; max-frequency = <24000000>; bus-width = <4>; // SD-card slot - mmc-cap-mmc-highspeed; - mmc-cap-sd-highspeed; + cap-mmc-highspeed; + cap-sd-highspeed; cd-gpios = <&gpio 12 0x4>; cd-inverted; vmmc-supply = <&ab3100_ldo_g_reg>; diff --git a/arch/arm/boot/dts/stih407-b2120.dts b/arch/arm/boot/dts/stih407-b2120.dts new file mode 100644 index 000000000000..fe69f92e5f82 --- /dev/null +++ b/arch/arm/boot/dts/stih407-b2120.dts @@ -0,0 +1,78 @@ +/* + * Copyright (C) 2014 STMicroelectronics (R&D) Limited. + * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; +#include "stih407.dtsi" +/ { + model = "STiH407 B2120"; + compatible = "st,stih407-b2120", "st,stih407"; + + chosen { + bootargs = "console=ttyAS0,115200"; + linux,stdout-path = &sbc_serial0; + }; + + memory { + device_type = "memory"; + reg = <0x40000000 0x80000000>; + }; + + aliases { + ttyAS0 = &sbc_serial0; + }; + + soc { + sbc_serial0: serial@9530000 { + status = "okay"; + }; + + leds { + compatible = "gpio-leds"; + red { + #gpio-cells = <2>; + label = "Front Panel LED"; + gpios = <&pio4 1 0>; + linux,default-trigger = "heartbeat"; + }; + green { + #gpio-cells = <2>; + gpios = <&pio1 3 0>; + default-state = "off"; + }; + }; + + i2c@9842000 { + status = "okay"; + }; + + i2c@9843000 { + status = "okay"; + }; + + i2c@9844000 { + status = "okay"; + }; + + i2c@9845000 { + status = "okay"; + }; + + i2c@9540000 { + status = "okay"; + }; + + /* SSC11 to HDMI */ + i2c@9541000 { + status = "okay"; + /* HDMI V1.3a supports Standard mode only */ + clock-frequency = <100000>; + st,i2c-min-scl-pulse-width-us = <0>; + st,i2c-min-sda-pulse-width-us = <5>; + }; + }; +}; diff --git a/arch/arm/boot/dts/stih407-clock.dtsi b/arch/arm/boot/dts/stih407-clock.dtsi new file mode 100644 index 000000000000..800f46f009f3 --- /dev/null +++ b/arch/arm/boot/dts/stih407-clock.dtsi @@ -0,0 +1,39 @@ +/* + * Copyright (C) 2014 STMicroelectronics R&D Limited + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/ { + clocks { + /* + * Fixed 30MHz oscillator inputs to SoC + */ + clk_sysin: clk-sysin { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <30000000>; + }; + + /* + * ARM Peripheral clock for timers + */ + arm_periph_clk: arm-periph-clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <600000000>; + }; + + /* + * Bootloader initialized system infrastructure clock for + * serial devices. + */ + clk_ext2f_a9: clockgen-c0@13 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <200000000>; + clock-output-names = "clk-s-icn-reg-0"; + }; + }; +}; diff --git a/arch/arm/boot/dts/stih407-pinctrl.dtsi b/arch/arm/boot/dts/stih407-pinctrl.dtsi new file mode 100644 index 000000000000..402844cb3152 --- /dev/null +++ b/arch/arm/boot/dts/stih407-pinctrl.dtsi @@ -0,0 +1,615 @@ +/* + * Copyright (C) 2014 STMicroelectronics Limited. + * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * publishhed by the Free Software Foundation. + */ +#include "st-pincfg.h" +#include <dt-bindings/interrupt-controller/arm-gic.h> +/ { + + aliases { + /* 0-5: PIO_SBC */ + gpio0 = &pio0; + gpio1 = &pio1; + gpio2 = &pio2; + gpio3 = &pio3; + gpio4 = &pio4; + gpio5 = &pio5; + /* 10-19: PIO_FRONT0 */ + gpio6 = &pio10; + gpio7 = &pio11; + gpio8 = &pio12; + gpio9 = &pio13; + gpio10 = &pio14; + gpio11 = &pio15; + gpio12 = &pio16; + gpio13 = &pio17; + gpio14 = &pio18; + gpio15 = &pio19; + /* 20: PIO_FRONT1 */ + gpio16 = &pio20; + /* 30-35: PIO_REAR */ + gpio17 = &pio30; + gpio18 = &pio31; + gpio19 = &pio32; + gpio20 = &pio33; + gpio21 = &pio34; + gpio22 = &pio35; + /* 40-42: PIO_FLASH */ + gpio23 = &pio40; + gpio24 = &pio41; + gpio25 = &pio42; + }; + + soc { + pin-controller-sbc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,stih407-sbc-pinctrl"; + st,syscfg = <&syscfg_sbc>; + reg = <0x0961f080 0x4>; + reg-names = "irqmux"; + interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>; + interrupts-names = "irqmux"; + ranges = <0 0x09610000 0x6000>; + + pio0: gpio@09610000 { + gpio-controller; + #gpio-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x0 0x100>; + st,bank-name = "PIO0"; + }; + pio1: gpio@09611000 { + gpio-controller; + #gpio-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x1000 0x100>; + st,bank-name = "PIO1"; + }; + pio2: gpio@09612000 { + gpio-controller; + #gpio-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x2000 0x100>; + st,bank-name = "PIO2"; + }; + pio3: gpio@09613000 { + gpio-controller; + #gpio-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x3000 0x100>; + st,bank-name = "PIO3"; + }; + pio4: gpio@09614000 { + gpio-controller; + #gpio-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x4000 0x100>; + st,bank-name = "PIO4"; + }; + + pio5: gpio@09615000 { + gpio-controller; + #gpio-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x5000 0x100>; + st,bank-name = "PIO5"; + }; + + rc { + pinctrl_ir: ir0 { + st,pins { + ir = <&pio4 0 ALT2 IN>; + }; + }; + }; + + /* SBC_ASC0 - UART10 */ + sbc_serial0 { + pinctrl_sbc_serial0: sbc_serial0-0 { + st,pins { + tx = <&pio3 4 ALT1 OUT>; + rx = <&pio3 5 ALT1 IN>; + }; + }; + }; + /* SBC_ASC1 - UART11 */ + sbc_serial1 { + pinctrl_sbc_serial1: sbc_serial1-0 { + st,pins { + tx = <&pio2 6 ALT3 OUT>; + rx = <&pio2 7 ALT3 IN>; + }; + }; + }; + + i2c10 { + pinctrl_i2c10_default: i2c10-default { + st,pins { + sda = <&pio4 6 ALT1 BIDIR>; + scl = <&pio4 5 ALT1 BIDIR>; + }; + }; + }; + + i2c11 { + pinctrl_i2c11_default: i2c11-default { + st,pins { + sda = <&pio5 1 ALT1 BIDIR>; + scl = <&pio5 0 ALT1 BIDIR>; + }; + }; + }; + + keyscan { + pinctrl_keyscan: keyscan { + st,pins { + keyin0 = <&pio4 0 ALT6 IN>; + keyin1 = <&pio4 5 ALT4 IN>; + keyin2 = <&pio0 4 ALT2 IN>; + keyin3 = <&pio2 6 ALT2 IN>; + + keyout0 = <&pio4 6 ALT4 OUT>; + keyout1 = <&pio1 7 ALT2 OUT>; + keyout2 = <&pio0 6 ALT2 OUT>; + keyout3 = <&pio2 7 ALT2 OUT>; + }; + }; + }; + + gmac1 { + /* + * Almost all the boards based on STiH407 SoC have an embedded + * switch where the mdio/mdc have been used for managing the SMI + * iface via I2C. For this reason these lines can be allocated + * by using dedicated configuration (in case of there will be a + * standard PHY transceiver on-board). + */ + pinctrl_rgmii1: rgmii1-0 { + st,pins { + + txd0 = <&pio0 0 ALT1 OUT DE_IO 0 CLK_A>; + txd1 = <&pio0 1 ALT1 OUT DE_IO 0 CLK_A>; + txd2 = <&pio0 2 ALT1 OUT DE_IO 0 CLK_A>; + txd3 = <&pio0 3 ALT1 OUT DE_IO 0 CLK_A>; + txen = <&pio0 5 ALT1 OUT DE_IO 0 CLK_A>; + txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>; + rxd0 = <&pio1 4 ALT1 IN DE_IO 0 CLK_A>; + rxd1 = <&pio1 5 ALT1 IN DE_IO 0 CLK_A>; + rxd2 = <&pio1 6 ALT1 IN DE_IO 0 CLK_A>; + rxd3 = <&pio1 7 ALT1 IN DE_IO 0 CLK_A>; + rxdv = <&pio2 0 ALT1 IN DE_IO 0 CLK_A>; + rxclk = <&pio2 2 ALT1 IN NICLK 500 CLK_A>; + clk125 = <&pio3 7 ALT4 IN NICLK 0 CLK_A>; + phyclk = <&pio2 3 ALT4 OUT NICLK 1750 CLK_B>; + }; + }; + + pinctrl_rgmii1_mdio: rgmii1-mdio { + st,pins { + mdio = <&pio1 0 ALT1 OUT BYPASS 0>; + mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>; + mdint = <&pio1 3 ALT1 IN BYPASS 0>; + }; + }; + + pinctrl_mii1: mii1 { + st,pins { + txd0 = <&pio0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>; + txd1 = <&pio0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>; + txd2 = <&pio0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>; + txd3 = <&pio0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>; + txer = <&pio0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>; + txen = <&pio0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>; + txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>; + col = <&pio0 7 ALT1 IN BYPASS 1000>; + + mdio = <&pio1 0 ALT1 OUT BYPASS 1500>; + mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>; + crs = <&pio1 2 ALT1 IN BYPASS 1000>; + mdint = <&pio1 3 ALT1 IN BYPASS 0>; + rxd0 = <&pio1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; + rxd1 = <&pio1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>; + rxd2 = <&pio1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>; + rxd3 = <&pio1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>; + + rxdv = <&pio2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; + rx_er = <&pio2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; + rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>; + phyclk = <&pio2 3 ALT1 OUT NICLK 0 CLK_A>; + }; + }; + }; + + pwm1 { + pinctrl_pwm1_chan0_default: pwm1-0-default { + st,pins { + pwm-out = <&pio3 0 ALT1 OUT>; + }; + }; + pinctrl_pwm1_chan1_default: pwm1-1-default { + st,pins { + pwm-out = <&pio4 4 ALT1 OUT>; + }; + }; + pinctrl_pwm1_chan2_default: pwm1-2-default { + st,pins { + pwm-out = <&pio4 6 ALT3 OUT>; + }; + }; + pinctrl_pwm1_chan3_default: pwm1-3-default { + st,pins { + pwm-out = <&pio4 7 ALT3 OUT>; + }; + }; + }; + }; + + pin-controller-front0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,stih407-front-pinctrl"; + st,syscfg = <&syscfg_front>; + reg = <0x0920f080 0x4>; + reg-names = "irqmux"; + interrupts = <GIC_SPI 189 IRQ_TYPE_NONE>; + interrupts-names = "irqmux"; + ranges = <0 0x09200000 0x10000>; + + pio10: pio@09200000 { + gpio-controller; + #gpio-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x0 0x100>; + st,bank-name = "PIO10"; + }; + pio11: pio@09201000 { + gpio-controller; + #gpio-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x1000 0x100>; + st,bank-name = "PIO11"; + }; + pio12: pio@09202000 { + gpio-controller; + #gpio-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x2000 0x100>; + st,bank-name = "PIO12"; + }; + pio13: pio@09203000 { + gpio-controller; + #gpio-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x3000 0x100>; + st,bank-name = "PIO13"; + }; + pio14: pio@09204000 { + gpio-controller; + #gpio-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x4000 0x100>; + st,bank-name = "PIO14"; + }; + pio15: pio@09205000 { + gpio-controller; + #gpio-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x5000 0x100>; + st,bank-name = "PIO15"; + }; + pio16: pio@09206000 { + gpio-controller; + #gpio-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x6000 0x100>; + st,bank-name = "PIO16"; + }; + pio17: pio@09207000 { + gpio-controller; + #gpio-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x7000 0x100>; + st,bank-name = "PIO17"; + }; + pio18: pio@09208000 { + gpio-controller; + #gpio-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x8000 0x100>; + st,bank-name = "PIO18"; + }; + pio19: pio@09209000 { + gpio-controller; + #gpio-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x9000 0x100>; + st,bank-name = "PIO19"; + }; + + /* Comms */ + serial0 { + pinctrl_serial0: serial0-0 { + st,pins { + tx = <&pio17 0 ALT1 OUT>; + rx = <&pio17 1 ALT1 IN>; + }; + }; + }; + + serial1 { + pinctrl_serial1: serial1-0 { + st,pins { + tx = <&pio16 0 ALT1 OUT>; + rx = <&pio16 1 ALT1 IN>; + }; + }; + }; + + serial2 { + pinctrl_serial2: serial2-0 { + st,pins { + tx = <&pio15 0 ALT1 OUT>; + rx = <&pio15 1 ALT1 IN>; + }; + }; + }; + + mmc1 { + pinctrl_sd1: sd1-0 { + st,pins { + sd_clk = <&pio19 3 ALT5 BIDIR NICLK 0 CLK_B>; + sd_cmd = <&pio19 2 ALT5 BIDIR_PU BYPASS 0>; + sd_dat0 = <&pio19 4 ALT5 BIDIR_PU BYPASS 0>; + sd_dat1 = <&pio19 5 ALT5 BIDIR_PU BYPASS 0>; + sd_dat2 = <&pio19 6 ALT5 BIDIR_PU BYPASS 0>; + sd_dat3 = <&pio19 7 ALT5 BIDIR_PU BYPASS 0>; + sd_led = <&pio16 6 ALT6 OUT>; + sd_pwren = <&pio16 7 ALT6 OUT>; + sd_cd = <&pio19 0 ALT6 IN>; + sd_wp = <&pio19 1 ALT6 IN>; + }; + }; + }; + + + i2c0 { + pinctrl_i2c0_default: i2c0-default { + st,pins { + sda = <&pio10 6 ALT2 BIDIR>; + scl = <&pio10 5 ALT2 BIDIR>; + }; + }; + }; + + i2c1 { + pinctrl_i2c1_default: i2c1-default { + st,pins { + sda = <&pio11 1 ALT2 BIDIR>; + scl = <&pio11 0 ALT2 BIDIR>; + }; + }; + }; + + i2c2 { + pinctrl_i2c2_default: i2c2-default { + st,pins { + sda = <&pio15 6 ALT2 BIDIR>; + scl = <&pio15 5 ALT2 BIDIR>; + }; + }; + }; + + i2c3 { + pinctrl_i2c3_default: i2c3-default { + st,pins { + sda = <&pio18 6 ALT1 BIDIR>; + scl = <&pio18 5 ALT1 BIDIR>; + }; + }; + }; + + spi0 { + pinctrl_spi0_default: spi0-default { + st,pins { + mtsr = <&pio12 6 ALT2 BIDIR>; + mrst = <&pio12 7 ALT2 BIDIR>; + scl = <&pio12 5 ALT2 BIDIR>; + }; + }; + }; + }; + + pin-controller-front1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,stih407-front-pinctrl"; + st,syscfg = <&syscfg_front>; + reg = <0x0921f080 0x4>; + reg-names = "irqmux"; + interrupts = <GIC_SPI 190 IRQ_TYPE_NONE>; + interrupts-names = "irqmux"; + ranges = <0 0x09210000 0x10000>; + + pio20: pio@09210000 { + gpio-controller; + #gpio-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x0 0x100>; + st,bank-name = "PIO20"; + }; + }; + + pin-controller-rear { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,stih407-rear-pinctrl"; + st,syscfg = <&syscfg_rear>; + reg = <0x0922f080 0x4>; + reg-names = "irqmux"; + interrupts = <GIC_SPI 191 IRQ_TYPE_NONE>; + interrupts-names = "irqmux"; + ranges = <0 0x09220000 0x6000>; + + pio30: gpio@09220000 { + gpio-controller; + #gpio-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x0 0x100>; + st,bank-name = "PIO30"; + }; + pio31: gpio@09221000 { + gpio-controller; + #gpio-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x1000 0x100>; + st,bank-name = "PIO31"; + }; + pio32: gpio@09222000 { + gpio-controller; + #gpio-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x2000 0x100>; + st,bank-name = "PIO32"; + }; + pio33: gpio@09223000 { + gpio-controller; + #gpio-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x3000 0x100>; + st,bank-name = "PIO33"; + }; + pio34: gpio@09224000 { + gpio-controller; + #gpio-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x4000 0x100>; + st,bank-name = "PIO34"; + }; + pio35: gpio@09225000 { + gpio-controller; + #gpio-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x5000 0x100>; + st,bank-name = "PIO35"; + }; + + i2c4 { + pinctrl_i2c4_default: i2c4-default { + st,pins { + sda = <&pio30 1 ALT1 BIDIR>; + scl = <&pio30 0 ALT1 BIDIR>; + }; + }; + }; + + i2c5 { + pinctrl_i2c5_default: i2c5-default { + st,pins { + sda = <&pio34 4 ALT1 BIDIR>; + scl = <&pio34 3 ALT1 BIDIR>; + }; + }; + }; + + usb3 { + pinctrl_usb3: usb3-2 { + st,pins { + usb-oc-detect = <&pio35 4 ALT1 IN>; + usb-pwr-enable = <&pio35 5 ALT1 OUT>; + usb-vbus-valid = <&pio35 6 ALT1 IN>; + }; + }; + }; + + pwm0 { + pinctrl_pwm0_chan0_default: pwm0-0-default { + st,pins { + pwm-out = <&pio31 1 ALT1 OUT>; + }; + }; + }; + }; + + pin-controller-flash { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,stih407-flash-pinctrl"; + st,syscfg = <&syscfg_flash>; + reg = <0x0923f080 0x4>; + reg-names = "irqmux"; + interrupts = <GIC_SPI 192 IRQ_TYPE_NONE>; + interrupts-names = "irqmux"; + ranges = <0 0x09230000 0x3000>; + + pio40: gpio@09230000 { + gpio-controller; + #gpio-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0 0x100>; + st,bank-name = "PIO40"; + }; + pio41: gpio@09231000 { + gpio-controller; + #gpio-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x1000 0x100>; + st,bank-name = "PIO41"; + }; + pio42: gpio@09232000 { + gpio-controller; + #gpio-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x2000 0x100>; + st,bank-name = "PIO42"; + }; + + mmc0 { + pinctrl_mmc0: mmc0-0 { + st,pins { + emmc_clk = <&pio40 6 ALT1 BIDIR>; + emmc_cmd = <&pio40 7 ALT1 BIDIR_PU>; + emmc_d0 = <&pio41 0 ALT1 BIDIR_PU>; + emmc_d1 = <&pio41 1 ALT1 BIDIR_PU>; + emmc_d2 = <&pio41 2 ALT1 BIDIR_PU>; + emmc_d3 = <&pio41 3 ALT1 BIDIR_PU>; + emmc_d4 = <&pio41 4 ALT1 BIDIR_PU>; + emmc_d5 = <&pio41 5 ALT1 BIDIR_PU>; + emmc_d6 = <&pio41 6 ALT1 BIDIR_PU>; + emmc_d7 = <&pio41 7 ALT1 BIDIR_PU>; + }; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/stih407.dtsi b/arch/arm/boot/dts/stih407.dtsi new file mode 100644 index 000000000000..4f9024f19866 --- /dev/null +++ b/arch/arm/boot/dts/stih407.dtsi @@ -0,0 +1,263 @@ +/* + * Copyright (C) 2014 STMicroelectronics Limited. + * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * publishhed by the Free Software Foundation. + */ +#include "stih407-clock.dtsi" +#include "stih407-pinctrl.dtsi" +/ { + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + }; + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <1>; + }; + }; + + intc: interrupt-controller@08761000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x08761000 0x1000>, <0x08760100 0x100>; + }; + + scu@08760000 { + compatible = "arm,cortex-a9-scu"; + reg = <0x08760000 0x1000>; + }; + + timer@08760200 { + interrupt-parent = <&intc>; + compatible = "arm,cortex-a9-global-timer"; + reg = <0x08760200 0x100>; + interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&arm_periph_clk>; + }; + + l2: cache-controller { + compatible = "arm,pl310-cache"; + reg = <0x08762000 0x1000>; + arm,data-latency = <3 3 3>; + arm,tag-latency = <2 2 2>; + cache-unified; + cache-level = <2>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + ranges; + compatible = "simple-bus"; + + syscfg_sbc: sbc-syscfg@9620000 { + compatible = "st,stih407-sbc-syscfg", "syscon"; + reg = <0x9620000 0x1000>; + }; + + syscfg_front: front-syscfg@9280000 { + compatible = "st,stih407-front-syscfg", "syscon"; + reg = <0x9280000 0x1000>; + }; + + syscfg_rear: rear-syscfg@9290000 { + compatible = "st,stih407-rear-syscfg", "syscon"; + reg = <0x9290000 0x1000>; + }; + + syscfg_flash: flash-syscfg@92a0000 { + compatible = "st,stih407-flash-syscfg", "syscon"; + reg = <0x92a0000 0x1000>; + }; + + syscfg_sbc_reg: fvdp-lite-syscfg@9600000 { + compatible = "st,stih407-sbc-reg-syscfg", "syscon"; + reg = <0x9600000 0x1000>; + }; + + syscfg_core: core-syscfg@92b0000 { + compatible = "st,stih407-core-syscfg", "syscon"; + reg = <0x92b0000 0x1000>; + }; + + syscfg_lpm: lpm-syscfg@94b5100 { + compatible = "st,stih407-lpm-syscfg", "syscon"; + reg = <0x94b5100 0x1000>; + }; + + serial@9830000 { + compatible = "st,asc"; + reg = <0x9830000 0x2c>; + interrupts = <GIC_SPI 122 IRQ_TYPE_NONE>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_serial0>; + clocks = <&clk_ext2f_a9>; + + status = "disabled"; + }; + + serial@9831000 { + compatible = "st,asc"; + reg = <0x9831000 0x2c>; + interrupts = <GIC_SPI 123 IRQ_TYPE_NONE>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_serial1>; + clocks = <&clk_ext2f_a9>; + + status = "disabled"; + }; + + serial@9832000 { + compatible = "st,asc"; + reg = <0x9832000 0x2c>; + interrupts = <GIC_SPI 124 IRQ_TYPE_NONE>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_serial2>; + clocks = <&clk_ext2f_a9>; + + status = "disabled"; + }; + + /* SBC_ASC0 - UART10 */ + sbc_serial0: serial@9530000 { + compatible = "st,asc"; + reg = <0x9530000 0x2c>; + interrupts = <GIC_SPI 138 IRQ_TYPE_NONE>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sbc_serial0>; + clocks = <&clk_sysin>; + + status = "disabled"; + }; + + serial@9531000 { + compatible = "st,asc"; + reg = <0x9531000 0x2c>; + interrupts = <GIC_SPI 139 IRQ_TYPE_NONE>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sbc_serial1>; + clocks = <&clk_sysin>; + + status = "disabled"; + }; + + i2c@9840000 { + compatible = "st,comms-ssc4-i2c"; + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x9840000 0x110>; + clocks = <&clk_ext2f_a9>; + clock-names = "ssc"; + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_default>; + + status = "disabled"; + }; + + i2c@9841000 { + compatible = "st,comms-ssc4-i2c"; + reg = <0x9841000 0x110>; + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_ext2f_a9>; + clock-names = "ssc"; + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_default>; + + status = "disabled"; + }; + + i2c@9842000 { + compatible = "st,comms-ssc4-i2c"; + reg = <0x9842000 0x110>; + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_ext2f_a9>; + clock-names = "ssc"; + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_default>; + + status = "disabled"; + }; + + i2c@9843000 { + compatible = "st,comms-ssc4-i2c"; + reg = <0x9843000 0x110>; + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_ext2f_a9>; + clock-names = "ssc"; + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_default>; + + status = "disabled"; + }; + + i2c@9844000 { + compatible = "st,comms-ssc4-i2c"; + reg = <0x9844000 0x110>; + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_ext2f_a9>; + clock-names = "ssc"; + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4_default>; + + status = "disabled"; + }; + + i2c@9845000 { + compatible = "st,comms-ssc4-i2c"; + reg = <0x9845000 0x110>; + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_ext2f_a9>; + clock-names = "ssc"; + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c5_default>; + + status = "disabled"; + }; + + + /* SSCs on SBC */ + i2c@9540000 { + compatible = "st,comms-ssc4-i2c"; + reg = <0x9540000 0x110>; + interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_sysin>; + clock-names = "ssc"; + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c10_default>; + + status = "disabled"; + }; + + i2c@9541000 { + compatible = "st,comms-ssc4-i2c"; + reg = <0x9541000 0x110>; + interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_sysin>; + clock-names = "ssc"; + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c11_default>; + + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/boot/dts/stih415-b2000.dts b/arch/arm/boot/dts/stih415-b2000.dts index d4af53160435..bdfbd3765db2 100644 --- a/arch/arm/boot/dts/stih415-b2000.dts +++ b/arch/arm/boot/dts/stih415-b2000.dts @@ -11,5 +11,5 @@ #include "stih41x-b2000.dtsi" / { model = "STiH415 B2000 Board"; - compatible = "st,stih415", "st,stih415-b2000"; + compatible = "st,stih415-b2000", "st,stih415"; }; diff --git a/arch/arm/boot/dts/stih415-b2020.dts b/arch/arm/boot/dts/stih415-b2020.dts index 442b019e9a3a..71903a87bd31 100644 --- a/arch/arm/boot/dts/stih415-b2020.dts +++ b/arch/arm/boot/dts/stih415-b2020.dts @@ -11,5 +11,5 @@ #include "stih41x-b2020.dtsi" / { model = "STiH415 B2020 Board"; - compatible = "st,stih415", "st,stih415-b2020"; + compatible = "st,stih415-b2020", "st,stih415"; }; diff --git a/arch/arm/boot/dts/stih415-clock.dtsi b/arch/arm/boot/dts/stih415-clock.dtsi index d047dbc28d61..3ee34514bc4b 100644 --- a/arch/arm/boot/dts/stih415-clock.dtsi +++ b/arch/arm/boot/dts/stih415-clock.dtsi @@ -5,48 +5,529 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ + +#include <dt-bindings/clock/stih415-clks.h> + / { clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + /* * Fixed 30MHz oscillator input to SoC */ - CLK_SYSIN: CLK_SYSIN { + clk_sysin: clk-sysin { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <30000000>; }; /* - * ARM Peripheral clock for timers + * ClockGenAs on SASG1 */ - arm_periph_clk: arm_periph_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <500000000>; + clockgen-a@fee62000 { + reg = <0xfee62000 0xb48>; + + clk_s_a0_pll: clk-s-a0-pll { + #clock-cells = <1>; + compatible = "st,clkgena-plls-c65"; + + clocks = <&clk_sysin>; + + clock-output-names = "clk-s-a0-pll0-hs", + "clk-s-a0-pll0-ls", + "clk-s-a0-pll1"; + }; + + clk_s_a0_osc_prediv: clk-s-a0-osc-prediv { + #clock-cells = <0>; + compatible = "st,clkgena-prediv-c65", + "st,clkgena-prediv"; + + clocks = <&clk_sysin>; + + clock-output-names = "clk-s-a0-osc-prediv"; + }; + + clk_s_a0_hs: clk-s-a0-hs { + #clock-cells = <1>; + compatible = "st,clkgena-divmux-c65-hs", + "st,clkgena-divmux"; + + clocks = <&clk_s_a0_osc_prediv>, + <&clk_s_a0_pll 0>, /* PLL0 HS */ + <&clk_s_a0_pll 2>; /* PLL1 */ + + clock-output-names = "clk-s-fdma-0", + "clk-s-fdma-1", + ""; /* clk-s-jit-sense */ + /* Fourth output unused */ + }; + + clk_s_a0_ls: clk-s-a0-ls { + #clock-cells = <1>; + compatible = "st,clkgena-divmux-c65-ls", + "st,clkgena-divmux"; + + clocks = <&clk_s_a0_osc_prediv>, + <&clk_s_a0_pll 1>, /* PLL0 LS */ + <&clk_s_a0_pll 2>; /* PLL1 */ + + clock-output-names = "clk-s-icn-reg-0", + "clk-s-icn-if-0", + "clk-s-icn-reg-lp-0", + "clk-s-emiss", + "clk-s-eth1-phy", + "clk-s-mii-ref-out"; + /* Remaining outputs unused */ + }; + }; + + clockgen-a@fee81000 { + reg = <0xfee81000 0xb48>; + + clk_s_a1_pll: clk-s-a1-pll { + #clock-cells = <1>; + compatible = "st,clkgena-plls-c65"; + + clocks = <&clk_sysin>; + + clock-output-names = "clk-s-a1-pll0-hs", + "clk-s-a1-pll0-ls", + "clk-s-a1-pll1"; + }; + + clk_s_a1_osc_prediv: clk-s-a1-osc-prediv { + #clock-cells = <0>; + compatible = "st,clkgena-prediv-c65", + "st,clkgena-prediv"; + + clocks = <&clk_sysin>; + + clock-output-names = "clk-s-a1-osc-prediv"; + }; + + clk_s_a1_hs: clk-s-a1-hs { + #clock-cells = <1>; + compatible = "st,clkgena-divmux-c65-hs", + "st,clkgena-divmux"; + + clocks = <&clk_s_a1_osc_prediv>, + <&clk_s_a1_pll 0>, /* PLL0 HS */ + <&clk_s_a1_pll 2>; /* PLL1 */ + + clock-output-names = "", /* Reserved */ + "", /* Reserved */ + "clk-s-stac-phy", + "clk-s-vtac-tx-phy"; + }; + + clk_s_a1_ls: clk-s-a1-ls { + #clock-cells = <1>; + compatible = "st,clkgena-divmux-c65-ls", + "st,clkgena-divmux"; + + clocks = <&clk_s_a1_osc_prediv>, + <&clk_s_a1_pll 1>, /* PLL0 LS */ + <&clk_s_a1_pll 2>; /* PLL1 */ + + clock-output-names = "clk-s-icn-if-2", + "clk-s-card-mmc", + "clk-s-icn-if-1", + "clk-s-gmac0-phy", + "clk-s-nand-ctrl", + "", /* Reserved */ + "clk-s-mii0-ref-out", + ""; /* clk-s-stac-sys */ + /* Remaining outputs unused */ + }; }; /* - * Bootloader initialized system infrastructure clock for - * serial devices. + * ClockGenAs on MPE41 */ - CLKS_ICN_REG_0: CLKS_ICN_REG_0 { + clockgen-a@fde12000 { + reg = <0xfde12000 0xb50>; + + clk_m_a0_pll0: clk-m-a0-pll0 { + #clock-cells = <1>; + compatible = "st,plls-c32-a1x-0", "st,clkgen-plls-c32"; + + clocks = <&clk_sysin>; + + clock-output-names = "clk-m-a0-pll0-phi0", + "clk-m-a0-pll0-phi1", + "clk-m-a0-pll0-phi2", + "clk-m-a0-pll0-phi3"; + }; + + clk_m_a0_pll1: clk-m-a0-pll1 { + #clock-cells = <1>; + compatible = "st,plls-c32-a1x-1", "st,clkgen-plls-c32"; + + clocks = <&clk_sysin>; + + clock-output-names = "clk-m-a0-pll1-phi0", + "clk-m-a0-pll1-phi1", + "clk-m-a0-pll1-phi2", + "clk-m-a0-pll1-phi3"; + }; + + clk_m_a0_osc_prediv: clk-m-a0-osc-prediv { + #clock-cells = <0>; + compatible = "st,clkgena-prediv-c32", + "st,clkgena-prediv"; + + clocks = <&clk_sysin>; + + clock-output-names = "clk-m-a0-osc-prediv"; + }; + + clk_m_a0_div0: clk-m-a0-div0 { + #clock-cells = <1>; + compatible = "st,clkgena-divmux-c32-odf0", + "st,clkgena-divmux"; + + clocks = <&clk_m_a0_osc_prediv>, + <&clk_m_a0_pll0 0>, /* PLL0 PHI0 */ + <&clk_m_a0_pll1 0>; /* PLL1 PHI0 */ + + clock-output-names = "clk-m-apb-pm", /* Unused */ + "", /* Unused */ + "", /* Unused */ + "", /* Unused */ + "clk-m-pp-dmu-0", + "clk-m-pp-dmu-1", + "clk-m-icm-disp", + ""; /* Unused */ + }; + + clk_m_a0_div1: clk-m-a0-div1 { + #clock-cells = <1>; + compatible = "st,clkgena-divmux-c32-odf1", + "st,clkgena-divmux"; + + clocks = <&clk_m_a0_osc_prediv>, + <&clk_m_a0_pll0 1>, /* PLL0 PHI1 */ + <&clk_m_a0_pll1 1>; /* PLL1 PHI1 */ + + clock-output-names = "", /* Unused */ + "", /* Unused */ + "clk-m-a9-ext2f", + "clk-m-st40rt", + "clk-m-st231-dmu-0", + "clk-m-st231-dmu-1", + "clk-m-st231-aud", + "clk-m-st231-gp-0"; + }; + + clk_m_a0_div2: clk-m-a0-div2 { + #clock-cells = <1>; + compatible = "st,clkgena-divmux-c32-odf2", + "st,clkgena-divmux"; + + clocks = <&clk_m_a0_osc_prediv>, + <&clk_m_a0_pll0 2>, /* PLL0 PHI2 */ + <&clk_m_a0_pll1 2>; /* PLL1 PHI2 */ + + clock-output-names = "clk-m-st231-gp-1", + "clk-m-icn-cpu", + "clk-m-icn-stac", + "clk-m-icn-dmu-0", + "clk-m-icn-dmu-1", + "", /* Unused */ + "", /* Unused */ + ""; /* Unused */ + }; + + clk_m_a0_div3: clk-m-a0-div3 { + #clock-cells = <1>; + compatible = "st,clkgena-divmux-c32-odf3", + "st,clkgena-divmux"; + + clocks = <&clk_m_a0_osc_prediv>, + <&clk_m_a0_pll0 3>, /* PLL0 PHI3 */ + <&clk_m_a0_pll1 3>; /* PLL1 PHI3 */ + + clock-output-names = "", /* Unused */ + "", /* Unused */ + "", /* Unused */ + "", /* Unused */ + "", /* Unused */ + "", /* Unused */ + "clk-m-icn-eram", + "clk-m-a9-trace"; + }; + }; + + clockgen-a@fd6db000 { + reg = <0xfd6db000 0xb50>; + + clk_m_a1_pll0: clk-m-a1-pll0 { + #clock-cells = <1>; + compatible = "st,plls-c32-a1x-0", "st,clkgen-plls-c32"; + + clocks = <&clk_sysin>; + + clock-output-names = "clk-m-a1-pll0-phi0", + "clk-m-a1-pll0-phi1", + "clk-m-a1-pll0-phi2", + "clk-m-a1-pll0-phi3"; + }; + + clk_m_a1_pll1: clk-m-a1-pll1 { + #clock-cells = <1>; + compatible = "st,plls-c32-a1x-1", "st,clkgen-plls-c32"; + + clocks = <&clk_sysin>; + + clock-output-names = "clk-m-a1-pll1-phi0", + "clk-m-a1-pll1-phi1", + "clk-m-a1-pll1-phi2", + "clk-m-a1-pll1-phi3"; + }; + + clk_m_a1_osc_prediv: clk-m-a1-osc-prediv { + #clock-cells = <0>; + compatible = "st,clkgena-prediv-c32", + "st,clkgena-prediv"; + + clocks = <&clk_sysin>; + + clock-output-names = "clk-m-a1-osc-prediv"; + }; + + clk_m_a1_div0: clk-m-a1-div0 { + #clock-cells = <1>; + compatible = "st,clkgena-divmux-c32-odf0", + "st,clkgena-divmux"; + + clocks = <&clk_m_a1_osc_prediv>, + <&clk_m_a1_pll0 0>, /* PLL0 PHI0 */ + <&clk_m_a1_pll1 0>; /* PLL1 PHI0 */ + + clock-output-names = "clk-m-fdma-12", + "clk-m-fdma-10", + "clk-m-fdma-11", + "clk-m-hva-lmi", + "clk-m-proc-sc", + "clk-m-tp", + "clk-m-icn-gpu", + "clk-m-icn-vdp-0"; + }; + + clk_m_a1_div1: clk-m-a1-div1 { + #clock-cells = <1>; + compatible = "st,clkgena-divmux-c32-odf1", + "st,clkgena-divmux"; + + clocks = <&clk_m_a1_osc_prediv>, + <&clk_m_a1_pll0 1>, /* PLL0 PHI1 */ + <&clk_m_a1_pll1 1>; /* PLL1 PHI1 */ + + clock-output-names = "clk-m-icn-vdp-1", + "clk-m-icn-vdp-2", + "clk-m-icn-vdp-3", + "clk-m-prv-t1-bus", + "clk-m-icn-vdp-4", + "clk-m-icn-reg-10", + "", /* Unused */ + ""; /* clk-m-icn-st231 */ + }; + + clk_m_a1_div2: clk-m-a1-div2 { + #clock-cells = <1>; + compatible = "st,clkgena-divmux-c32-odf2", + "st,clkgena-divmux"; + + clocks = <&clk_m_a1_osc_prediv>, + <&clk_m_a1_pll0 2>, /* PLL0 PHI2 */ + <&clk_m_a1_pll1 2>; /* PLL1 PHI2 */ + + clock-output-names = "clk-m-fvdp-proc-alt", + "", /* Unused */ + "", /* Unused */ + "", /* Unused */ + "", /* Unused */ + "", /* Unused */ + "", /* Unused */ + ""; /* Unused */ + }; + + clk_m_a1_div3: clk-m-a1-div3 { + #clock-cells = <1>; + compatible = "st,clkgena-divmux-c32-odf3", + "st,clkgena-divmux"; + + clocks = <&clk_m_a1_osc_prediv>, + <&clk_m_a1_pll0 3>, /* PLL0 PHI3 */ + <&clk_m_a1_pll1 3>; /* PLL1 PHI3 */ + + clock-output-names = "", /* Unused */ + "", /* Unused */ + "", /* Unused */ + "", /* Unused */ + "", /* Unused */ + "", /* Unused */ + "", /* Unused */ + ""; /* Unused */ + }; + }; + + clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2 { #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <100000000>; + compatible = "fixed-factor-clock"; + clocks = <&clk_m_a0_div1 2>; + clock-div = <2>; + clock-mult = <1>; }; - CLKS_GMAC0_PHY: clockgenA1@7 { + clockgen-a@fd345000 { + reg = <0xfd345000 0xb50>; + + clk_m_a2_pll0: clk-m-a2-pll0 { + #clock-cells = <1>; + compatible = "st,plls-c32-a1x-0", "st,clkgen-plls-c32"; + + clocks = <&clk_sysin>; + + clock-output-names = "clk-m-a2-pll0-phi0", + "clk-m-a2-pll0-phi1", + "clk-m-a2-pll0-phi2", + "clk-m-a2-pll0-phi3"; + }; + + clk_m_a2_pll1: clk-m-a2-pll1 { + #clock-cells = <1>; + compatible = "st,plls-c32-a1x-1", "st,clkgen-plls-c32"; + + clocks = <&clk_sysin>; + + clock-output-names = "clk-m-a2-pll1-phi0", + "clk-m-a2-pll1-phi1", + "clk-m-a2-pll1-phi2", + "clk-m-a2-pll1-phi3"; + }; + + clk_m_a2_osc_prediv: clk-m-a2-osc-prediv { + #clock-cells = <0>; + compatible = "st,clkgena-prediv-c32", + "st,clkgena-prediv"; + + clocks = <&clk_sysin>; + + clock-output-names = "clk-m-a2-osc-prediv"; + }; + + clk_m_a2_div0: clk-m-a2-div0 { + #clock-cells = <1>; + compatible = "st,clkgena-divmux-c32-odf0", + "st,clkgena-divmux"; + + clocks = <&clk_m_a2_osc_prediv>, + <&clk_m_a2_pll0 0>, /* PLL0 PHI0 */ + <&clk_m_a2_pll1 0>; /* PLL1 PHI0 */ + + clock-output-names = "clk-m-vtac-main-phy", + "clk-m-vtac-aux-phy", + "clk-m-stac-phy", + "clk-m-stac-sys", + "", /* clk-m-mpestac-pg */ + "", /* clk-m-mpestac-wc */ + "", /* clk-m-mpevtacaux-pg*/ + ""; /* clk-m-mpevtacmain-pg*/ + }; + + clk_m_a2_div1: clk-m-a2-div1 { + #clock-cells = <1>; + compatible = "st,clkgena-divmux-c32-odf1", + "st,clkgena-divmux"; + + clocks = <&clk_m_a2_osc_prediv>, + <&clk_m_a2_pll0 1>, /* PLL0 PHI1 */ + <&clk_m_a2_pll1 1>; /* PLL1 PHI1 */ + + clock-output-names = "", /* clk-m-mpevtacrx0-wc */ + "", /* clk-m-mpevtacrx1-wc */ + "clk-m-compo-main", + "clk-m-compo-aux", + "clk-m-bdisp-0", + "clk-m-bdisp-1", + "clk-m-icn-bdisp-0", + "clk-m-icn-bdisp-1"; + }; + + clk_m_a2_div2: clk-m-a2-div2 { + #clock-cells = <1>; + compatible = "st,clkgena-divmux-c32-odf2", + "st,clkgena-divmux"; + + clocks = <&clk_m_a2_osc_prediv>, + <&clk_m_a2_pll0 2>, /* PLL0 PHI2 */ + <&clk_m_a2_pll1 2>; /* PLL1 PHI2 */ + + clock-output-names = "", /* clk-m-icn-hqvdp0 */ + "", /* clk-m-icn-hqvdp1 */ + "clk-m-icn-compo", + "", /* clk-m-icn-vdpaux */ + "clk-m-icn-ts", + "clk-m-icn-reg-lp-10", + "clk-m-dcephy-impctrl", + ""; /* Unused */ + }; + + clk_m_a2_div3: clk-m-a2-div3 { + #clock-cells = <1>; + compatible = "st,clkgena-divmux-c32-odf3", + "st,clkgena-divmux"; + + clocks = <&clk_m_a2_osc_prediv>, + <&clk_m_a2_pll0 3>, /* PLL0 PHI3 */ + <&clk_m_a2_pll1 3>; /* PLL1 PHI3 */ + + clock-output-names = ""; /* Unused */ + /* Remaining outputs unused */ + }; + }; + + /* + * A9 PLL + */ + clockgen-a9@fdde00d8 { + reg = <0xfdde00d8 0x70>; + + clockgen_a9_pll: clockgen-a9-pll { + #clock-cells = <1>; + compatible = "st,stih415-plls-c32-a9", "st,clkgen-plls-c32"; + + clocks = <&clk_sysin>; + clock-output-names = "clockgen-a9-pll-odf"; + }; + }; + + /* + * ARM CPU related clocks + */ + clk_m_a9: clk-m-a9@fdde00d8 { #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <25000000>; - clock-output-names = "CLKS_GMAC0_PHY"; + compatible = "st,stih415-clkgen-a9-mux", "st,clkgen-mux"; + reg = <0xfdde00d8 0x4>; + clocks = <&clockgen_a9_pll 0>, + <&clockgen_a9_pll 0>, + <&clk_m_a0_div1 2>, + <&clk_m_a9_ext2f_div2>; }; - CLKS_ETH1_PHY: clockgenA0@7 { + /* + * ARM Peripheral clock for timers + */ + arm_periph_clk: clk-m-a9-periphs { #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <25000000>; - clock-output-names = "CLKS_ETH1_PHY"; + compatible = "fixed-factor-clock"; + clocks = <&clk_m_a9>; + clock-div = <2>; + clock-mult = <1>; }; }; }; diff --git a/arch/arm/boot/dts/stih415-pinctrl.dtsi b/arch/arm/boot/dts/stih415-pinctrl.dtsi index 81df870e5ee6..8509a037ae21 100644 --- a/arch/arm/boot/dts/stih415-pinctrl.dtsi +++ b/arch/arm/boot/dts/stih415-pinctrl.dtsi @@ -102,6 +102,22 @@ }; }; + keyscan { + pinctrl_keyscan: keyscan { + st,pins { + keyin0 = <&PIO0 2 ALT2 IN>; + keyin1 = <&PIO0 3 ALT2 IN>; + keyin2 = <&PIO0 4 ALT2 IN>; + keyin3 = <&PIO2 6 ALT2 IN>; + + keyout0 = <&PIO1 6 ALT2 OUT>; + keyout1 = <&PIO1 7 ALT2 OUT>; + keyout2 = <&PIO0 6 ALT2 OUT>; + keyout3 = <&PIO2 7 ALT2 OUT>; + }; + }; + }; + sbc_i2c0 { pinctrl_sbc_i2c0_default: sbc_i2c0-default { st,pins { diff --git a/arch/arm/boot/dts/stih415.dtsi b/arch/arm/boot/dts/stih415.dtsi index d89064c20c8a..d6f254f302fe 100644 --- a/arch/arm/boot/dts/stih415.dtsi +++ b/arch/arm/boot/dts/stih415.dtsi @@ -82,7 +82,7 @@ interrupts = <0 197 0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_serial2>; - clocks = <&CLKS_ICN_REG_0>; + clocks = <&clk_s_a0_ls CLK_ICN_REG>; }; /* SBC comms block ASCs in SASG1 */ @@ -91,7 +91,7 @@ status = "disabled"; reg = <0xfe531000 0x2c>; interrupts = <0 210 0>; - clocks = <&CLK_SYSIN>; + clocks = <&clk_sysin>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sbc_serial1>; }; @@ -100,7 +100,7 @@ compatible = "st,comms-ssc4-i2c"; reg = <0xfed40000 0x110>; interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&CLKS_ICN_REG_0>; + clocks = <&clk_s_a0_ls CLK_ICN_REG>; clock-names = "ssc"; clock-frequency = <400000>; pinctrl-names = "default"; @@ -113,7 +113,7 @@ compatible = "st,comms-ssc4-i2c"; reg = <0xfed41000 0x110>; interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&CLKS_ICN_REG_0>; + clocks = <&clk_s_a0_ls CLK_ICN_REG>; clock-names = "ssc"; clock-frequency = <400000>; pinctrl-names = "default"; @@ -126,7 +126,7 @@ compatible = "st,comms-ssc4-i2c"; reg = <0xfe540000 0x110>; interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&CLK_SYSIN>; + clocks = <&clk_sysin>; clock-names = "ssc"; clock-frequency = <400000>; pinctrl-names = "default"; @@ -139,7 +139,7 @@ compatible = "st,comms-ssc4-i2c"; reg = <0xfe541000 0x110>; interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&CLK_SYSIN>; + clocks = <&clk_sysin>; clock-names = "ssc"; clock-frequency = <400000>; pinctrl-names = "default"; @@ -170,7 +170,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_mii0>; clock-names = "stmmaceth"; - clocks = <&CLKS_GMAC0_PHY>; + clocks = <&clk_s_a1_ls CLK_GMAC0_PHY>; }; ethernet1: dwmac@fef08000 { @@ -193,18 +193,30 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_mii1>; clock-names = "stmmaceth"; - clocks = <&CLKS_ETH1_PHY>; + clocks = <&clk_s_a0_ls CLK_ETH1_PHY>; }; rc: rc@fe518000 { compatible = "st,comms-irb"; reg = <0xfe518000 0x234>; interrupts = <0 203 0>; - clocks = <&CLK_SYSIN>; + clocks = <&clk_sysin>; rx-mode = "infrared"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ir>; resets = <&softreset STIH415_IRB_SOFTRESET>; }; + + keyscan: keyscan@fe4b0000 { + compatible = "st,sti-keyscan"; + status = "disabled"; + reg = <0xfe4b0000 0x2000>; + interrupts = <GIC_SPI 212 IRQ_TYPE_NONE>; + clocks = <&clk_sysin>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_keyscan>; + resets = <&powerdown STIH415_KEYSCAN_POWERDOWN>, + <&softreset STIH415_KEYSCAN_SOFTRESET>; + }; }; }; diff --git a/arch/arm/boot/dts/stih416-b2000.dts b/arch/arm/boot/dts/stih416-b2000.dts index a5eb6eee10bf..488e80a5d69d 100644 --- a/arch/arm/boot/dts/stih416-b2000.dts +++ b/arch/arm/boot/dts/stih416-b2000.dts @@ -9,8 +9,7 @@ /dts-v1/; #include "stih416.dtsi" #include "stih41x-b2000.dtsi" - / { - compatible = "st,stih416", "st,stih416-b2000"; model = "STiH416 B2000"; + compatible = "st,stih416-b2000", "st,stih416"; }; diff --git a/arch/arm/boot/dts/stih416-b2020-revE.dts b/arch/arm/boot/dts/stih416-b2020-revE.dts new file mode 100644 index 000000000000..ba0fa2caaf18 --- /dev/null +++ b/arch/arm/boot/dts/stih416-b2020-revE.dts @@ -0,0 +1,35 @@ +/* + * Copyright (C) 2014 STMicroelectronics (R&D) Limited. + * Author: Lee Jones <lee.jones@linaro.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * publishhed by the Free Software Foundation. + */ +/dts-v1/; +#include "stih416.dtsi" +#include "stih41x-b2020.dtsi" +/ { + model = "STiH416 B2020 REV-E"; + compatible = "st,stih416-b2020", "st,stih416"; + + soc { + leds { + compatible = "gpio-leds"; + red { + #gpio-cells = <1>; + label = "Front Panel LED"; + gpios = <&PIO4 1>; + linux,default-trigger = "heartbeat"; + }; + green { + gpios = <&PIO1 3>; + default-state = "off"; + }; + }; + + ethernet1: dwmac@fef08000 { + snps,reset-gpio = <&PIO0 7>; + }; + }; +}; diff --git a/arch/arm/boot/dts/stih416-b2020.dts b/arch/arm/boot/dts/stih416-b2020.dts index 276f28da573a..4e2df66b99ea 100644 --- a/arch/arm/boot/dts/stih416-b2020.dts +++ b/arch/arm/boot/dts/stih416-b2020.dts @@ -11,6 +11,5 @@ #include "stih41x-b2020.dtsi" / { model = "STiH416 B2020"; - compatible = "st,stih416", "st,stih416-b2020"; - + compatible = "st,stih416-b2020", "st,stih416"; }; diff --git a/arch/arm/boot/dts/stih416-clock.dtsi b/arch/arm/boot/dts/stih416-clock.dtsi index a6942c75cbbb..5b4fb838cddb 100644 --- a/arch/arm/boot/dts/stih416-clock.dtsi +++ b/arch/arm/boot/dts/stih416-clock.dtsi @@ -6,50 +6,751 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ + +#include <dt-bindings/clock/stih416-clks.h> + / { clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + /* * Fixed 30MHz oscillator inputs to SoC */ - CLK_SYSIN: CLK_SYSIN { + clk_sysin: clk-sysin { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <30000000>; - clock-output-names = "CLK_SYSIN"; + }; + + /* + * ClockGenAs on SASG2 + */ + clockgen-a@fee62000 { + reg = <0xfee62000 0xb48>; + + clk_s_a0_pll: clk-s-a0-pll { + #clock-cells = <1>; + compatible = "st,clkgena-plls-c65"; + + clocks = <&clk_sysin>; + + clock-output-names = "clk-s-a0-pll0-hs", + "clk-s-a0-pll0-ls", + "clk-s-a0-pll1"; + }; + + clk_s_a0_osc_prediv: clk-s-a0-osc-prediv { + #clock-cells = <0>; + compatible = "st,clkgena-prediv-c65", + "st,clkgena-prediv"; + + clocks = <&clk_sysin>; + + clock-output-names = "clk-s-a0-osc-prediv"; + }; + + clk_s_a0_hs: clk-s-a0-hs { + #clock-cells = <1>; + compatible = "st,clkgena-divmux-c65-hs", + "st,clkgena-divmux"; + + clocks = <&clk_s_a0_osc_prediv>, + <&clk_s_a0_pll 0>, /* PLL0 HS */ + <&clk_s_a0_pll 2>; /* PLL1 */ + + clock-output-names = "clk-s-fdma-0", + "clk-s-fdma-1", + ""; /* clk-s-jit-sense */ + /* Fourth output unused */ + }; + + clk_s_a0_ls: clk-s-a0-ls { + #clock-cells = <1>; + compatible = "st,clkgena-divmux-c65-ls", + "st,clkgena-divmux"; + + clocks = <&clk_s_a0_osc_prediv>, + <&clk_s_a0_pll 1>, /* PLL0 LS */ + <&clk_s_a0_pll 2>; /* PLL1 */ + + clock-output-names = "clk-s-icn-reg-0", + "clk-s-icn-if-0", + "clk-s-icn-reg-lp-0", + "clk-s-emiss", + "clk-s-eth1-phy", + "clk-s-mii-ref-out"; + /* Remaining outputs unused */ + }; + }; + + clockgen-a@fee81000 { + reg = <0xfee81000 0xb48>; + + clk_s_a1_pll: clk-s-a1-pll { + #clock-cells = <1>; + compatible = "st,clkgena-plls-c65"; + + clocks = <&clk_sysin>; + + clock-output-names = "clk-s-a1-pll0-hs", + "clk-s-a1-pll0-ls", + "clk-s-a1-pll1"; + }; + + clk_s_a1_osc_prediv: clk-s-a1-osc-prediv { + #clock-cells = <0>; + compatible = "st,clkgena-prediv-c65", + "st,clkgena-prediv"; + + clocks = <&clk_sysin>; + + clock-output-names = "clk-s-a1-osc-prediv"; + }; + + clk_s_a1_hs: clk-s-a1-hs { + #clock-cells = <1>; + compatible = "st,clkgena-divmux-c65-hs", + "st,clkgena-divmux"; + + clocks = <&clk_s_a1_osc_prediv>, + <&clk_s_a1_pll 0>, /* PLL0 HS */ + <&clk_s_a1_pll 2>; /* PLL1 */ + + clock-output-names = "", /* Reserved */ + "", /* Reserved */ + "clk-s-stac-phy", + "clk-s-vtac-tx-phy"; + }; + + clk_s_a1_ls: clk-s-a1-ls { + #clock-cells = <1>; + compatible = "st,clkgena-divmux-c65-ls", + "st,clkgena-divmux"; + + clocks = <&clk_s_a1_osc_prediv>, + <&clk_s_a1_pll 1>, /* PLL0 LS */ + <&clk_s_a1_pll 2>; /* PLL1 */ + + clock-output-names = "clk-s-icn-if-2", + "clk-s-card-mmc-0", + "clk-s-icn-if-1", + "clk-s-gmac0-phy", + "clk-s-nand-ctrl", + "", /* Reserved */ + "clk-s-mii0-ref-out", + "clk-s-stac-sys", + "clk-s-card-mmc-1"; + /* Remaining outputs unused */ + }; + }; + + /* + * ClockGenAs on MPE42 + */ + clockgen-a@fde12000 { + reg = <0xfde12000 0xb50>; + + clk_m_a0_pll0: clk-m-a0-pll0 { + #clock-cells = <1>; + compatible = "st,plls-c32-a1x-0", "st,clkgen-plls-c32"; + + clocks = <&clk_sysin>; + + clock-output-names = "clk-m-a0-pll0-phi0", + "clk-m-a0-pll0-phi1", + "clk-m-a0-pll0-phi2", + "clk-m-a0-pll0-phi3"; + }; + + clk_m_a0_pll1: clk-m-a0-pll1 { + #clock-cells = <1>; + compatible = "st,plls-c32-a1x-1", "st,clkgen-plls-c32"; + + clocks = <&clk_sysin>; + + clock-output-names = "clk-m-a0-pll1-phi0", + "clk-m-a0-pll1-phi1", + "clk-m-a0-pll1-phi2", + "clk-m-a0-pll1-phi3"; + }; + + clk_m_a0_osc_prediv: clk-m-a0-osc-prediv { + #clock-cells = <0>; + compatible = "st,clkgena-prediv-c32", + "st,clkgena-prediv"; + + clocks = <&clk_sysin>; + + clock-output-names = "clk-m-a0-osc-prediv"; + }; + + clk_m_a0_div0: clk-m-a0-div0 { + #clock-cells = <1>; + compatible = "st,clkgena-divmux-c32-odf0", + "st,clkgena-divmux"; + + clocks = <&clk_m_a0_osc_prediv>, + <&clk_m_a0_pll0 0>, /* PLL0 PHI0 */ + <&clk_m_a0_pll1 0>; /* PLL1 PHI0 */ + + clock-output-names = "", /* Unused */ + "", /* Unused */ + "clk-m-fdma-12", + "", /* Unused */ + "clk-m-pp-dmu-0", + "clk-m-pp-dmu-1", + "clk-m-icm-lmi", + "clk-m-vid-dmu-0"; + }; + + clk_m_a0_div1: clk-m-a0-div1 { + #clock-cells = <1>; + compatible = "st,clkgena-divmux-c32-odf1", + "st,clkgena-divmux"; + + clocks = <&clk_m_a0_osc_prediv>, + <&clk_m_a0_pll0 1>, /* PLL0 PHI1 */ + <&clk_m_a0_pll1 1>; /* PLL1 PHI1 */ + + clock-output-names = "clk-m-vid-dmu-1", + "", /* Unused */ + "clk-m-a9-ext2f", + "clk-m-st40rt", + "clk-m-st231-dmu-0", + "clk-m-st231-dmu-1", + "clk-m-st231-aud", + "clk-m-st231-gp-0"; + }; + + clk_m_a0_div2: clk-m-a0-div2 { + #clock-cells = <1>; + compatible = "st,clkgena-divmux-c32-odf2", + "st,clkgena-divmux"; + + clocks = <&clk_m_a0_osc_prediv>, + <&clk_m_a0_pll0 2>, /* PLL0 PHI2 */ + <&clk_m_a0_pll1 2>; /* PLL1 PHI2 */ + + clock-output-names = "clk-m-st231-gp-1", + "clk-m-icn-cpu", + "clk-m-icn-stac", + "clk-m-tx-icn-dmu-0", + "clk-m-tx-icn-dmu-1", + "clk-m-tx-icn-ts", + "clk-m-icn-vdp-0", + "clk-m-icn-vdp-1"; + }; + + clk_m_a0_div3: clk-m-a0-div3 { + #clock-cells = <1>; + compatible = "st,clkgena-divmux-c32-odf3", + "st,clkgena-divmux"; + + clocks = <&clk_m_a0_osc_prediv>, + <&clk_m_a0_pll0 3>, /* PLL0 PHI3 */ + <&clk_m_a0_pll1 3>; /* PLL1 PHI3 */ + + clock-output-names = "", /* Unused */ + "", /* Unused */ + "", /* Unused */ + "", /* Unused */ + "clk-m-icn-vp8", + "", /* Unused */ + "clk-m-icn-reg-11", + "clk-m-a9-trace"; + }; + }; + + clockgen-a@fd6db000 { + reg = <0xfd6db000 0xb50>; + + clk_m_a1_pll0: clk-m-a1-pll0 { + #clock-cells = <1>; + compatible = "st,plls-c32-a1x-0", "st,clkgen-plls-c32"; + + clocks = <&clk_sysin>; + + clock-output-names = "clk-m-a1-pll0-phi0", + "clk-m-a1-pll0-phi1", + "clk-m-a1-pll0-phi2", + "clk-m-a1-pll0-phi3"; + }; + + clk_m_a1_pll1: clk-m-a1-pll1 { + #clock-cells = <1>; + compatible = "st,plls-c32-a1x-1", "st,clkgen-plls-c32"; + + clocks = <&clk_sysin>; + + clock-output-names = "clk-m-a1-pll1-phi0", + "clk-m-a1-pll1-phi1", + "clk-m-a1-pll1-phi2", + "clk-m-a1-pll1-phi3"; + }; + + clk_m_a1_osc_prediv: clk-m-a1-osc-prediv { + #clock-cells = <0>; + compatible = "st,clkgena-prediv-c32", + "st,clkgena-prediv"; + + clocks = <&clk_sysin>; + + clock-output-names = "clk-m-a1-osc-prediv"; + }; + + clk_m_a1_div0: clk-m-a1-div0 { + #clock-cells = <1>; + compatible = "st,clkgena-divmux-c32-odf0", + "st,clkgena-divmux"; + + clocks = <&clk_m_a1_osc_prediv>, + <&clk_m_a1_pll0 0>, /* PLL0 PHI0 */ + <&clk_m_a1_pll1 0>; /* PLL1 PHI0 */ + + clock-output-names = "", /* Unused */ + "clk-m-fdma-10", + "clk-m-fdma-11", + "clk-m-hva-alt", + "clk-m-proc-sc", + "clk-m-tp", + "clk-m-rx-icn-dmu-0", + "clk-m-rx-icn-dmu-1"; + }; + + clk_m_a1_div1: clk-m-a1-div1 { + #clock-cells = <1>; + compatible = "st,clkgena-divmux-c32-odf1", + "st,clkgena-divmux"; + + clocks = <&clk_m_a1_osc_prediv>, + <&clk_m_a1_pll0 1>, /* PLL0 PHI1 */ + <&clk_m_a1_pll1 1>; /* PLL1 PHI1 */ + + clock-output-names = "clk-m-rx-icn-ts", + "clk-m-rx-icn-vdp-0", + "", /* Unused */ + "clk-m-prv-t1-bus", + "clk-m-icn-reg-12", + "clk-m-icn-reg-10", + "", /* Unused */ + "clk-m-icn-st231"; + }; + + clk_m_a1_div2: clk-m-a1-div2 { + #clock-cells = <1>; + compatible = "st,clkgena-divmux-c32-odf2", + "st,clkgena-divmux"; + + clocks = <&clk_m_a1_osc_prediv>, + <&clk_m_a1_pll0 2>, /* PLL0 PHI2 */ + <&clk_m_a1_pll1 2>; /* PLL1 PHI2 */ + + clock-output-names = "clk-m-fvdp-proc-alt", + "clk-m-icn-reg-13", + "clk-m-tx-icn-gpu", + "clk-m-rx-icn-gpu", + "", /* Unused */ + "", /* Unused */ + "", /* clk-m-apb-pm-12 */ + ""; /* Unused */ + }; + + clk_m_a1_div3: clk-m-a1-div3 { + #clock-cells = <1>; + compatible = "st,clkgena-divmux-c32-odf3", + "st,clkgena-divmux"; + + clocks = <&clk_m_a1_osc_prediv>, + <&clk_m_a1_pll0 3>, /* PLL0 PHI3 */ + <&clk_m_a1_pll1 3>; /* PLL1 PHI3 */ + + clock-output-names = "", /* Unused */ + "", /* Unused */ + "", /* Unused */ + "", /* Unused */ + "", /* Unused */ + "", /* Unused */ + "", /* Unused */ + ""; /* clk-m-gpu-alt */ + }; + }; + + clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2 { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&clk_m_a0_div1 2>; + clock-div = <2>; + clock-mult = <1>; + }; + + clockgen-a@fd345000 { + reg = <0xfd345000 0xb50>; + + clk_m_a2_pll0: clk-m-a2-pll0 { + #clock-cells = <1>; + compatible = "st,plls-c32-a1x-0", "st,clkgen-plls-c32"; + + clocks = <&clk_sysin>; + + clock-output-names = "clk-m-a2-pll0-phi0", + "clk-m-a2-pll0-phi1", + "clk-m-a2-pll0-phi2", + "clk-m-a2-pll0-phi3"; + }; + + clk_m_a2_pll1: clk-m-a2-pll1 { + #clock-cells = <1>; + compatible = "st,plls-c32-a1x-1", "st,clkgen-plls-c32"; + + clocks = <&clk_sysin>; + + clock-output-names = "clk-m-a2-pll1-phi0", + "clk-m-a2-pll1-phi1", + "clk-m-a2-pll1-phi2", + "clk-m-a2-pll1-phi3"; + }; + + clk_m_a2_osc_prediv: clk-m-a2-osc-prediv { + #clock-cells = <0>; + compatible = "st,clkgena-prediv-c32", + "st,clkgena-prediv"; + + clocks = <&clk_sysin>; + + clock-output-names = "clk-m-a2-osc-prediv"; + }; + + clk_m_a2_div0: clk-m-a2-div0 { + #clock-cells = <1>; + compatible = "st,clkgena-divmux-c32-odf0", + "st,clkgena-divmux"; + + clocks = <&clk_m_a2_osc_prediv>, + <&clk_m_a2_pll0 0>, /* PLL0 PHI0 */ + <&clk_m_a2_pll1 0>; /* PLL1 PHI0 */ + + clock-output-names = "clk-m-vtac-main-phy", + "clk-m-vtac-aux-phy", + "clk-m-stac-phy", + "clk-m-stac-sys", + "", /* clk-m-mpestac-pg */ + "", /* clk-m-mpestac-wc */ + "", /* clk-m-mpevtacaux-pg*/ + ""; /* clk-m-mpevtacmain-pg*/ + }; + + clk_m_a2_div1: clk-m-a2-div1 { + #clock-cells = <1>; + compatible = "st,clkgena-divmux-c32-odf1", + "st,clkgena-divmux"; + + clocks = <&clk_m_a2_osc_prediv>, + <&clk_m_a2_pll0 1>, /* PLL0 PHI1 */ + <&clk_m_a2_pll1 1>; /* PLL1 PHI1 */ + + clock-output-names = "", /* clk-m-mpevtacrx0-wc */ + "", /* clk-m-mpevtacrx1-wc */ + "clk-m-compo-main", + "clk-m-compo-aux", + "clk-m-bdisp-0", + "clk-m-bdisp-1", + "clk-m-icn-bdisp", + "clk-m-icn-compo"; + }; + + clk_m_a2_div2: clk-m-a2-div2 { + #clock-cells = <1>; + compatible = "st,clkgena-divmux-c32-odf2", + "st,clkgena-divmux"; + + clocks = <&clk_m_a2_osc_prediv>, + <&clk_m_a2_pll0 2>, /* PLL0 PHI2 */ + <&clk_m_a2_pll1 2>; /* PLL1 PHI2 */ + + clock-output-names = "clk-m-icn-vdp-2", + "", /* Unused */ + "clk-m-icn-reg-14", + "clk-m-mdtp", + "clk-m-jpegdec", + "", /* Unused */ + "clk-m-dcephy-impctrl", + ""; /* Unused */ + }; + + clk_m_a2_div3: clk-m-a2-div3 { + #clock-cells = <1>; + compatible = "st,clkgena-divmux-c32-odf3", + "st,clkgena-divmux"; + + clocks = <&clk_m_a2_osc_prediv>, + <&clk_m_a2_pll0 3>, /* PLL0 PHI3 */ + <&clk_m_a2_pll1 3>; /* PLL1 PHI3 */ + + clock-output-names = "", /* Unused */ + ""; /* clk-m-apb-pm-11 */ + /* Remaining outputs unused */ + }; + }; + + /* + * A9 PLL + */ + clockgen-a9@fdde08b0 { + reg = <0xfdde08b0 0x70>; + + clockgen_a9_pll: clockgen-a9-pll { + #clock-cells = <1>; + compatible = "st,stih416-plls-c32-a9", "st,clkgen-plls-c32"; + + clocks = <&clk_sysin>; + clock-output-names = "clockgen-a9-pll-odf"; + }; + }; + + /* + * ARM CPU related clocks + */ + clk_m_a9: clk-m-a9@fdde08ac { + #clock-cells = <0>; + compatible = "st,stih416-clkgen-a9-mux", "st,clkgen-mux"; + reg = <0xfdde08ac 0x4>; + clocks = <&clockgen_a9_pll 0>, + <&clockgen_a9_pll 0>, + <&clk_m_a0_div1 2>, + <&clk_m_a9_ext2f_div2>; }; /* * ARM Peripheral clock for timers */ - arm_periph_clk: arm_periph_clk { + arm_periph_clk: clk-m-a9-periphs { #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <600000000>; + compatible = "fixed-factor-clock"; + clocks = <&clk_m_a9>; + clock-div = <2>; + clock-mult = <1>; }; /* - * Bootloader initialized system infrastructure clock for - * serial devices. + * Frequency synthesizers on the SASG2 */ - CLK_S_ICN_REG_0: clockgenA0@4 { + clockgen_b0: clockgen-b0@fee108b4 { + #clock-cells = <1>; + compatible = "st,stih416-quadfs216", "st,quadfs"; + reg = <0xfee108b4 0x44>; + + clocks = <&clk_sysin>; + clock-output-names = "clk-s-usb48", + "clk-s-dss", + "clk-s-stfe-frc-2", + "clk-s-thsens-scard"; + }; + + clockgen_b1: clockgen-b1@fe8308c4 { + #clock-cells = <1>; + compatible = "st,stih416-quadfs216", "st,quadfs"; + reg = <0xfe8308c4 0x44>; + + clocks = <&clk_sysin>; + clock-output-names = "clk-s-pcm-0", + "clk-s-pcm-1", + "clk-s-pcm-2", + "clk-s-pcm-3"; + }; + + clockgen_c: clockgen-c@fe8307d0 { + #clock-cells = <1>; + compatible = "st,stih416-quadfs432", "st,quadfs"; + reg = <0xfe8307d0 0x44>; + + clocks = <&clk_sysin>; + clock-output-names = "clk-s-c-fs0-ch0", + "clk-s-c-vcc-sd", + "clk-s-c-fs0-ch2"; + }; + + clk_s_vcc_hd: clk-s-vcc-hd@fe8308b8 { #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <100000000>; - clock-output-names = "CLK_S_ICN_REG_0"; + compatible = "st,stih416-clkgenc-vcc-hd", "st,clkgen-mux"; + reg = <0xfe8308b8 0x4>; /* SYSCFG2558 */ + + clocks = <&clk_sysin>, + <&clockgen_c 0>; }; - CLK_S_GMAC0_PHY: clockgenA1@7 { + /* + * Add a dummy clock for the HDMI PHY for the VCC input mux + */ + clk_s_tmds_fromphy: clk-s-tmds-fromphy { #clock-cells = <0>; compatible = "fixed-clock"; - clock-frequency = <25000000>; - clock-output-names = "CLK_S_GMAC0_PHY"; + clock-frequency = <0>; + }; + + clockgen_c_vcc: clockgen-c-vcc@fe8308ac { + #clock-cells = <1>; + compatible = "st,stih416-clkgenc", "st,clkgen-vcc"; + reg = <0xfe8308ac 0xc>; /* SYSCFG2555,2556,2557 */ + + clocks = <&clk_s_vcc_hd>, + <&clockgen_c 1>, + <&clk_s_tmds_fromphy>, + <&clockgen_c 2>; + + clock-output-names = "clk-s-pix-hdmi", + "clk-s-pix-dvo", + "clk-s-out-dvo", + "clk-s-pix-hd", + "clk-s-hddac", + "clk-s-denc", + "clk-s-sddac", + "clk-s-pix-main", + "clk-s-pix-aux", + "clk-s-stfe-frc-0", + "clk-s-ref-mcru", + "clk-s-slave-mcru", + "clk-s-tmds-hdmi", + "clk-s-hdmi-reject-pll", + "clk-s-thsens"; }; - CLK_S_ETH1_PHY: clockgenA0@7 { + clockgen_d: clockgen-d@fee107e0 { + #clock-cells = <1>; + compatible = "st,stih416-quadfs216", "st,quadfs"; + reg = <0xfee107e0 0x44>; + + clocks = <&clk_sysin>; + clock-output-names = "clk-s-ccsc", + "clk-s-stfe-frc-1", + "clk-s-tsout-1", + "clk-s-mchi"; + }; + + /* + * Frequency synthesizers on the MPE42 + */ + clockgen_e: clockgen-e@fd3208bc { + #clock-cells = <1>; + compatible = "st,stih416-quadfs660-E", "st,quadfs"; + reg = <0xfd3208bc 0xb0>; + + clocks = <&clk_sysin>; + clock-output-names = "clk-m-pix-mdtp-0", + "clk-m-pix-mdtp-1", + "clk-m-pix-mdtp-2", + "clk-m-mpelpc"; + }; + + clockgen_f: clockgen-f@fd320878 { + #clock-cells = <1>; + compatible = "st,stih416-quadfs660-F", "st,quadfs"; + reg = <0xfd320878 0xf0>; + + clocks = <&clk_sysin>; + clock-output-names = "clk-m-main-vidfs", + "clk-m-hva-fs", + "clk-m-fvdp-vcpu", + "clk-m-fvdp-proc-fs"; + }; + + clk_m_fvdp_proc: clk-m-fvdp-proc@fd320910 { + #clock-cells = <0>; + compatible = "st,stih416-clkgenf-vcc-fvdp", "st,clkgen-mux"; + reg = <0xfd320910 0x4>; /* SYSCFG8580 */ + + clocks = <&clk_m_a1_div2 0>, + <&clockgen_f 3>; + }; + + clk_m_hva: clk-m-hva@fd690868 { + #clock-cells = <0>; + compatible = "st,stih416-clkgenf-vcc-hva", "st,clkgen-mux"; + reg = <0xfd690868 0x4>; /* SYSCFG9538 */ + + clocks = <&clockgen_f 1>, + <&clk_m_a1_div0 3>; + }; + + clk_m_f_vcc_hd: clk-m-f-vcc-hd@fd32086c { + #clock-cells = <0>; + compatible = "st,stih416-clkgenf-vcc-hd", "st,clkgen-mux"; + reg = <0xfd32086c 0x4>; /* SYSCFG8539 */ + + clocks = <&clockgen_c_vcc 7>, + <&clockgen_f 0>; + }; + + clk_m_f_vcc_sd: clk-m-f-vcc-sd@fd32086c { + #clock-cells = <0>; + compatible = "st,stih416-clkgenf-vcc-sd", "st,clkgen-mux"; + reg = <0xfd32086c 0x4>; /* SYSCFG8539 */ + + clocks = <&clockgen_c_vcc 8>, + <&clockgen_f 1>; + }; + + /* + * Add a dummy clock for the HDMIRx external signal clock + */ + clk_m_pix_hdmirx_sas: clk-m-pix-hdmirx-sas { #clock-cells = <0>; compatible = "fixed-clock"; - clock-frequency = <25000000>; - clock-output-names = "CLK_S_ETH1_PHY"; + clock-frequency = <0>; + }; + + clockgen_f_vcc: clockgen-f-vcc@fd32086c { + #clock-cells = <1>; + compatible = "st,stih416-clkgenf", "st,clkgen-vcc"; + reg = <0xfd32086c 0xc>; /* SYSCFG8539,8540,8541 */ + + clocks = <&clk_m_f_vcc_hd>, + <&clk_m_f_vcc_sd>, + <&clockgen_f 0>, + <&clk_m_pix_hdmirx_sas>; + + clock-output-names = "clk-m-pix-main-pipe", + "clk-m-pix-aux-pipe", + "clk-m-pix-main-cru", + "clk-m-pix-aux-cru", + "clk-m-xfer-be-compo", + "clk-m-xfer-pip-compo", + "clk-m-xfer-aux-compo", + "clk-m-vsens", + "clk-m-pix-hdmirx-0", + "clk-m-pix-hdmirx-1"; + }; + + /* + * DDR PLL + */ + clockgen-ddr@0xfdde07d8 { + reg = <0xfdde07d8 0x110>; + + clockgen_ddr_pll: clockgen-ddr-pll { + #clock-cells = <1>; + compatible = "st,stih416-plls-c32-ddr", "st,clkgen-plls-c32"; + + clocks = <&clk_sysin>; + clock-output-names = "clockgen-ddr0", + "clockgen-ddr1"; + }; + }; + + /* + * GPU PLL + */ + clockgen-gpu@fd68ff00 { + reg = <0xfd68ff00 0x910>; + + clockgen_gpu_pll: clockgen-gpu-pll { + #clock-cells = <1>; + compatible = "st,stih416-gpu-pll-c32", "st,clkgengpu-pll-c32"; + + clocks = <&clk_sysin>; + clock-output-names = "clockgen-gpu-pll"; + }; }; }; }; diff --git a/arch/arm/boot/dts/stih416-pinctrl.dtsi b/arch/arm/boot/dts/stih416-pinctrl.dtsi index 250d5ecc951e..ee6c119e261e 100644 --- a/arch/arm/boot/dts/stih416-pinctrl.dtsi +++ b/arch/arm/boot/dts/stih416-pinctrl.dtsi @@ -122,6 +122,22 @@ }; }; + keyscan { + pinctrl_keyscan: keyscan { + st,pins { + keyin0 = <&PIO0 2 ALT2 IN>; + keyin1 = <&PIO0 3 ALT2 IN>; + keyin2 = <&PIO0 4 ALT2 IN>; + keyin3 = <&PIO2 6 ALT2 IN>; + + keyout0 = <&PIO1 6 ALT2 OUT>; + keyout1 = <&PIO1 7 ALT2 OUT>; + keyout2 = <&PIO0 6 ALT2 OUT>; + keyout3 = <&PIO2 7 ALT2 OUT>; + }; + }; + }; + sbc_i2c0 { pinctrl_sbc_i2c0_default: sbc_i2c0-default { st,pins { diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi index 78746d20382e..06473c5d9ea9 100644 --- a/arch/arm/boot/dts/stih416.dtsi +++ b/arch/arm/boot/dts/stih416.dtsi @@ -89,7 +89,7 @@ status = "disabled"; reg = <0xfed32000 0x2c>; interrupts = <0 197 0>; - clocks = <&CLK_S_ICN_REG_0>; + clocks = <&clk_s_a0_ls CLK_ICN_REG>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_serial2 &pinctrl_serial2_oe>; }; @@ -102,14 +102,14 @@ interrupts = <0 210 0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sbc_serial1>; - clocks = <&CLK_SYSIN>; + clocks = <&clk_sysin>; }; i2c@fed40000 { compatible = "st,comms-ssc4-i2c"; reg = <0xfed40000 0x110>; interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&CLK_S_ICN_REG_0>; + clocks = <&clk_s_a0_ls CLK_ICN_REG>; clock-names = "ssc"; clock-frequency = <400000>; pinctrl-names = "default"; @@ -122,7 +122,7 @@ compatible = "st,comms-ssc4-i2c"; reg = <0xfed41000 0x110>; interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&CLK_S_ICN_REG_0>; + clocks = <&clk_s_a0_ls CLK_ICN_REG>; clock-names = "ssc"; clock-frequency = <400000>; pinctrl-names = "default"; @@ -135,7 +135,7 @@ compatible = "st,comms-ssc4-i2c"; reg = <0xfe540000 0x110>; interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&CLK_SYSIN>; + clocks = <&clk_sysin>; clock-names = "ssc"; clock-frequency = <400000>; pinctrl-names = "default"; @@ -148,7 +148,7 @@ compatible = "st,comms-ssc4-i2c"; reg = <0xfe541000 0x110>; interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&CLK_SYSIN>; + clocks = <&clk_sysin>; clock-names = "ssc"; clock-frequency = <400000>; pinctrl-names = "default"; @@ -176,7 +176,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_mii0>; clock-names = "stmmaceth"; - clocks = <&CLK_S_GMAC0_PHY>; + clocks = <&clk_s_a1_ls CLK_GMAC0_PHY>; }; ethernet1: dwmac@fef08000 { @@ -198,7 +198,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_mii1>; clock-names = "stmmaceth"; - clocks = <&CLK_S_ETH1_PHY>; + clocks = <&clk_s_a0_ls CLK_ETH1_PHY>; }; rc: rc@fe518000 { @@ -206,7 +206,7 @@ reg = <0xfe518000 0x234>; interrupts = <0 203 0>; rx-mode = "infrared"; - clocks = <&CLK_SYSIN>; + clocks = <&clk_sysin>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ir>; resets = <&softreset STIH416_IRB_SOFTRESET>; @@ -224,5 +224,17 @@ status = "disabled"; }; + + keyscan: keyscan@fe4b0000 { + compatible = "st,sti-keyscan"; + status = "disabled"; + reg = <0xfe4b0000 0x2000>; + interrupts = <GIC_SPI 212 IRQ_TYPE_NONE>; + clocks = <&clk_sysin>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_keyscan>; + resets = <&powerdown STIH416_KEYSCAN_POWERDOWN>, + <&softreset STIH416_KEYSCAN_SOFTRESET>; + }; }; }; diff --git a/arch/arm/boot/dts/stih41x-b2000.dtsi b/arch/arm/boot/dts/stih41x-b2000.dtsi index bf65c49095af..b3dd6ca5c2ae 100644 --- a/arch/arm/boot/dts/stih41x-b2000.dtsi +++ b/arch/arm/boot/dts/stih41x-b2000.dtsi @@ -6,6 +6,7 @@ * it under the terms of the GNU General Public License version 2 as * publishhed by the Free Software Foundation. */ +#include <dt-bindings/input/input.h> / { memory{ @@ -14,7 +15,7 @@ }; chosen { - bootargs = "console=ttyAS0,115200"; + bootargs = "console=ttyAS0,115200 clk_ignore_unused"; linux,stdout-path = &serial2; }; @@ -68,5 +69,27 @@ snps,reset-active-low; snps,reset-delays-us = <0 10000 10000>; }; + + keyscan: keyscan@fe4b0000 { + keypad,num-rows = <4>; + keypad,num-columns = <4>; + st,debounce-us = <5000>; + linux,keymap = < MATRIX_KEY(0x00, 0x00, KEY_F13) + MATRIX_KEY(0x00, 0x01, KEY_F9) + MATRIX_KEY(0x00, 0x02, KEY_F5) + MATRIX_KEY(0x00, 0x03, KEY_F1) + MATRIX_KEY(0x01, 0x00, KEY_F14) + MATRIX_KEY(0x01, 0x01, KEY_F10) + MATRIX_KEY(0x01, 0x02, KEY_F6) + MATRIX_KEY(0x01, 0x03, KEY_F2) + MATRIX_KEY(0x02, 0x00, KEY_F15) + MATRIX_KEY(0x02, 0x01, KEY_F11) + MATRIX_KEY(0x02, 0x02, KEY_F7) + MATRIX_KEY(0x02, 0x03, KEY_F3) + MATRIX_KEY(0x03, 0x00, KEY_F16) + MATRIX_KEY(0x03, 0x01, KEY_F12) + MATRIX_KEY(0x03, 0x02, KEY_F8) + MATRIX_KEY(0x03, 0x03, KEY_F4) >; + }; }; }; diff --git a/arch/arm/boot/dts/stih41x-b2020.dtsi b/arch/arm/boot/dts/stih41x-b2020.dtsi index 838513f9ddc0..d8a84295c328 100644 --- a/arch/arm/boot/dts/stih41x-b2020.dtsi +++ b/arch/arm/boot/dts/stih41x-b2020.dtsi @@ -14,7 +14,7 @@ }; chosen { - bootargs = "console=ttyAS0,115200"; + bootargs = "console=ttyAS0,115200 clk_ignore_unused"; linux,stdout-path = &sbc_serial1; }; diff --git a/arch/arm/boot/dts/stih41x.dtsi b/arch/arm/boot/dts/stih41x.dtsi index f5b9898d9c6e..5cb0e63376b5 100644 --- a/arch/arm/boot/dts/stih41x.dtsi +++ b/arch/arm/boot/dts/stih41x.dtsi @@ -1,3 +1,10 @@ +/* + * Copyright (C) 2014 STMicroelectronics Limited. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * publishhed by the Free Software Foundation. + */ / { #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/sun4i-a10-a1000.dts b/arch/arm/boot/dts/sun4i-a10-a1000.dts index fa746aea5e66..0b97c071dd56 100644 --- a/arch/arm/boot/dts/sun4i-a10-a1000.dts +++ b/arch/arm/boot/dts/sun4i-a10-a1000.dts @@ -36,6 +36,16 @@ }; }; + mmc0: mmc@01c0f000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 1 0>; /* PH1 */ + cd-inverted; + status = "okay"; + }; + usbphy: phy@01c13400 { usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>; diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts index 4684cbe6843b..c200eacc66e8 100644 --- a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts +++ b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts @@ -34,6 +34,16 @@ }; }; + mmc0: mmc@01c0f000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 1 0>; /* PH1 */ + cd-inverted; + status = "okay"; + }; + usbphy: phy@01c13400 { usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>; diff --git a/arch/arm/boot/dts/sun4i-a10-hackberry.dts b/arch/arm/boot/dts/sun4i-a10-hackberry.dts index d7c17e46ce23..547fadcb984b 100644 --- a/arch/arm/boot/dts/sun4i-a10-hackberry.dts +++ b/arch/arm/boot/dts/sun4i-a10-hackberry.dts @@ -36,6 +36,16 @@ }; }; + mmc0: mmc@01c0f000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 1 0>; /* PH1 */ + cd-inverted; + status = "okay"; + }; + usbphy: phy@01c13400 { usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>; diff --git a/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts b/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts index fe9272ee55c3..f13723e18b86 100644 --- a/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts +++ b/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts @@ -24,6 +24,16 @@ }; soc@01c00000 { + mmc0: mmc@01c0f000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 1 0>; /* PH1 */ + cd-inverted; + status = "okay"; + }; + uart0: serial@01c28000 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_a>; diff --git a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts index dd84a9e313b3..c01cea50cf0c 100644 --- a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts +++ b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts @@ -20,6 +20,16 @@ compatible = "pineriver,mini-xplus", "allwinner,sun4i-a10"; soc@01c00000 { + mmc0: mmc@01c0f000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 1 0>; /* PH1 */ + cd-inverted; + status = "okay"; + }; + usbphy: phy@01c13400 { usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>; diff --git a/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts b/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts index 66cf0c7cf5b7..d46a7dbecef5 100644 --- a/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts +++ b/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts @@ -33,6 +33,16 @@ }; }; + mmc0: mmc@01c0f000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 1 0>; /* PH1 */ + cd-inverted; + status = "okay"; + }; + usbphy: phy@01c13400 { usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>; diff --git a/arch/arm/boot/dts/sun4i-a10-pcduino.dts b/arch/arm/boot/dts/sun4i-a10-pcduino.dts index 255b47e7019c..fb03bccb78d2 100644 --- a/arch/arm/boot/dts/sun4i-a10-pcduino.dts +++ b/arch/arm/boot/dts/sun4i-a10-pcduino.dts @@ -34,6 +34,16 @@ }; }; + mmc0: mmc@01c0f000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 1 0>; /* PH1 */ + cd-inverted; + status = "okay"; + }; + usbphy: phy@01c13400 { usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>; diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi index 9174724571e2..d96e179490ce 100644 --- a/arch/arm/boot/dts/sun4i-a10.dtsi +++ b/arch/arm/boot/dts/sun4i-a10.dtsi @@ -377,6 +377,42 @@ #size-cells = <0>; }; + mmc0: mmc@01c0f000 { + compatible = "allwinner,sun4i-a10-mmc"; + reg = <0x01c0f000 0x1000>; + clocks = <&ahb_gates 8>, <&mmc0_clk>; + clock-names = "ahb", "mmc"; + interrupts = <32>; + status = "disabled"; + }; + + mmc1: mmc@01c10000 { + compatible = "allwinner,sun4i-a10-mmc"; + reg = <0x01c10000 0x1000>; + clocks = <&ahb_gates 9>, <&mmc1_clk>; + clock-names = "ahb", "mmc"; + interrupts = <33>; + status = "disabled"; + }; + + mmc2: mmc@01c11000 { + compatible = "allwinner,sun4i-a10-mmc"; + reg = <0x01c11000 0x1000>; + clocks = <&ahb_gates 10>, <&mmc2_clk>; + clock-names = "ahb", "mmc"; + interrupts = <34>; + status = "disabled"; + }; + + mmc3: mmc@01c12000 { + compatible = "allwinner,sun4i-a10-mmc"; + reg = <0x01c12000 0x1000>; + clocks = <&ahb_gates 11>, <&mmc3_clk>; + clock-names = "ahb", "mmc"; + interrupts = <35>; + status = "disabled"; + }; + usbphy: phy@01c13400 { #phy-cells = <1>; compatible = "allwinner,sun4i-a10-usb-phy"; @@ -477,6 +513,20 @@ #size-cells = <0>; #gpio-cells = <3>; + pwm0_pins_a: pwm0@0 { + allwinner,pins = "PB2"; + allwinner,function = "pwm"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + pwm1_pins_a: pwm1@0 { + allwinner,pins = "PI3"; + allwinner,function = "pwm"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + uart0_pins_a: uart0@0 { allwinner,pins = "PB22", "PB23"; allwinner,function = "uart0"; @@ -529,6 +579,20 @@ allwinner,drive = <0>; allwinner,pull = <0>; }; + + mmc0_pins_a: mmc0@0 { + allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5"; + allwinner,function = "mmc0"; + allwinner,drive = <2>; + allwinner,pull = <0>; + }; + + mmc0_cd_pin_reference_design: mmc0_cd_pin@0 { + allwinner,pins = "PH1"; + allwinner,function = "gpio_in"; + allwinner,drive = <0>; + allwinner,pull = <1>; + }; }; timer@01c20c00 { @@ -549,6 +613,14 @@ interrupts = <24>; }; + pwm: pwm@01c20e00 { + compatible = "allwinner,sun4i-a10-pwm"; + reg = <0x01c20e00 0xc>; + clocks = <&osc24M>; + #pwm-cells = <3>; + status = "disabled"; + }; + sid: eeprom@01c23800 { compatible = "allwinner,sun4i-a10-sid"; reg = <0x01c23800 0x10>; @@ -641,30 +713,36 @@ }; i2c0: i2c@01c2ac00 { - compatible = "allwinner,sun4i-i2c"; + compatible = "allwinner,sun4i-a10-i2c"; reg = <0x01c2ac00 0x400>; interrupts = <7>; clocks = <&apb1_gates 0>; clock-frequency = <100000>; status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; }; i2c1: i2c@01c2b000 { - compatible = "allwinner,sun4i-i2c"; + compatible = "allwinner,sun4i-a10-i2c"; reg = <0x01c2b000 0x400>; interrupts = <8>; clocks = <&apb1_gates 1>; clock-frequency = <100000>; status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; }; i2c2: i2c@01c2b400 { - compatible = "allwinner,sun4i-i2c"; + compatible = "allwinner,sun4i-a10-i2c"; reg = <0x01c2b400 0x400>; interrupts = <9>; clocks = <&apb1_gates 2>; clock-frequency = <100000>; status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; }; }; }; diff --git a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts index 23611b71d3aa..ea9519da5764 100644 --- a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts +++ b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts @@ -35,6 +35,26 @@ }; }; + mmc0: mmc@01c0f000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_olinuxino_micro>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 6 1 0>; /* PG1 */ + cd-inverted; + status = "okay"; + }; + + mmc1: mmc@01c10000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins_a>, <&mmc1_cd_pin_olinuxino_micro>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 6 13 0>; /* PG13 */ + cd-inverted; + status = "okay"; + }; + usbphy: phy@01c13400 { usb1_vbus-supply = <®_usb1_vbus>; status = "okay"; @@ -49,6 +69,20 @@ }; pinctrl@01c20800 { + mmc0_cd_pin_olinuxino_micro: mmc0_cd_pin@0 { + allwinner,pins = "PG1"; + allwinner,function = "gpio_in"; + allwinner,drive = <0>; + allwinner,pull = <1>; + }; + + mmc1_cd_pin_olinuxino_micro: mmc1_cd_pin@0 { + allwinner,pins = "PG13"; + allwinner,function = "gpio_in"; + allwinner,drive = <0>; + allwinner,pull = <1>; + }; + led_pins_olinuxino: led_pins@0 { allwinner,pins = "PE3"; allwinner,function = "gpio_out"; diff --git a/arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts b/arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts new file mode 100644 index 000000000000..43a93762d4f2 --- /dev/null +++ b/arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts @@ -0,0 +1,100 @@ +/* + * Copyright 2014 Hans de Goede <hdegoede@redhat.com> + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "sun5i-a10s.dtsi" +/include/ "sunxi-common-regulators.dtsi" + +/ { + model = "R7 A10s hdmi tv-stick"; + compatible = "allwinner,r7-tv-dongle", "allwinner,sun5i-a10s"; + + soc@01c00000 { + mmc0: mmc@01c0f000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_r7>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 6 1 0>; /* PG1 */ + cd-inverted; + status = "okay"; + }; + + mmc1: mmc@01c10000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins_a>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + non-removable; + status = "okay"; + }; + + usbphy: phy@01c13400 { + usb1_vbus-supply = <®_usb1_vbus>; + status = "okay"; + }; + + ehci0: usb@01c14000 { + status = "okay"; + }; + + ohci0: usb@01c14400 { + status = "okay"; + }; + + pinctrl@01c20800 { + mmc0_cd_pin_r7: mmc0_cd_pin@0 { + allwinner,pins = "PG1"; + allwinner,function = "gpio_in"; + allwinner,drive = <0>; + allwinner,pull = <1>; + }; + + led_pins_r7: led_pins@0 { + allwinner,pins = "PB2"; + allwinner,function = "gpio_out"; + allwinner,drive = <1>; + allwinner,pull = <0>; + }; + + usb1_vbus_pin_r7: usb1_vbus_pin@0 { + allwinner,pins = "PG13"; + allwinner,function = "gpio_out"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + }; + + uart0: serial@01c28000 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins_r7>; + + green { + label = "r7-tv-dongle:green:usr"; + gpios = <&pio 1 2 0>; + default-state = "on"; + }; + }; + + reg_usb1_vbus: usb1-vbus { + pinctrl-0 = <&usb1_vbus_pin_r7>; + gpio = <&pio 6 13 0>; + status = "okay"; + }; +}; diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi index 79989ed5658d..b64f705d9008 100644 --- a/arch/arm/boot/dts/sun5i-a10s.dtsi +++ b/arch/arm/boot/dts/sun5i-a10s.dtsi @@ -338,6 +338,33 @@ #size-cells = <0>; }; + mmc0: mmc@01c0f000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c0f000 0x1000>; + clocks = <&ahb_gates 8>, <&mmc0_clk>; + clock-names = "ahb", "mmc"; + interrupts = <32>; + status = "disabled"; + }; + + mmc1: mmc@01c10000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c10000 0x1000>; + clocks = <&ahb_gates 9>, <&mmc1_clk>; + clock-names = "ahb", "mmc"; + interrupts = <33>; + status = "disabled"; + }; + + mmc2: mmc@01c11000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c11000 0x1000>; + clocks = <&ahb_gates 10>, <&mmc2_clk>; + clock-names = "ahb", "mmc"; + interrupts = <34>; + status = "disabled"; + }; + usbphy: phy@01c13400 { #phy-cells = <1>; compatible = "allwinner,sun5i-a13-usb-phy"; @@ -451,6 +478,20 @@ allwinner,drive = <0>; allwinner,pull = <0>; }; + + mmc0_pins_a: mmc0@0 { + allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5"; + allwinner,function = "mmc0"; + allwinner,drive = <2>; + allwinner,pull = <0>; + }; + + mmc1_pins_a: mmc1@0 { + allwinner,pins = "PG3","PG4","PG5","PG6","PG7","PG8"; + allwinner,function = "mmc1"; + allwinner,drive = <2>; + allwinner,pull = <0>; + }; }; timer@01c20c00 { @@ -519,7 +560,7 @@ i2c0: i2c@01c2ac00 { #address-cells = <1>; #size-cells = <0>; - compatible = "allwinner,sun4i-i2c"; + compatible = "allwinner,sun5i-a10s-i2c", "allwinner,sun4i-a10-i2c"; reg = <0x01c2ac00 0x400>; interrupts = <7>; clocks = <&apb1_gates 0>; @@ -530,7 +571,7 @@ i2c1: i2c@01c2b000 { #address-cells = <1>; #size-cells = <0>; - compatible = "allwinner,sun4i-i2c"; + compatible = "allwinner,sun5i-a10s-i2c", "allwinner,sun4i-a10-i2c"; reg = <0x01c2b000 0x400>; interrupts = <8>; clocks = <&apb1_gates 1>; @@ -541,7 +582,7 @@ i2c2: i2c@01c2b400 { #address-cells = <1>; #size-cells = <0>; - compatible = "allwinner,sun4i-i2c"; + compatible = "allwinner,sun5i-a10s-i2c", "allwinner,sun4i-a10-i2c"; reg = <0x01c2b400 0x400>; interrupts = <9>; clocks = <&apb1_gates 2>; diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts index 11169d5b5b86..fa44b026483b 100644 --- a/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts +++ b/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts @@ -21,6 +21,16 @@ compatible = "olimex,a13-olinuxino-micro", "allwinner,sun5i-a13"; soc@01c00000 { + mmc0: mmc@01c0f000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_olinuxinom>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 6 0 0>; /* PG0 */ + cd-inverted; + status = "okay"; + }; + usbphy: phy@01c13400 { usb1_vbus-supply = <®_usb1_vbus>; status = "okay"; @@ -35,6 +45,13 @@ }; pinctrl@01c20800 { + mmc0_cd_pin_olinuxinom: mmc0_cd_pin@0 { + allwinner,pins = "PG0"; + allwinner,function = "gpio_in"; + allwinner,drive = <0>; + allwinner,pull = <1>; + }; + led_pins_olinuxinom: led_pins@0 { allwinner,pins = "PG9"; allwinner,function = "gpio_out"; diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts index 7a9187bbeb28..429994e1943e 100644 --- a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts +++ b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts @@ -20,6 +20,16 @@ compatible = "olimex,a13-olinuxino", "allwinner,sun5i-a13"; soc@01c00000 { + mmc0: mmc@01c0f000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_olinuxino>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 6 0 0>; /* PG0 */ + cd-inverted; + status = "okay"; + }; + usbphy: phy@01c13400 { usb1_vbus-supply = <®_usb1_vbus>; status = "okay"; @@ -34,6 +44,13 @@ }; pinctrl@01c20800 { + mmc0_cd_pin_olinuxino: mmc0_cd_pin@0 { + allwinner,pins = "PG0"; + allwinner,function = "gpio_in"; + allwinner,drive = <0>; + allwinner,pull = <1>; + }; + led_pins_olinuxino: led_pins@0 { allwinner,pins = "PG9"; allwinner,function = "gpio_out"; diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi index f01c315bdc4b..3b2a94c40f6e 100644 --- a/arch/arm/boot/dts/sun5i-a13.dtsi +++ b/arch/arm/boot/dts/sun5i-a13.dtsi @@ -320,6 +320,24 @@ #size-cells = <0>; }; + mmc0: mmc@01c0f000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c0f000 0x1000>; + clocks = <&ahb_gates 8>, <&mmc0_clk>; + clock-names = "ahb", "mmc"; + interrupts = <32>; + status = "disabled"; + }; + + mmc2: mmc@01c11000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c11000 0x1000>; + clocks = <&ahb_gates 10>, <&mmc2_clk>; + clock-names = "ahb", "mmc"; + interrupts = <34>; + status = "disabled"; + }; + usbphy: phy@01c13400 { #phy-cells = <1>; compatible = "allwinner,sun5i-a13-usb-phy"; @@ -415,6 +433,13 @@ allwinner,drive = <0>; allwinner,pull = <0>; }; + + mmc0_pins_a: mmc0@0 { + allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5"; + allwinner,function = "mmc0"; + allwinner,drive = <2>; + allwinner,pull = <0>; + }; }; timer@01c20c00 { @@ -461,30 +486,36 @@ }; i2c0: i2c@01c2ac00 { - compatible = "allwinner,sun4i-i2c"; + compatible = "allwinner,sun5i-a13-i2c", "allwinner,sun4i-a10-i2c"; reg = <0x01c2ac00 0x400>; interrupts = <7>; clocks = <&apb1_gates 0>; clock-frequency = <100000>; status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; }; i2c1: i2c@01c2b000 { - compatible = "allwinner,sun4i-i2c"; + compatible = "allwinner,sun5i-a13-i2c", "allwinner,sun4i-a10-i2c"; reg = <0x01c2b000 0x400>; interrupts = <8>; clocks = <&apb1_gates 1>; clock-frequency = <100000>; status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; }; i2c2: i2c@01c2b400 { - compatible = "allwinner,sun4i-i2c"; + compatible = "allwinner,sun5i-a13-i2c", "allwinner,sun4i-a10-i2c"; reg = <0x01c2b400 0x400>; interrupts = <9>; clocks = <&apb1_gates 2>; clock-frequency = <100000>; status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; }; timer@01c60000 { diff --git a/arch/arm/boot/dts/sun6i-a31-app4-evb1.dts b/arch/arm/boot/dts/sun6i-a31-app4-evb1.dts new file mode 100644 index 000000000000..2bbf8867362b --- /dev/null +++ b/arch/arm/boot/dts/sun6i-a31-app4-evb1.dts @@ -0,0 +1,57 @@ +/* + * Copyright 2014 Boris Brezillon + * + * Boris Brezillon <boris.brezillon@free-electrons.com> + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "sun6i-a31.dtsi" +/include/ "sunxi-common-regulators.dtsi" + +/ { + model = "Allwinner A31 APP4 EVB1 Evaluation Board"; + compatible = "allwinner,app4-evb1", "allwinner,sun6i-a31"; + + chosen { + bootargs = "earlyprintk console=ttyS0,115200"; + }; + + soc@01c00000 { + pio: pinctrl@01c20800 { + usb1_vbus_pin_a: usb1_vbus_pin@0 { + allwinner,pins = "PH27"; + allwinner,function = "gpio_out"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + }; + + usbphy: phy@01c19400 { + usb1_vbus-supply = <®_usb1_vbus>; + status = "okay"; + }; + + ehci0: usb@01c1a000 { + status = "okay"; + }; + + uart0: serial@01c28000 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; + }; + }; + + reg_usb1_vbus: usb1-vbus { + pinctrl-0 = <&usb1_vbus_pin_a>; + gpio = <&pio 7 27 0>; + status = "okay"; + }; +}; diff --git a/arch/arm/boot/dts/sun6i-a31-colombus.dts b/arch/arm/boot/dts/sun6i-a31-colombus.dts index 3898a7bce831..546cf6eff5c7 100644 --- a/arch/arm/boot/dts/sun6i-a31-colombus.dts +++ b/arch/arm/boot/dts/sun6i-a31-colombus.dts @@ -13,6 +13,7 @@ /dts-v1/; /include/ "sun6i-a31.dtsi" +/include/ "sunxi-common-regulators.dtsi" / { model = "WITS A31 Colombus Evaluation Board"; @@ -23,6 +24,45 @@ }; soc@01c00000 { + mmc0: mmc@01c0f000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_colombus>; + vmmc-supply = <®_vcc3v0>; + bus-width = <4>; + cd-gpios = <&pio 0 8 0>; /* PA8 */ + cd-inverted; + status = "okay"; + }; + + usbphy: phy@01c19400 { + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; + }; + + ehci1: usb@01c1b000 { + status = "okay"; + }; + + pio: pinctrl@01c20800 { + mmc0_pins_a: mmc0@0 { + allwinner,pull = <1>; + }; + + mmc0_cd_pin_colombus: mmc0_cd_pin@0 { + allwinner,pins = "PA8"; + allwinner,function = "gpio_in"; + allwinner,drive = <0>; + allwinner,pull = <1>; + }; + + usb2_vbus_pin_colombus: usb2_vbus_pin@0 { + allwinner,pins = "PH24"; + allwinner,function = "gpio_out"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + }; + uart0: serial@01c28000 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_a>; @@ -47,4 +87,11 @@ status = "okay"; }; }; + + reg_usb2_vbus: usb2-vbus { + pinctrl-names = "default"; + pinctrl-0 = <&usb2_vbus_pin_colombus>; + gpio = <&pio 7 24 0>; + status = "okay"; + }; }; diff --git a/arch/arm/boot/dts/sun6i-a31-m9.dts b/arch/arm/boot/dts/sun6i-a31-m9.dts new file mode 100644 index 000000000000..bc6115da5ae1 --- /dev/null +++ b/arch/arm/boot/dts/sun6i-a31-m9.dts @@ -0,0 +1,50 @@ +/* + * Copyright 2014 Hans de Goede <hdegoede@redhat.com> + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "sun6i-a31.dtsi" +/include/ "sunxi-common-regulators.dtsi" + +/ { + model = "Mele M9 / A1000G Quad top set box"; + compatible = "mele,m9", "allwinner,sun6i-a31"; + + chosen { + bootargs = "earlyprintk console=ttyS0,115200"; + }; + + soc@01c00000 { + mmc0: mmc@01c0f000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_m9>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 22 0>; /* PH22 */ + cd-inverted; + status = "okay"; + }; + + pio: pinctrl@01c20800 { + mmc0_cd_pin_m9: mmc0_cd_pin@0 { + allwinner,pins = "PH22"; + allwinner,function = "gpio_in"; + allwinner,drive = <0>; + allwinner,pull = <1>; + }; + }; + + uart0: serial@01c28000 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; + }; + }; +}; diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index d45efa74827c..a9dfa12eb735 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -27,6 +27,7 @@ cpus { + enable-method = "allwinner,sun6i-a31"; #address-cells = <1>; #size-cells = <0>; @@ -59,6 +60,14 @@ reg = <0x40000000 0x80000000>; }; + pmu { + compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu"; + interrupts = <0 120 4>, + <0 121 4>, + <0 122 4>, + <0 123 4>; + }; + clocks { #address-cells = <1>; #size-cells = <1>; @@ -198,6 +207,38 @@ "apb2_uart4", "apb2_uart5"; }; + mmc0_clk: clk@01c20088 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + reg = <0x01c20088 0x4>; + clocks = <&osc24M>, <&pll6>; + clock-output-names = "mmc0"; + }; + + mmc1_clk: clk@01c2008c { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + reg = <0x01c2008c 0x4>; + clocks = <&osc24M>, <&pll6>; + clock-output-names = "mmc1"; + }; + + mmc2_clk: clk@01c20090 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + reg = <0x01c20090 0x4>; + clocks = <&osc24M>, <&pll6>; + clock-output-names = "mmc2"; + }; + + mmc3_clk: clk@01c20094 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + reg = <0x01c20094 0x4>; + clocks = <&osc24M>, <&pll6>; + clock-output-names = "mmc3"; + }; + spi0_clk: clk@01c200a0 { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-mod0-clk"; @@ -229,6 +270,17 @@ clocks = <&osc24M>, <&pll6>; clock-output-names = "spi3"; }; + + usb_clk: clk@01c200cc { + #clock-cells = <1>; + #reset-cells = <1>; + compatible = "allwinner,sun6i-a31-usb-clk"; + reg = <0x01c200cc 0x4>; + clocks = <&osc24M>; + clock-output-names = "usb_phy0", "usb_phy1", "usb_phy2", + "usb_ohci0", "usb_ohci1", + "usb_ohci2"; + }; }; soc@01c00000 { @@ -237,12 +289,134 @@ #size-cells = <1>; ranges; - nmi_intc: interrupt-controller@01f00c0c { - compatible = "allwinner,sun6i-a31-sc-nmi"; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x01f00c0c 0x38>; - interrupts = <0 32 4>; + dma: dma-controller@01c02000 { + compatible = "allwinner,sun6i-a31-dma"; + reg = <0x01c02000 0x1000>; + interrupts = <0 50 4>; + clocks = <&ahb1_gates 6>; + resets = <&ahb1_rst 6>; + #dma-cells = <1>; + }; + + mmc0: mmc@01c0f000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c0f000 0x1000>; + clocks = <&ahb1_gates 8>, <&mmc0_clk>; + clock-names = "ahb", "mmc"; + resets = <&ahb1_rst 8>; + reset-names = "ahb"; + interrupts = <0 60 4>; + status = "disabled"; + }; + + mmc1: mmc@01c10000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c10000 0x1000>; + clocks = <&ahb1_gates 9>, <&mmc1_clk>; + clock-names = "ahb", "mmc"; + resets = <&ahb1_rst 9>; + reset-names = "ahb"; + interrupts = <0 61 4>; + status = "disabled"; + }; + + mmc2: mmc@01c11000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c11000 0x1000>; + clocks = <&ahb1_gates 10>, <&mmc2_clk>; + clock-names = "ahb", "mmc"; + resets = <&ahb1_rst 10>; + reset-names = "ahb"; + interrupts = <0 62 4>; + status = "disabled"; + }; + + mmc3: mmc@01c12000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c12000 0x1000>; + clocks = <&ahb1_gates 11>, <&mmc3_clk>; + clock-names = "ahb", "mmc"; + resets = <&ahb1_rst 11>; + reset-names = "ahb"; + interrupts = <0 63 4>; + status = "disabled"; + }; + + usbphy: phy@01c19400 { + compatible = "allwinner,sun6i-a31-usb-phy"; + reg = <0x01c19400 0x10>, + <0x01c1a800 0x4>, + <0x01c1b800 0x4>; + reg-names = "phy_ctrl", + "pmu1", + "pmu2"; + clocks = <&usb_clk 8>, + <&usb_clk 9>, + <&usb_clk 10>; + clock-names = "usb0_phy", + "usb1_phy", + "usb2_phy"; + resets = <&usb_clk 0>, + <&usb_clk 1>, + <&usb_clk 2>; + reset-names = "usb0_reset", + "usb1_reset", + "usb2_reset"; + status = "disabled"; + #phy-cells = <1>; + }; + + ehci0: usb@01c1a000 { + compatible = "allwinner,sun6i-a31-ehci", "generic-ehci"; + reg = <0x01c1a000 0x100>; + interrupts = <0 72 4>; + clocks = <&ahb1_gates 26>; + resets = <&ahb1_rst 26>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci0: usb@01c1a400 { + compatible = "allwinner,sun6i-a31-ohci", "generic-ohci"; + reg = <0x01c1a400 0x100>; + interrupts = <0 73 4>; + clocks = <&ahb1_gates 29>, <&usb_clk 16>; + resets = <&ahb1_rst 29>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + ehci1: usb@01c1b000 { + compatible = "allwinner,sun6i-a31-ehci", "generic-ehci"; + reg = <0x01c1b000 0x100>; + interrupts = <0 74 4>; + clocks = <&ahb1_gates 27>; + resets = <&ahb1_rst 27>; + phys = <&usbphy 2>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci1: usb@01c1b400 { + compatible = "allwinner,sun6i-a31-ohci", "generic-ohci"; + reg = <0x01c1b400 0x100>; + interrupts = <0 75 4>; + clocks = <&ahb1_gates 30>, <&usb_clk 17>; + resets = <&ahb1_rst 30>; + phys = <&usbphy 2>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci2: usb@01c1c400 { + compatible = "allwinner,sun6i-a31-ohci", "generic-ohci"; + reg = <0x01c1c400 0x100>; + interrupts = <0 77 4>; + clocks = <&ahb1_gates 31>, <&usb_clk 18>; + resets = <&ahb1_rst 31>; + status = "disabled"; }; pio: pinctrl@01c20800 { @@ -286,6 +460,13 @@ allwinner,drive = <0>; allwinner,pull = <0>; }; + + mmc0_pins_a: mmc0@0 { + allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5"; + allwinner,function = "mmc0"; + allwinner,drive = <2>; + allwinner,pull = <0>; + }; }; ahb1_rst: reset@01c202c0 { @@ -330,6 +511,8 @@ reg-io-width = <4>; clocks = <&apb2_gates 16>; resets = <&apb2_rst 16>; + dmas = <&dma 6>, <&dma 6>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -341,6 +524,8 @@ reg-io-width = <4>; clocks = <&apb2_gates 17>; resets = <&apb2_rst 17>; + dmas = <&dma 7>, <&dma 7>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -352,6 +537,8 @@ reg-io-width = <4>; clocks = <&apb2_gates 18>; resets = <&apb2_rst 18>; + dmas = <&dma 8>, <&dma 8>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -363,6 +550,8 @@ reg-io-width = <4>; clocks = <&apb2_gates 19>; resets = <&apb2_rst 19>; + dmas = <&dma 9>, <&dma 9>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -374,6 +563,8 @@ reg-io-width = <4>; clocks = <&apb2_gates 20>; resets = <&apb2_rst 20>; + dmas = <&dma 10>, <&dma 10>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -385,6 +576,8 @@ reg-io-width = <4>; clocks = <&apb2_gates 21>; resets = <&apb2_rst 21>; + dmas = <&dma 22>, <&dma 22>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -428,12 +621,25 @@ status = "disabled"; }; + timer@01c60000 { + compatible = "allwinner,sun6i-a31-hstimer", "allwinner,sun7i-a20-hstimer"; + reg = <0x01c60000 0x1000>; + interrupts = <0 51 4>, + <0 52 4>, + <0 53 4>, + <0 54 4>; + clocks = <&ahb1_gates 19>; + resets = <&ahb1_rst 19>; + }; + spi0: spi@01c68000 { compatible = "allwinner,sun6i-a31-spi"; reg = <0x01c68000 0x1000>; interrupts = <0 65 4>; clocks = <&ahb1_gates 20>, <&spi0_clk>; clock-names = "ahb", "mod"; + dmas = <&dma 23>, <&dma 23>; + dma-names = "rx", "tx"; resets = <&ahb1_rst 20>; status = "disabled"; }; @@ -444,6 +650,8 @@ interrupts = <0 66 4>; clocks = <&ahb1_gates 21>, <&spi1_clk>; clock-names = "ahb", "mod"; + dmas = <&dma 24>, <&dma 24>; + dma-names = "rx", "tx"; resets = <&ahb1_rst 21>; status = "disabled"; }; @@ -454,6 +662,8 @@ interrupts = <0 67 4>; clocks = <&ahb1_gates 22>, <&spi2_clk>; clock-names = "ahb", "mod"; + dmas = <&dma 25>, <&dma 25>; + dma-names = "rx", "tx"; resets = <&ahb1_rst 22>; status = "disabled"; }; @@ -464,6 +674,8 @@ interrupts = <0 68 4>; clocks = <&ahb1_gates 23>, <&spi3_clk>; clock-names = "ahb", "mod"; + dmas = <&dma 26>, <&dma 26>; + dma-names = "rx", "tx"; resets = <&ahb1_rst 23>; status = "disabled"; }; @@ -479,14 +691,74 @@ interrupts = <1 9 0xf04>; }; + nmi_intc: interrupt-controller@01f00c0c { + compatible = "allwinner,sun6i-a31-sc-nmi"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x01f00c0c 0x38>; + interrupts = <0 32 4>; + }; + + prcm@01f01400 { + compatible = "allwinner,sun6i-a31-prcm"; + reg = <0x01f01400 0x200>; + + ar100: ar100_clk { + compatible = "allwinner,sun6i-a31-ar100-clk"; + #clock-cells = <0>; + clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>; + clock-output-names = "ar100"; + }; + + ahb0: ahb0_clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + clocks = <&ar100>; + clock-output-names = "ahb0"; + }; + + apb0: apb0_clk { + compatible = "allwinner,sun6i-a31-apb0-clk"; + #clock-cells = <0>; + clocks = <&ahb0>; + clock-output-names = "apb0"; + }; + + apb0_gates: apb0_gates_clk { + compatible = "allwinner,sun6i-a31-apb0-gates-clk"; + #clock-cells = <1>; + clocks = <&apb0>; + clock-output-names = "apb0_pio", "apb0_ir", + "apb0_timer", "apb0_p2wi", + "apb0_uart", "apb0_1wire", + "apb0_i2c"; + }; + + apb0_rst: apb0_rst { + compatible = "allwinner,sun6i-a31-clock-reset"; + #reset-cells = <1>; + }; + }; + cpucfg@01f01c00 { compatible = "allwinner,sun6i-a31-cpuconfig"; reg = <0x01f01c00 0x300>; }; - prcm@01f01c00 { - compatible = "allwinner,sun6i-a31-prcm"; - reg = <0x01f01400 0x200>; + r_pio: pinctrl@01f02c00 { + compatible = "allwinner,sun6i-a31-r-pinctrl"; + reg = <0x01f02c00 0x400>; + interrupts = <0 45 4>, + <0 46 4>; + clocks = <&apb0_gates 0>; + resets = <&apb0_rst 0>; + gpio-controller; + interrupt-controller; + #address-cells = <1>; + #size-cells = <0>; + #gpio-cells = <3>; }; }; }; diff --git a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts index 68de89ffbdfa..a5ad945197e8 100644 --- a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts +++ b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts @@ -20,6 +20,16 @@ compatible = "cubietech,cubieboard2", "allwinner,sun7i-a20"; soc@01c00000 { + mmc0: mmc@01c0f000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 1 0>; /* PH1 */ + cd-inverted; + status = "okay"; + }; + usbphy: phy@01c13400 { usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>; diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts index cb25d3c8da58..b87fea901489 100644 --- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts +++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts @@ -20,6 +20,25 @@ compatible = "cubietech,cubietruck", "allwinner,sun7i-a20"; soc@01c00000 { + mmc0: mmc@01c0f000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 1 0>; /* PH1 */ + cd-inverted; + status = "okay"; + }; + + mmc3: mmc@01c12000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc3_pins_a>; + vmmc-supply = <®_vmmc3>; + bus-width = <4>; + non-removable; + status = "okay"; + }; + usbphy: phy@01c13400 { usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>; @@ -48,6 +67,18 @@ }; pinctrl@01c20800 { + mmc3_pins_a: mmc3@0 { + /* AP6210 requires pull-up */ + allwinner,pull = <1>; + }; + + vmmc3_pin_cubietruck: vmmc3_pin@0 { + allwinner,pins = "PH9"; + allwinner,function = "gpio_out"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + ahci_pwr_pin_cubietruck: ahci_pwr_pin@1 { allwinner,pins = "PH12"; allwinner,function = "gpio_out"; @@ -63,6 +94,12 @@ }; }; + pwm: pwm@01c20e00 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pins_a>, <&pwm1_pins_a>; + status = "okay"; + }; + uart0: serial@01c28000 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_a>; @@ -139,4 +176,15 @@ reg_usb2_vbus: usb2-vbus { status = "okay"; }; + + reg_vmmc3: vmmc3 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&vmmc3_pin_cubietruck>; + regulator-name = "vmmc3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&pio 7 9 0>; + }; }; diff --git a/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts b/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts new file mode 100644 index 000000000000..b77308e90199 --- /dev/null +++ b/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts @@ -0,0 +1,176 @@ +/* + * Copyright 2014 Hans de Goede <hdegoede@redhat.com> + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "sun7i-a20.dtsi" +/include/ "sunxi-common-regulators.dtsi" + +/ { + model = "I12 / Q5 / QT840A A20 tvbox"; + compatible = "allwinner,i12-tvbox", "allwinner,sun7i-a20"; + + soc@01c00000 { + mmc0: mmc@01c0f000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 1 0>; /* PH1 */ + cd-inverted; + status = "okay"; + }; + + mmc3: mmc@01c12000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc3_pins_a>; + vmmc-supply = <®_vmmc3>; + bus-width = <4>; + non-removable; + status = "okay"; + }; + + usbphy: phy@01c13400 { + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; + }; + + ehci0: usb@01c14000 { + status = "okay"; + }; + + ohci0: usb@01c14400 { + status = "okay"; + }; + + ehci1: usb@01c1c000 { + status = "okay"; + }; + + ohci1: usb@01c1c400 { + status = "okay"; + }; + + pinctrl@01c20800 { + mmc3_pins_a: mmc3@0 { + /* AP6210 / AP6330 requires pull-up */ + allwinner,pull = <1>; + }; + + vmmc3_pin_i12_tvbox: vmmc3_pin@0 { + allwinner,pins = "PH2"; + allwinner,function = "gpio_out"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + vmmc3_io_pin_i12_tvbox: vmmc3_io_pin@0 { + allwinner,pins = "PH12"; + allwinner,function = "gpio_out"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + gmac_power_pin_i12_tvbox: gmac_power_pin@0 { + allwinner,pins = "PH21"; + allwinner,function = "gpio_out"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + led_pins_i12_tvbox: led_pins@0 { + allwinner,pins = "PH9", "PH20"; + allwinner,function = "gpio_out"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + }; + + uart0: serial@01c28000 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; + }; + + gmac: ethernet@01c50000 { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_pins_mii_a>; + phy = <&phy1>; + phy-mode = "mii"; + phy-supply = <®_gmac_3v3>; + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins_i12_tvbox>; + + red { + label = "i12_tvbox:red:usr"; + gpios = <&pio 7 9 1>; + }; + + blue { + label = "i12_tvbox:blue:usr"; + gpios = <&pio 7 20 0>; + }; + }; + + reg_usb1_vbus: usb1-vbus { + status = "okay"; + }; + + reg_usb2_vbus: usb2-vbus { + status = "okay"; + }; + + reg_vmmc3: vmmc3 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&vmmc3_pin_i12_tvbox>; + regulator-name = "vmmc3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&pio 7 2 0>; + }; + + reg_vmmc3_io: vmmc3-io { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&vmmc3_io_pin_i12_tvbox>; + regulator-name = "vmmc3-io"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + /* This controls VCC-PI, must be always on! */ + regulator-always-on; + enable-active-high; + gpio = <&pio 7 12 0>; + }; + + reg_gmac_3v3: gmac-3v3 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac_power_pin_i12_tvbox>; + regulator-name = "gmac-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <50000>; + enable-active-high; + gpio = <&pio 7 21 0>; + }; +}; diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts index eeadf76362fa..b759630bc9a9 100644 --- a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts +++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts @@ -31,6 +31,26 @@ status = "okay"; }; + mmc0: mmc@01c0f000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 1 0>; /* PH1 */ + cd-inverted; + status = "okay"; + }; + + mmc3: mmc@01c12000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc3_pins_a>, <&mmc3_cd_pin_olinuxinom>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 11 0>; /* PH11 */ + cd-inverted; + status = "okay"; + }; + usbphy: phy@01c13400 { usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>; @@ -65,6 +85,13 @@ }; pinctrl@01c20800 { + mmc3_cd_pin_olinuxinom: mmc3_cd_pin@0 { + allwinner,pins = "PH11"; + allwinner,function = "gpio_in"; + allwinner,drive = <0>; + allwinner,pull = <1>; + }; + led_pins_olinuxino: led_pins@0 { allwinner,pins = "PH2"; allwinner,function = "gpio_out"; diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index aba1c8a3f388..01e94664232a 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -57,6 +57,12 @@ <1 10 0xf08>; }; + pmu { + compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu"; + interrupts = <0 120 4>, + <0 121 4>; + }; + clocks { #address-cells = <1>; #size-cells = <1>; @@ -455,6 +461,42 @@ #size-cells = <0>; }; + mmc0: mmc@01c0f000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c0f000 0x1000>; + clocks = <&ahb_gates 8>, <&mmc0_clk>; + clock-names = "ahb", "mmc"; + interrupts = <0 32 4>; + status = "disabled"; + }; + + mmc1: mmc@01c10000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c10000 0x1000>; + clocks = <&ahb_gates 9>, <&mmc1_clk>; + clock-names = "ahb", "mmc"; + interrupts = <0 33 4>; + status = "disabled"; + }; + + mmc2: mmc@01c11000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c11000 0x1000>; + clocks = <&ahb_gates 10>, <&mmc2_clk>; + clock-names = "ahb", "mmc"; + interrupts = <0 34 4>; + status = "disabled"; + }; + + mmc3: mmc@01c12000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c12000 0x1000>; + clocks = <&ahb_gates 11>, <&mmc3_clk>; + clock-names = "ahb", "mmc"; + interrupts = <0 35 4>; + status = "disabled"; + }; + usbphy: phy@01c13400 { #phy-cells = <1>; compatible = "allwinner,sun7i-a20-usb-phy"; @@ -548,6 +590,20 @@ #size-cells = <0>; #gpio-cells = <3>; + pwm0_pins_a: pwm0@0 { + allwinner,pins = "PB2"; + allwinner,function = "pwm"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + pwm1_pins_a: pwm1@0 { + allwinner,pins = "PI3"; + allwinner,function = "pwm"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + uart0_pins_a: uart0@0 { allwinner,pins = "PB22", "PB23"; allwinner,function = "uart0"; @@ -661,6 +717,27 @@ allwinner,drive = <0>; allwinner,pull = <0>; }; + + mmc0_pins_a: mmc0@0 { + allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5"; + allwinner,function = "mmc0"; + allwinner,drive = <2>; + allwinner,pull = <0>; + }; + + mmc0_cd_pin_reference_design: mmc0_cd_pin@0 { + allwinner,pins = "PH1"; + allwinner,function = "gpio_in"; + allwinner,drive = <0>; + allwinner,pull = <1>; + }; + + mmc3_pins_a: mmc3@0 { + allwinner,pins = "PI4","PI5","PI6","PI7","PI8","PI9"; + allwinner,function = "mmc3"; + allwinner,drive = <2>; + allwinner,pull = <0>; + }; }; timer@01c20c00 { @@ -686,6 +763,14 @@ interrupts = <0 24 4>; }; + pwm: pwm@01c20e00 { + compatible = "allwinner,sun7i-a20-pwm"; + reg = <0x01c20e00 0xc>; + clocks = <&osc24M>; + #pwm-cells = <3>; + status = "disabled"; + }; + sid: eeprom@01c23800 { compatible = "allwinner,sun7i-a20-sid"; reg = <0x01c23800 0x200>; @@ -778,48 +863,58 @@ }; i2c0: i2c@01c2ac00 { - compatible = "allwinner,sun4i-i2c"; + compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; reg = <0x01c2ac00 0x400>; interrupts = <0 7 4>; clocks = <&apb1_gates 0>; clock-frequency = <100000>; status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; }; i2c1: i2c@01c2b000 { - compatible = "allwinner,sun4i-i2c"; + compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; reg = <0x01c2b000 0x400>; interrupts = <0 8 4>; clocks = <&apb1_gates 1>; clock-frequency = <100000>; status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; }; i2c2: i2c@01c2b400 { - compatible = "allwinner,sun4i-i2c"; + compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; reg = <0x01c2b400 0x400>; interrupts = <0 9 4>; clocks = <&apb1_gates 2>; clock-frequency = <100000>; status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; }; i2c3: i2c@01c2b800 { - compatible = "allwinner,sun4i-i2c"; + compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; reg = <0x01c2b800 0x400>; interrupts = <0 88 4>; clocks = <&apb1_gates 3>; clock-frequency = <100000>; status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; }; i2c4: i2c@01c2c000 { - compatible = "allwinner,sun4i-i2c"; + compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c"; reg = <0x01c2c000 0x400>; interrupts = <0 89 4>; clocks = <&apb1_gates 15>; clock-frequency = <100000>; status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; }; gmac: ethernet@01c50000 { diff --git a/arch/arm/boot/dts/sunxi-common-regulators.dtsi b/arch/arm/boot/dts/sunxi-common-regulators.dtsi index 18eeac0670b9..3d021efd1a38 100644 --- a/arch/arm/boot/dts/sunxi-common-regulators.dtsi +++ b/arch/arm/boot/dts/sunxi-common-regulators.dtsi @@ -72,4 +72,18 @@ gpio = <&pio 7 3 0>; status = "disabled"; }; + + reg_vcc3v0: vcc3v0 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + reg_vcc3v3: vcc3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; }; diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts index a288a12823ed..5c21d216515a 100644 --- a/arch/arm/boot/dts/tegra114-dalmore.dts +++ b/arch/arm/boot/dts/tegra114-dalmore.dts @@ -25,6 +25,7 @@ hdmi@54280000 { status = "okay"; + hdmi-supply = <&vdd_5v0_hdmi>; vdd-supply = <&vdd_hdmi_reg>; pll-supply = <&palmas_smps3_reg>; @@ -36,6 +37,8 @@ dsi@54300000 { status = "okay"; + avdd-dsi-csi-supply = <&avdd_1v2_reg>; + panel@0 { compatible = "panasonic,vvx10f004b00", "simple-panel"; @@ -982,12 +985,10 @@ regulator-max-microvolt = <2800000>; }; - ldo3 { + avdd_1v2_reg: ldo3 { regulator-name = "avdd-dsi-csi"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; }; ldo4 { @@ -1105,6 +1106,7 @@ sdhci@78000400 { cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_HIGH>; bus-width = <4>; status = "okay"; }; @@ -1231,8 +1233,6 @@ regulator-name = "vdd_hdmi_5v0"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; vin-supply = <&tps65090_dcdc1_reg>; }; @@ -1245,6 +1245,17 @@ enable-active-high; gpio = <&palmas_gpio 6 0>; }; + + vdd_5v0_hdmi: regulator@7 { + compatible = "regulator-fixed"; + reg = <7>; + regulator-name = "VDD_5V0_HDMI_CON"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&tps65090_dcdc1_reg>; + }; }; sound { diff --git a/arch/arm/boot/dts/tegra114-roth.dts b/arch/arm/boot/dts/tegra114-roth.dts new file mode 100644 index 000000000000..0b0e8e07d965 --- /dev/null +++ b/arch/arm/boot/dts/tegra114-roth.dts @@ -0,0 +1,1113 @@ +/dts-v1/; + +#include <dt-bindings/input/input.h> +#include "tegra114.dtsi" + +/ { + model = "NVIDIA SHIELD"; + compatible = "nvidia,roth", "nvidia,tegra114"; + + chosen { + /* SHIELD's bootloader's arguments need to be overridden */ + bootargs = "console=ttyS0,115200n8 console=tty1 gpt fbcon=rotate:1"; + /* SHIELD's bootloader will place initrd at this address */ + linux,initrd-start = <0x82000000>; + linux,initrd-end = <0x82800000>; + }; + + firmware { + trusted-foundations { + compatible = "tlm,trusted-foundations"; + tlm,version-major = <2>; + tlm,version-minor = <8>; + }; + }; + + memory { + /* memory >= 0x79600000 is reserved for firmware usage */ + reg = <0x80000000 0x79600000>; + }; + + pinmux@70000868 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + clk1_out_pw4 { + nvidia,pins = "clk1_out_pw4"; + nvidia,function = "extperiph1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + dap1_din_pn1 { + nvidia,pins = "dap1_din_pn1"; + nvidia,function = "i2s0"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dap1_dout_pn2 { + nvidia,pins = "dap1_dout_pn2", + "dap1_fs_pn0", + "dap1_sclk_pn3"; + nvidia,function = "i2s0"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dap2_din_pa4 { + nvidia,pins = "dap2_din_pa4"; + nvidia,function = "i2s1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dap2_dout_pa5 { + nvidia,pins = "dap2_dout_pa5", + "dap2_fs_pa2", + "dap2_sclk_pa3"; + nvidia,function = "i2s1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dap4_din_pp5 { + nvidia,pins = "dap4_din_pp5", + "dap4_dout_pp6", + "dap4_fs_pp4", + "dap4_sclk_pp7"; + nvidia,function = "i2s3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dvfs_pwm_px0 { + nvidia,pins = "dvfs_pwm_px0", + "dvfs_clk_px2"; + nvidia,function = "cldvfs"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + ulpi_clk_py0 { + nvidia,pins = "ulpi_clk_py0", + "ulpi_data0_po1", + "ulpi_data1_po2", + "ulpi_data2_po3", + "ulpi_data3_po4", + "ulpi_data4_po5", + "ulpi_data5_po6", + "ulpi_data6_po7", + "ulpi_data7_po0"; + nvidia,function = "ulpi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + ulpi_dir_py1 { + nvidia,pins = "ulpi_dir_py1", + "ulpi_nxt_py2"; + nvidia,function = "ulpi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + ulpi_stp_py3 { + nvidia,pins = "ulpi_stp_py3"; + nvidia,function = "ulpi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + cam_i2c_scl_pbb1 { + nvidia,pins = "cam_i2c_scl_pbb1", + "cam_i2c_sda_pbb2"; + nvidia,function = "i2c3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,lock = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + cam_mclk_pcc0 { + nvidia,pins = "cam_mclk_pcc0", + "pbb0"; + nvidia,function = "vi_alt3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,lock = <TEGRA_PIN_DISABLE>; + }; + pbb4 { + nvidia,pins = "pbb4"; + nvidia,function = "vgp4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,lock = <TEGRA_PIN_DISABLE>; + }; + gen2_i2c_scl_pt5 { + nvidia,pins = "gen2_i2c_scl_pt5", + "gen2_i2c_sda_pt6"; + nvidia,function = "i2c2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,lock = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + gmi_a16_pj7 { + nvidia,pins = "gmi_a16_pj7", + "gmi_a19_pk7"; + nvidia,function = "uartd"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi_a17_pb0 { + nvidia,pins = "gmi_a17_pb0", + "gmi_a18_pb1"; + nvidia,function = "uartd"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gmi_ad5_pg5 { + nvidia,pins = "gmi_ad5_pg5", + "gmi_wr_n_pi0"; + nvidia,function = "spi4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gmi_ad6_pg6 { + nvidia,pins = "gmi_ad6_pg6", + "gmi_ad7_pg7"; + nvidia,function = "spi4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gmi_ad12_ph4 { + nvidia,pins = "gmi_ad12_ph4"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi_cs6_n_pi13 { + nvidia,pins = "gmi_cs6_n_pi3"; + nvidia,function = "nand"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi_ad9_ph1 { + nvidia,pins = "gmi_ad9_ph1"; + nvidia,function = "pwm1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi_cs1_n_pj2 { + nvidia,pins = "gmi_cs1_n_pj2", + "gmi_oe_n_pi1"; + nvidia,function = "soc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gmi_rst_n_pi4 { + nvidia,pins = "gmi_rst_n_pi4"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gmi_iordy_pi5 { + nvidia,pins = "gmi_iordy_pi5"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + clk2_out_pw5 { + nvidia,pins = "clk2_out_pw5"; + nvidia,function = "extperiph2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc1_clk_pz0 { + nvidia,pins = "sdmmc1_clk_pz0"; + nvidia,function = "sdmmc1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + sdmmc1_cmd_pz1 { + nvidia,pins = "sdmmc1_cmd_pz1", + "sdmmc1_dat0_py7", + "sdmmc1_dat1_py6", + "sdmmc1_dat2_py5", + "sdmmc1_dat3_py4"; + nvidia,function = "sdmmc1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc3_clk_pa6 { + nvidia,pins = "sdmmc3_clk_pa6"; + nvidia,function = "sdmmc3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + sdmmc3_cmd_pa7 { + nvidia,pins = "sdmmc3_cmd_pa7", + "sdmmc3_dat0_pb7", + "sdmmc3_dat1_pb6", + "sdmmc3_dat2_pb5", + "sdmmc3_dat3_pb4", + "sdmmc3_cd_n_pv2", + "sdmmc3_clk_lb_out_pee4", + "sdmmc3_clk_lb_in_pee5"; + nvidia,function = "sdmmc3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + kb_col4_pq4 { + nvidia,pins = "kb_col4_pq4"; + nvidia,function = "sdmmc3"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc4_clk_pcc4 { + nvidia,pins = "sdmmc4_clk_pcc4"; + nvidia,function = "sdmmc4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + sdmmc4_cmd_pt7 { + nvidia,pins = "sdmmc4_cmd_pt7", + "sdmmc4_dat0_paa0", + "sdmmc4_dat1_paa1", + "sdmmc4_dat2_paa2", + "sdmmc4_dat3_paa3", + "sdmmc4_dat4_paa4", + "sdmmc4_dat5_paa5", + "sdmmc4_dat6_paa6", + "sdmmc4_dat7_paa7"; + nvidia,function = "sdmmc4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + clk_32k_out_pa0 { + nvidia,pins = "clk_32k_out_pa0"; + nvidia,function = "blink"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + kb_col0_pq0 { + nvidia,pins = "kb_col0_pq0", + "kb_col1_pq1", + "kb_col2_pq2", + "kb_row0_pr0", + "kb_row1_pr1", + "kb_row2_pr2", + "kb_row8_ps0"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + kb_row7_pr7 { + nvidia,pins = "kb_row7_pr7"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + kb_row10_ps2 { + nvidia,pins = "kb_row10_ps2"; + nvidia,function = "uarta"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + kb_row9_ps1 { + nvidia,pins = "kb_row9_ps1"; + nvidia,function = "uarta"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pwr_i2c_scl_pz6 { + nvidia,pins = "pwr_i2c_scl_pz6", + "pwr_i2c_sda_pz7"; + nvidia,function = "i2cpwr"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,lock = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + sys_clk_req_pz5 { + nvidia,pins = "sys_clk_req_pz5"; + nvidia,function = "sysclk"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + core_pwr_req { + nvidia,pins = "core_pwr_req"; + nvidia,function = "pwron"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + cpu_pwr_req { + nvidia,pins = "cpu_pwr_req"; + nvidia,function = "cpu"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pwr_int_n { + nvidia,pins = "pwr_int_n"; + nvidia,function = "pmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + reset_out_n { + nvidia,pins = "reset_out_n"; + nvidia,function = "reset_out_n"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + clk3_out_pee0 { + nvidia,pins = "clk3_out_pee0"; + nvidia,function = "extperiph3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gen1_i2c_scl_pc4 { + nvidia,pins = "gen1_i2c_scl_pc4", + "gen1_i2c_sda_pc5"; + nvidia,function = "i2c1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,lock = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + uart2_cts_n_pj5 { + nvidia,pins = "uart2_cts_n_pj5"; + nvidia,function = "uartb"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + uart2_rts_n_pj6 { + nvidia,pins = "uart2_rts_n_pj6"; + nvidia,function = "uartb"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + uart2_rxd_pc3 { + nvidia,pins = "uart2_rxd_pc3"; + nvidia,function = "irda"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + uart2_txd_pc2 { + nvidia,pins = "uart2_txd_pc2"; + nvidia,function = "irda"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + uart3_cts_n_pa1 { + nvidia,pins = "uart3_cts_n_pa1", + "uart3_rxd_pw7"; + nvidia,function = "uartc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + uart3_rts_n_pc0 { + nvidia,pins = "uart3_rts_n_pc0", + "uart3_txd_pw6"; + nvidia,function = "uartc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + owr { + nvidia,pins = "owr"; + nvidia,function = "owr"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + hdmi_cec_pee3 { + nvidia,pins = "hdmi_cec_pee3"; + nvidia,function = "cec"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,lock = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + ddc_scl_pv4 { + nvidia,pins = "ddc_scl_pv4", + "ddc_sda_pv5"; + nvidia,function = "i2c4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,lock = <TEGRA_PIN_DISABLE>; + nvidia,rcv-sel = <TEGRA_PIN_ENABLE>; + }; + spdif_in_pk6 { + nvidia,pins = "spdif_in_pk6"; + nvidia,function = "usb"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,lock = <TEGRA_PIN_DISABLE>; + }; + usb_vbus_en0_pn4 { + nvidia,pins = "usb_vbus_en0_pn4"; + nvidia,function = "usb"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,lock = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + }; + gpio_x6_aud_px6 { + nvidia,pins = "gpio_x6_aud_px6"; + nvidia,function = "spi6"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gpio_x1_aud_px1 { + nvidia,pins = "gpio_x1_aud_px1"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gpio_x7_aud_px7 { + nvidia,pins = "gpio_x7_aud_px7"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gmi_adv_n_pk0 { + nvidia,pins = "gmi_adv_n_pk0"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gmi_cs0_n_pj0 { + nvidia,pins = "gmi_cs0_n_pj0"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pu3 { + nvidia,pins = "pu3"; + nvidia,function = "pwm0"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gpio_x4_aud_px4 { + nvidia,pins = "gpio_x4_aud_px4", + "gpio_x5_aud_px5"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gpio_x3_aud_px3 { + nvidia,pins = "gpio_x3_aud_px3"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gpio_w2_aud_pw2 { + nvidia,pins = "gpio_w2_aud_pw2"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gpio_w3_aud_pw3 { + nvidia,pins = "gpio_w3_aud_pw3"; + nvidia,function = "spi6"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dap3_fs_pp0 { + nvidia,pins = "dap3_fs_pp0", + "dap3_din_pp1", + "dap3_dout_pp2", + "dap3_sclk_pp3"; + nvidia,function = "i2s2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pv0 { + nvidia,pins = "pv0"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pv1 { + nvidia,pins = "pv1"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pbb3 { + nvidia,pins = "pbb3", + "pbb5", + "pbb6", + "pbb7"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pcc1 { + nvidia,pins = "pcc1", + "pcc2"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gmi_ad0_pg0 { + nvidia,pins = "gmi_ad0_pg0", + "gmi_ad1_pg1"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi_ad10_ph2 { + nvidia,pins = "gmi_ad10_ph2", + "gmi_ad12_ph4", + "gmi_ad15_ph7", + "gmi_cs3_n_pk4"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi_ad11_ph3 { + nvidia,pins = "gmi_ad11_ph3", + "gmi_ad13_ph5", + "gmi_ad8_ph0", + "gmi_clk_pk1", + "gmi_cs2_n_pk3"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi_ad14_ph6 { + nvidia,pins = "gmi_ad14_ph6", + "gmi_cs0_n_pj0", + "gmi_cs4_n_pk2", + "gmi_cs7_n_pi6", + "gmi_dqs_p_pj3", + "gmi_wp_n_pc7"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gmi_ad2_pg2 { + nvidia,pins = "gmi_ad2_pg2", + "gmi_ad3_pg3"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc1_wp_n_pv3 { + nvidia,pins = "sdmmc1_wp_n_pv3"; + nvidia,function = "spi4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + clk2_req_pcc5 { + nvidia,pins = "clk2_req_pcc5"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + kb_col3_pq3 { + nvidia,pins = "kb_col3_pq3"; + nvidia,function = "pwm2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + kb_col5_pq5 { + nvidia,pins = "kb_col5_pq5"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + kb_col6_pq6 { + nvidia,pins = "kb_col6_pq6", + "kb_col7_pq7"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + kb_row3_pr3 { + nvidia,pins = "kb_row3_pr3", + "kb_row4_pr4", + "kb_row6_pr6"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + clk3_req_pee1 { + nvidia,pins = "clk3_req_pee1"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pu2 { + nvidia,pins = "pu2"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + hdmi_int_pn7 { + nvidia,pins = "hdmi_int_pn7"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + drive_sdio1 { + nvidia,pins = "drive_sdio1"; + nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; + nvidia,schmitt = <TEGRA_PIN_DISABLE>; + nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; + nvidia,pull-down-strength = <36>; + nvidia,pull-up-strength = <20>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOW>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOW>; + }; + drive_sdio3 { + nvidia,pins = "drive_sdio3"; + nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; + nvidia,schmitt = <TEGRA_PIN_DISABLE>; + nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; + nvidia,pull-down-strength = <36>; + nvidia,pull-up-strength = <20>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; + }; + drive_gma { + nvidia,pins = "drive_gma"; + nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; + nvidia,schmitt = <TEGRA_PIN_DISABLE>; + nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; + nvidia,pull-down-strength = <2>; + nvidia,pull-up-strength = <2>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; + nvidia,drive-type = <1>; + }; + }; + }; + + /* Usable on reworked devices only */ + serial@70006300 { + status = "okay"; + }; + + pwm@7000a000 { + status = "okay"; + }; + + i2c@7000d000 { + status = "okay"; + clock-frequency = <400000>; + + regulator@43 { + compatible = "ti,tps51632"; + reg = <0x43>; + regulator-name = "vdd-cpu"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1520000>; + regulator-always-on; + regulator-boot-on; + }; + + palmas: pmic@58 { + compatible = "ti,palmas"; + reg = <0x58>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; + + #interrupt-cells = <2>; + interrupt-controller; + + ti,system-power-controller; + + palmas_gpio: gpio { + compatible = "ti,palmas-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + + pmic { + compatible = "ti,tps65913-pmic", "ti,palmas-pmic"; + + regulators { + smps12 { + regulator-name = "vdd-ddr"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_1v8: smps3 { + regulator-name = "vdd-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + smps457 { + regulator-name = "vdd-soc"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + }; + + smps8 { + regulator-name = "avdd-pll-1v05"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-always-on; + regulator-boot-on; + }; + + smps9 { + regulator-name = "vdd-2v85-emmc"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + smps10_out1 { + regulator-name = "vdd-fan"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + smps10_out2 { + regulator-name = "vdd-5v0-sys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo2 { + regulator-name = "vdd-2v8-display"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-boot-on; + }; + + ldo3 { + regulator-name = "avdd-1v2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo4 { + regulator-name = "vpp-fuse"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo5 { + regulator-name = "avdd-hdmi-pll"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + ldo6 { + regulator-name = "vdd-sensor-2v8"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + ldo8 { + regulator-name = "vdd-rtc"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-boot-on; + ti,enable-ldo8-tracking; + }; + + vddio_sdmmc3: ldo9 { + regulator-name = "vddio-sdmmc3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + ldousb { + regulator-name = "avdd-usb-hdmi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_3v3_sys: regen1 { + regulator-name = "rail-3v3"; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + regen2 { + regulator-name = "rail-5v0"; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + }; + }; + + rtc { + compatible = "ti,palmas-rtc"; + interrupt-parent = <&palmas>; + interrupts = <8 0>; + }; + + }; + }; + + pmc@7000e400 { + nvidia,invert-interrupt; + }; + + /* SD card */ + sdhci@78000400 { + status = "okay"; + bus-width = <4>; + vmmc-supply = <&vddio_sdmmc3>; + cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; + power-gpios = <&gpio TEGRA_GPIO(H, 0) GPIO_ACTIVE_HIGH>; + }; + + /* eMMC */ + sdhci@78000600 { + status = "okay"; + bus-width = <8>; + vmmc-supply = <&vdd_1v8>; + non-removable; + }; + + /* External USB port (must be powered) */ + usb@7d000000 { + status = "okay"; + }; + + usb-phy@7d000000 { + status = "okay"; + nvidia,xcvr-setup = <7>; + nvidia,xcvr-lsfslew = <2>; + nvidia,xcvr-lsrslew = <2>; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + /* Should be changed to "otg" once we have vbus_supply */ + /* As of now, USB devices need to be powered externally */ + dr_mode = "host"; + }; + + /* SHIELD controller */ + usb@7d008000 { + status = "okay"; + }; + + usb-phy@7d008000 { + status = "okay"; + nvidia,xcvr-setup = <7>; + nvidia,xcvr-lsfslew = <2>; + nvidia,xcvr-lsrslew = <2>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm 1 40000>; + + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + + power-supply = <&lcd_bl_en>; + enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; + }; + + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + clk32k_in: clock { + compatible = "fixed-clock"; + reg=<0>; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + back { + label = "Back"; + gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_LOW>; + linux,code = <KEY_BACK>; + }; + + home { + label = "Home"; + gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>; + linux,code = <KEY_HOME>; + }; + + power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; + linux,code = <KEY_POWER>; + gpio-key,wakeup; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + lcd_bl_en: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "lcd_bl_en"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + }; + + regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "vdd_lcd_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vdd_1v8>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>; + regulator-boot-on; + }; + + regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "vdd_1v8_ts"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio TEGRA_GPIO(K, 3) GPIO_ACTIVE_LOW>; + regulator-boot-on; + }; + + regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "vdd_3v3_ts"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(H, 5) GPIO_ACTIVE_HIGH>; + regulator-boot-on; + }; + + regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + regulator-name = "vdd_1v8_com"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vdd_1v8>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(X, 1) GPIO_ACTIVE_HIGH>; + regulator-boot-on; + }; + + regulator@5 { + compatible = "regulator-fixed"; + reg = <5>; + regulator-name = "vdd_3v3_com"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vdd_3v3_sys>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_HIGH>; + regulator-always-on; + regulator-boot-on; + }; + }; +}; diff --git a/arch/arm/boot/dts/tegra114-tn7.dts b/arch/arm/boot/dts/tegra114-tn7.dts new file mode 100644 index 000000000000..963662145635 --- /dev/null +++ b/arch/arm/boot/dts/tegra114-tn7.dts @@ -0,0 +1,348 @@ +/dts-v1/; + +#include <dt-bindings/input/input.h> +#include "tegra114.dtsi" + +/ { + model = "Tegra Note 7"; + compatible = "nvidia,tn7", "nvidia,tegra114"; + + chosen { + /* TN7's bootloader's arguments need to be overridden */ + bootargs = "console=ttyS0,115200n8 console=tty1 gpt fbcon=rotate:2"; + /* TN7's bootloader will place initrd at this address */ + linux,initrd-start = <0x82000000>; + linux,initrd-end = <0x82800000>; + }; + + firmware { + trusted-foundations { + compatible = "tlm,trusted-foundations"; + tlm,version-major = <2>; + tlm,version-minor = <8>; + }; + }; + + memory { + /* memory >= 0x37e00000 is reserved for firmware usage */ + reg = <0x80000000 0x37e00000>; + }; + + host1x@50000000 { + dsi@54300000 { + status = "okay"; + + vdd-supply = <&vdd_1v2_ap>; + + panel@0 { + compatible = "lg,ld070wx3-sl01"; + reg = <0>; + + power-supply = <&vdd_lcd>; + backlight = <&backlight>; + }; + }; + }; + + serial@70006300 { + status = "okay"; + }; + + pwm@7000a000 { + status = "okay"; + }; + + i2c@7000d000 { + status = "okay"; + clock-frequency = <400000>; + + palmas: pmic@58 { + compatible = "ti,palmas"; + reg = <0x58>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; + + #interrupt-cells = <2>; + interrupt-controller; + + ti,system-power-controller; + + palmas_gpio: gpio { + compatible = "ti,palmas-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + + pmic { + compatible = "ti,tps65913-pmic", "ti,palmas-pmic"; + + ldoln-in-supply = <&vdd_smps10_out2>; + + regulators { + smps123 { + regulator-name = "vd-cpu"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + }; + + smps45 { + regulator-name = "vd-soc"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-boot-on; + }; + + smps6 { + regulator-name = "va-lcd-hv"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + }; + + smps7 { + regulator-name = "vd-ddr"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_1v8: smps8 { + regulator-name = "vs-pmu-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_2v9_sys: smps9 { + regulator-name = "vs-sys-2v9"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_smps10_out1: smps10_out1 { + regulator-name = "vd-smps10-out1"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_smps10_out2: smps10_out2 { + regulator-name = "vd-smps10-out2"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo1 { + regulator-name = "va-pllx"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_1v2_ap: ldo2 { + regulator-name = "va-ap-1v2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo3 { + regulator-name = "vd-fuse"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo4 { + regulator-name = "vd-ts-hv"; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3200000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo5 { + regulator-name = "va-cam2-hv"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; + + ldo6 { + regulator-name = "va-sns-hv"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + ldo7 { + regulator-name = "va-cam1-hv"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; + + ldo8 { + regulator-name = "va-ap-rtc"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + ti,enable-ldo8-tracking; + regulator-always-on; + regulator-boot-on; + }; + + ldo9 { + regulator-name = "vi-sdcard"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + }; + + ldousb { + regulator-name = "avdd-usb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + ldoln { + regulator-name = "va-hdmi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; + + rtc { + compatible = "ti,palmas-rtc"; + interrupt-parent = <&palmas>; + interrupts = <8 0>; + }; + + }; + }; + + pmc@7000e400 { + nvidia,invert-interrupt; + }; + + /* eMMC */ + sdhci@78000600 { + status = "okay"; + bus-width = <8>; + vmmc-supply = <&vdd_1v8>; + non-removable; + }; + + usb@7d000000 { + status = "okay"; + }; + + usb-phy@7d000000 { + status = "okay"; + nvidia,xcvr-setup = <7>; + nvidia,xcvr-lsfslew = <2>; + nvidia,xcvr-lsrslew = <2>; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + /* Should be changed to "otg" once we have vbus_supply */ + /* As of now, USB devices need to be powered externally */ + dr_mode = "host"; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm 1 40000>; + + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + + power-supply = <&lcd_bl_en>; + }; + + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + clk32k_in: clock { + compatible = "fixed-clock"; + reg = <0>; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; + linux,code = <KEY_POWER>; + gpio-key,wakeup; + }; + + volume_down { + label = "Volume Down"; + gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEDOWN>; + }; + + volume_up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEUP>; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + /* FIXME: output of BQ24192 */ + vs_sys: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "VS_SYS"; + regulator-min-microvolt = <4200000>; + regulator-max-microvolt = <4200000>; + regulator-always-on; + regulator-boot-on; + }; + + lcd_bl_en: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "VDD_LCD_BL"; + regulator-min-microvolt = <16500000>; + regulator-max-microvolt = <16500000>; + gpio = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vs_sys>; + regulator-boot-on; + }; + + vdd_lcd: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "VD_LCD_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&palmas_gpio 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_1v8>; + regulator-boot-on; + }; + }; +}; diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts new file mode 100644 index 000000000000..e31fb61a81d3 --- /dev/null +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts @@ -0,0 +1,1827 @@ +/dts-v1/; + +#include <dt-bindings/input/input.h> +#include "tegra124.dtsi" + +/ { + model = "NVIDIA Tegra124 Jetson TK1"; + compatible = "nvidia,jetson-tk1", "nvidia,tegra124"; + + aliases { + rtc0 = "/i2c@0,7000d000/pmic@40"; + rtc1 = "/rtc@0,7000e000"; + }; + + memory { + reg = <0x0 0x80000000 0x0 0x80000000>; + }; + + host1x@0,50000000 { + hdmi@0,54280000 { + status = "okay"; + + hdmi-supply = <&vdd_5v0_hdmi>; + pll-supply = <&vdd_hdmi_pll>; + vdd-supply = <&vdd_3v3_hdmi>; + + nvidia,ddc-i2c-bus = <&hdmi_ddc>; + nvidia,hpd-gpio = + <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; + }; + }; + + pinmux: pinmux@0,70000868 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + clk_32k_out_pa0 { + nvidia,pins = "clk_32k_out_pa0"; + nvidia,function = "soc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + uart3_cts_n_pa1 { + nvidia,pins = "uart3_cts_n_pa1"; + nvidia,function = "uartc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dap2_fs_pa2 { + nvidia,pins = "dap2_fs_pa2"; + nvidia,function = "i2s1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dap2_sclk_pa3 { + nvidia,pins = "dap2_sclk_pa3"; + nvidia,function = "i2s1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dap2_din_pa4 { + nvidia,pins = "dap2_din_pa4"; + nvidia,function = "i2s1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dap2_dout_pa5 { + nvidia,pins = "dap2_dout_pa5"; + nvidia,function = "i2s1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc3_clk_pa6 { + nvidia,pins = "sdmmc3_clk_pa6"; + nvidia,function = "sdmmc3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + sdmmc3_cmd_pa7 { + nvidia,pins = "sdmmc3_cmd_pa7"; + nvidia,function = "sdmmc3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pb0 { + nvidia,pins = "pb0"; + nvidia,function = "uartd"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pb1 { + nvidia,pins = "pb1"; + nvidia,function = "uartd"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc3_dat3_pb4 { + nvidia,pins = "sdmmc3_dat3_pb4"; + nvidia,function = "sdmmc3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc3_dat2_pb5 { + nvidia,pins = "sdmmc3_dat2_pb5"; + nvidia,function = "sdmmc3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc3_dat1_pb6 { + nvidia,pins = "sdmmc3_dat1_pb6"; + nvidia,function = "sdmmc3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc3_dat0_pb7 { + nvidia,pins = "sdmmc3_dat0_pb7"; + nvidia,function = "sdmmc3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + uart3_rts_n_pc0 { + nvidia,pins = "uart3_rts_n_pc0"; + nvidia,function = "uartc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + uart2_txd_pc2 { + nvidia,pins = "uart2_txd_pc2"; + nvidia,function = "irda"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + uart2_rxd_pc3 { + nvidia,pins = "uart2_rxd_pc3"; + nvidia,function = "irda"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gen1_i2c_scl_pc4 { + nvidia,pins = "gen1_i2c_scl_pc4"; + nvidia,function = "i2c1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + }; + gen1_i2c_sda_pc5 { + nvidia,pins = "gen1_i2c_sda_pc5"; + nvidia,function = "i2c1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + }; + pc7 { + nvidia,pins = "pc7"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pg0 { + nvidia,pins = "pg0"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pg1 { + nvidia,pins = "pg1"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pg2 { + nvidia,pins = "pg2"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pg3 { + nvidia,pins = "pg3"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pg4 { + nvidia,pins = "pg4"; + nvidia,function = "spi4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pg5 { + nvidia,pins = "pg5"; + nvidia,function = "spi4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pg6 { + nvidia,pins = "pg6"; + nvidia,function = "spi4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pg7 { + nvidia,pins = "pg7"; + nvidia,function = "spi4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + ph0 { + nvidia,pins = "ph0"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + ph1 { + nvidia,pins = "ph1"; + nvidia,function = "pwm1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + ph2 { + nvidia,pins = "ph2"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + ph3 { + nvidia,pins = "ph3"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + ph4 { + nvidia,pins = "ph4"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + ph5 { + nvidia,pins = "ph5"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + ph6 { + nvidia,pins = "ph6"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + ph7 { + nvidia,pins = "ph7"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pi0 { + nvidia,pins = "pi0"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pi1 { + nvidia,pins = "pi1"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pi2 { + nvidia,pins = "pi2"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pi3 { + nvidia,pins = "pi3"; + nvidia,function = "spi4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pi4 { + nvidia,pins = "pi4"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pi5 { + nvidia,pins = "pi5"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pi6 { + nvidia,pins = "pi6"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pi7 { + nvidia,pins = "pi7"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pj0 { + nvidia,pins = "pj0"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pj2 { + nvidia,pins = "pj2"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + uart2_cts_n_pj5 { + nvidia,pins = "uart2_cts_n_pj5"; + nvidia,function = "uartb"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + uart2_rts_n_pj6 { + nvidia,pins = "uart2_rts_n_pj6"; + nvidia,function = "uartb"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pj7 { + nvidia,pins = "pj7"; + nvidia,function = "uartd"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pk0 { + nvidia,pins = "pk0"; + nvidia,function = "soc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pk1 { + nvidia,pins = "pk1"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pk2 { + nvidia,pins = "pk2"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pk3 { + nvidia,pins = "pk3"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pk4 { + nvidia,pins = "pk4"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + spdif_out_pk5 { + nvidia,pins = "spdif_out_pk5"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + spdif_in_pk6 { + nvidia,pins = "spdif_in_pk6"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pk7 { + nvidia,pins = "pk7"; + nvidia,function = "uartd"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + dap1_fs_pn0 { + nvidia,pins = "dap1_fs_pn0"; + nvidia,function = "i2s0"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dap1_din_pn1 { + nvidia,pins = "dap1_din_pn1"; + nvidia,function = "i2s0"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dap1_dout_pn2 { + nvidia,pins = "dap1_dout_pn2"; + nvidia,function = "sata"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + dap1_sclk_pn3 { + nvidia,pins = "dap1_sclk_pn3"; + nvidia,function = "i2s0"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + usb_vbus_en0_pn4 { + nvidia,pins = "usb_vbus_en0_pn4"; + nvidia,function = "usb"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + }; + usb_vbus_en1_pn5 { + nvidia,pins = "usb_vbus_en1_pn5"; + nvidia,function = "usb"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + }; + hdmi_int_pn7 { + nvidia,pins = "hdmi_int_pn7"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,rcv-sel = <TEGRA_PIN_DISABLE>; + }; + ulpi_data7_po0 { + nvidia,pins = "ulpi_data7_po0"; + nvidia,function = "ulpi"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + ulpi_data0_po1 { + nvidia,pins = "ulpi_data0_po1"; + nvidia,function = "ulpi"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + ulpi_data1_po2 { + nvidia,pins = "ulpi_data1_po2"; + nvidia,function = "ulpi"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + ulpi_data2_po3 { + nvidia,pins = "ulpi_data2_po3"; + nvidia,function = "ulpi"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + ulpi_data3_po4 { + nvidia,pins = "ulpi_data3_po4"; + nvidia,function = "ulpi"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + ulpi_data4_po5 { + nvidia,pins = "ulpi_data4_po5"; + nvidia,function = "ulpi"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + ulpi_data5_po6 { + nvidia,pins = "ulpi_data5_po6"; + nvidia,function = "ulpi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + ulpi_data6_po7 { + nvidia,pins = "ulpi_data6_po7"; + nvidia,function = "ulpi"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dap3_fs_pp0 { + nvidia,pins = "dap3_fs_pp0"; + nvidia,function = "i2s2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + dap3_din_pp1 { + nvidia,pins = "dap3_din_pp1"; + nvidia,function = "i2s2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + dap3_dout_pp2 { + nvidia,pins = "dap3_dout_pp2"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + dap3_sclk_pp3 { + nvidia,pins = "dap3_sclk_pp3"; + nvidia,function = "rsvd3"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + dap4_fs_pp4 { + nvidia,pins = "dap4_fs_pp4"; + nvidia,function = "i2s3"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dap4_din_pp5 { + nvidia,pins = "dap4_din_pp5"; + nvidia,function = "i2s3"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dap4_dout_pp6 { + nvidia,pins = "dap4_dout_pp6"; + nvidia,function = "i2s3"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dap4_sclk_pp7 { + nvidia,pins = "dap4_sclk_pp7"; + nvidia,function = "i2s3"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + kb_col0_pq0 { + nvidia,pins = "kb_col0_pq0"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + kb_col1_pq1 { + nvidia,pins = "kb_col1_pq1"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + kb_col2_pq2 { + nvidia,pins = "kb_col2_pq2"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + kb_col3_pq3 { + nvidia,pins = "kb_col3_pq3"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + kb_col4_pq4 { + nvidia,pins = "kb_col4_pq4"; + nvidia,function = "sdmmc3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + kb_col5_pq5 { + nvidia,pins = "kb_col5_pq5"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + kb_col6_pq6 { + nvidia,pins = "kb_col6_pq6"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + kb_col7_pq7 { + nvidia,pins = "kb_col7_pq7"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + kb_row0_pr0 { + nvidia,pins = "kb_row0_pr0"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + kb_row1_pr1 { + nvidia,pins = "kb_row1_pr1"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + kb_row2_pr2 { + nvidia,pins = "kb_row2_pr2"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + kb_row3_pr3 { + nvidia,pins = "kb_row3_pr3"; + nvidia,function = "sys"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + kb_row4_pr4 { + nvidia,pins = "kb_row4_pr4"; + nvidia,function = "rsvd3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + kb_row5_pr5 { + nvidia,pins = "kb_row5_pr5"; + nvidia,function = "rsvd3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + kb_row6_pr6 { + nvidia,pins = "kb_row6_pr6"; + nvidia,function = "displaya_alt"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + kb_row7_pr7 { + nvidia,pins = "kb_row7_pr7"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + kb_row8_ps0 { + nvidia,pins = "kb_row8_ps0"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + kb_row9_ps1 { + nvidia,pins = "kb_row9_ps1"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + kb_row10_ps2 { + nvidia,pins = "kb_row10_ps2"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + kb_row11_ps3 { + nvidia,pins = "kb_row11_ps3"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + kb_row12_ps4 { + nvidia,pins = "kb_row12_ps4"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + kb_row13_ps5 { + nvidia,pins = "kb_row13_ps5"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + kb_row14_ps6 { + nvidia,pins = "kb_row14_ps6"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + kb_row15_ps7 { + nvidia,pins = "kb_row15_ps7"; + nvidia,function = "soc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + kb_row16_pt0 { + nvidia,pins = "kb_row16_pt0"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + kb_row17_pt1 { + nvidia,pins = "kb_row17_pt1"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gen2_i2c_scl_pt5 { + nvidia,pins = "gen2_i2c_scl_pt5"; + nvidia,function = "i2c2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + }; + gen2_i2c_sda_pt6 { + nvidia,pins = "gen2_i2c_sda_pt6"; + nvidia,function = "i2c2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + }; + sdmmc4_cmd_pt7 { + nvidia,pins = "sdmmc4_cmd_pt7"; + nvidia,function = "sdmmc4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pu0 { + nvidia,pins = "pu0"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pu1 { + nvidia,pins = "pu1"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pu2 { + nvidia,pins = "pu2"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pu3 { + nvidia,pins = "pu3"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pu4 { + nvidia,pins = "pu4"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pu5 { + nvidia,pins = "pu5"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pu6 { + nvidia,pins = "pu6"; + nvidia,function = "rsvd3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pv0 { + nvidia,pins = "pv0"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pv1 { + nvidia,pins = "pv1"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc3_cd_n_pv2 { + nvidia,pins = "sdmmc3_cd_n_pv2"; + nvidia,function = "sdmmc3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc1_wp_n_pv3 { + nvidia,pins = "sdmmc1_wp_n_pv3"; + nvidia,function = "sdmmc1"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + ddc_scl_pv4 { + nvidia,pins = "ddc_scl_pv4"; + nvidia,function = "i2c4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,rcv-sel = <TEGRA_PIN_DISABLE>; + }; + ddc_sda_pv5 { + nvidia,pins = "ddc_sda_pv5"; + nvidia,function = "i2c4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,rcv-sel = <TEGRA_PIN_DISABLE>; + }; + gpio_w2_aud_pw2 { + nvidia,pins = "gpio_w2_aud_pw2"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gpio_w3_aud_pw3 { + nvidia,pins = "gpio_w3_aud_pw3"; + nvidia,function = "spi6"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dap_mclk1_pw4 { + nvidia,pins = "dap_mclk1_pw4"; + nvidia,function = "extperiph1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + clk2_out_pw5 { + nvidia,pins = "clk2_out_pw5"; + nvidia,function = "extperiph2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + uart3_txd_pw6 { + nvidia,pins = "uart3_txd_pw6"; + nvidia,function = "uartc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + uart3_rxd_pw7 { + nvidia,pins = "uart3_rxd_pw7"; + nvidia,function = "uartc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dvfs_pwm_px0 { + nvidia,pins = "dvfs_pwm_px0"; + nvidia,function = "cldvfs"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gpio_x1_aud_px1 { + nvidia,pins = "gpio_x1_aud_px1"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + dvfs_clk_px2 { + nvidia,pins = "dvfs_clk_px2"; + nvidia,function = "cldvfs"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gpio_x3_aud_px3 { + nvidia,pins = "gpio_x3_aud_px3"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gpio_x4_aud_px4 { + nvidia,pins = "gpio_x4_aud_px4"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gpio_x5_aud_px5 { + nvidia,pins = "gpio_x5_aud_px5"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gpio_x6_aud_px6 { + nvidia,pins = "gpio_x6_aud_px6"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gpio_x7_aud_px7 { + nvidia,pins = "gpio_x7_aud_px7"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + ulpi_clk_py0 { + nvidia,pins = "ulpi_clk_py0"; + nvidia,function = "spi1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + ulpi_dir_py1 { + nvidia,pins = "ulpi_dir_py1"; + nvidia,function = "spi1"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + ulpi_nxt_py2 { + nvidia,pins = "ulpi_nxt_py2"; + nvidia,function = "spi1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + ulpi_stp_py3 { + nvidia,pins = "ulpi_stp_py3"; + nvidia,function = "spi1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + sdmmc1_dat3_py4 { + nvidia,pins = "sdmmc1_dat3_py4"; + nvidia,function = "sdmmc1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc1_dat2_py5 { + nvidia,pins = "sdmmc1_dat2_py5"; + nvidia,function = "sdmmc1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc1_dat1_py6 { + nvidia,pins = "sdmmc1_dat1_py6"; + nvidia,function = "sdmmc1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc1_dat0_py7 { + nvidia,pins = "sdmmc1_dat0_py7"; + nvidia,function = "sdmmc1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc1_clk_pz0 { + nvidia,pins = "sdmmc1_clk_pz0"; + nvidia,function = "sdmmc1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc1_cmd_pz1 { + nvidia,pins = "sdmmc1_cmd_pz1"; + nvidia,function = "sdmmc1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pwr_i2c_scl_pz6 { + nvidia,pins = "pwr_i2c_scl_pz6"; + nvidia,function = "i2cpwr"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + }; + pwr_i2c_sda_pz7 { + nvidia,pins = "pwr_i2c_sda_pz7"; + nvidia,function = "i2cpwr"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + }; + sdmmc4_dat0_paa0 { + nvidia,pins = "sdmmc4_dat0_paa0"; + nvidia,function = "sdmmc4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc4_dat1_paa1 { + nvidia,pins = "sdmmc4_dat1_paa1"; + nvidia,function = "sdmmc4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc4_dat2_paa2 { + nvidia,pins = "sdmmc4_dat2_paa2"; + nvidia,function = "sdmmc4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc4_dat3_paa3 { + nvidia,pins = "sdmmc4_dat3_paa3"; + nvidia,function = "sdmmc4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc4_dat4_paa4 { + nvidia,pins = "sdmmc4_dat4_paa4"; + nvidia,function = "sdmmc4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc4_dat5_paa5 { + nvidia,pins = "sdmmc4_dat5_paa5"; + nvidia,function = "sdmmc4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc4_dat6_paa6 { + nvidia,pins = "sdmmc4_dat6_paa6"; + nvidia,function = "sdmmc4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc4_dat7_paa7 { + nvidia,pins = "sdmmc4_dat7_paa7"; + nvidia,function = "sdmmc4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pbb0 { + nvidia,pins = "pbb0"; + nvidia,function = "vimclk2_alt"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + cam_i2c_scl_pbb1 { + nvidia,pins = "cam_i2c_scl_pbb1"; + nvidia,function = "i2c3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + }; + cam_i2c_sda_pbb2 { + nvidia,pins = "cam_i2c_sda_pbb2"; + nvidia,function = "i2c3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + }; + pbb3 { + nvidia,pins = "pbb3"; + nvidia,function = "vgp3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pbb4 { + nvidia,pins = "pbb4"; + nvidia,function = "vgp4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pbb5 { + nvidia,pins = "pbb5"; + nvidia,function = "rsvd3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pbb6 { + nvidia,pins = "pbb6"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pbb7 { + nvidia,pins = "pbb7"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + cam_mclk_pcc0 { + nvidia,pins = "cam_mclk_pcc0"; + nvidia,function = "vi_alt3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pcc1 { + nvidia,pins = "pcc1"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pcc2 { + nvidia,pins = "pcc2"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc4_clk_pcc4 { + nvidia,pins = "sdmmc4_clk_pcc4"; + nvidia,function = "sdmmc4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + clk2_req_pcc5 { + nvidia,pins = "clk2_req_pcc5"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + clk3_out_pee0 { + nvidia,pins = "clk3_out_pee0"; + nvidia,function = "extperiph3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + clk3_req_pee1 { + nvidia,pins = "clk3_req_pee1"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + dap_mclk1_req_pee2 { + nvidia,pins = "dap_mclk1_req_pee2"; + nvidia,function = "sata"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + hdmi_cec_pee3 { + nvidia,pins = "hdmi_cec_pee3"; + nvidia,function = "cec"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + }; + sdmmc3_clk_lb_out_pee4 { + nvidia,pins = "sdmmc3_clk_lb_out_pee4"; + nvidia,function = "sdmmc3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc3_clk_lb_in_pee5 { + nvidia,pins = "sdmmc3_clk_lb_in_pee5"; + nvidia,function = "sdmmc3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dp_hpd_pff0 { + nvidia,pins = "dp_hpd_pff0"; + nvidia,function = "dp"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + usb_vbus_en2_pff1 { + nvidia,pins = "usb_vbus_en2_pff1"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + pff2 { + nvidia,pins = "pff2"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + core_pwr_req { + nvidia,pins = "core_pwr_req"; + nvidia,function = "pwron"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + cpu_pwr_req { + nvidia,pins = "cpu_pwr_req"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pwr_int_n { + nvidia,pins = "pwr_int_n"; + nvidia,function = "pmi"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + reset_out_n { + nvidia,pins = "reset_out_n"; + nvidia,function = "reset_out_n"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + owr { + nvidia,pins = "owr"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,rcv-sel = <TEGRA_PIN_DISABLE>; + }; + clk_32k_in { + nvidia,pins = "clk_32k_in"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + jtag_rtck { + nvidia,pins = "jtag_rtck"; + nvidia,function = "rtck"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + }; + }; + + /* DB9 serial port */ + serial@0,70006300 { + status = "okay"; + }; + + /* Expansion GEN1_I2C_*, mini-PCIe I2C, on-board components */ + i2c@0,7000c000 { + status = "okay"; + clock-frequency = <100000>; + + rt5639: audio-codec@1c { + compatible = "realtek,rt5639"; + reg = <0x1c>; + interrupt-parent = <&gpio>; + interrupts = <TEGRA_GPIO(H, 4) GPIO_ACTIVE_HIGH>; + realtek,ldo1-en-gpios = + <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_HIGH>; + }; + + temperature-sensor@4c { + compatible = "ti,tmp451"; + reg = <0x4c>; + interrupt-parent = <&gpio>; + interrupts = <TEGRA_GPIO(I, 6) IRQ_TYPE_LEVEL_LOW>; + }; + + eeprom@56 { + compatible = "atmel,24c02"; + reg = <0x56>; + pagesize = <8>; + }; + }; + + /* Expansion GEN2_I2C_* */ + i2c@0,7000c400 { + status = "okay"; + clock-frequency = <100000>; + }; + + /* Expansion CAM_I2C_* */ + i2c@0,7000c500 { + status = "okay"; + clock-frequency = <100000>; + }; + + /* HDMI DDC */ + hdmi_ddc: i2c@0,7000c700 { + status = "okay"; + clock-frequency = <100000>; + }; + + /* Expansion PWR_I2C_*, on-board components */ + i2c@0,7000d000 { + status = "okay"; + clock-frequency = <400000>; + + pmic: pmic@40 { + compatible = "ams,as3722"; + reg = <0x40>; + interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; + + ams,system-power-controller; + + #interrupt-cells = <2>; + interrupt-controller; + + gpio-controller; + #gpio-cells = <2>; + + pinctrl-names = "default"; + pinctrl-0 = <&as3722_default>; + + as3722_default: pinmux { + gpio0 { + pins = "gpio0"; + function = "gpio"; + bias-pull-down; + }; + + gpio1_2_4_7 { + pins = "gpio1", "gpio2", "gpio4", "gpio7"; + function = "gpio"; + bias-pull-up; + }; + + gpio3_5_6 { + pins = "gpio3", "gpio5", "gpio6"; + bias-high-impedance; + }; + }; + + regulators { + vsup-sd2-supply = <&vdd_5v0_sys>; + vsup-sd3-supply = <&vdd_5v0_sys>; + vsup-sd4-supply = <&vdd_5v0_sys>; + vsup-sd5-supply = <&vdd_5v0_sys>; + vin-ldo0-supply = <&vdd_1v35_lp0>; + vin-ldo1-6-supply = <&vdd_3v3_run>; + vin-ldo2-5-7-supply = <&vddio_1v8>; + vin-ldo3-4-supply = <&vdd_3v3_sys>; + vin-ldo9-10-supply = <&vdd_5v0_sys>; + vin-ldo11-supply = <&vdd_3v3_run>; + + sd0 { + regulator-name = "+VDD_CPU_AP"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1400000>; + regulator-min-microamp = <3500000>; + regulator-max-microamp = <3500000>; + regulator-always-on; + regulator-boot-on; + ams,external-control = <2>; + }; + + sd1 { + regulator-name = "+VDD_CORE"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + regulator-min-microamp = <2500000>; + regulator-max-microamp = <2500000>; + regulator-always-on; + regulator-boot-on; + ams,external-control = <1>; + }; + + vdd_1v35_lp0: sd2 { + regulator-name = "+1.35V_LP0(sd2)"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + sd3 { + regulator-name = "+1.35V_LP0(sd3)"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_1v05_run: sd4 { + regulator-name = "+1.05V_RUN"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + + vddio_1v8: sd5 { + regulator-name = "+1.8V_VDDIO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + sd6 { + regulator-name = "+VDD_GPU_AP"; + regulator-min-microvolt = <650000>; + regulator-max-microvolt = <1200000>; + regulator-min-microamp = <3500000>; + regulator-max-microamp = <3500000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo0 { + regulator-name = "+1.05V_RUN_AVDD"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-boot-on; + regulator-always-on; + ams,external-control = <1>; + }; + + ldo1 { + regulator-name = "+1.8V_RUN_CAM"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo2 { + regulator-name = "+1.2V_GEN_AVDD"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3 { + regulator-name = "+1.05V_LP0_VDD_RTC"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + ams,enable-tracking; + }; + + ldo4 { + regulator-name = "+2.8V_RUN_CAM"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo5 { + regulator-name = "+1.2V_RUN_CAM_FRONT"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + vddio_sdmmc3: ldo6 { + regulator-name = "+VDDIO_SDMMC3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + ldo7 { + regulator-name = "+1.05V_RUN_CAM_REAR"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + + ldo9 { + regulator-name = "+3.3V_RUN_TOUCH"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo10 { + regulator-name = "+2.8V_RUN_CAM_AF"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo11 { + regulator-name = "+1.8V_RUN_VPP_FUSE"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + }; + }; + + /* Expansion TS_SPI_* */ + spi@0,7000d400 { + status = "okay"; + }; + + /* Internal SPI */ + spi@0,7000da00 { + status = "okay"; + spi-max-frequency = <25000000>; + spi-flash@0 { + compatible = "winbond,w25q32dw"; + reg = <0>; + spi-max-frequency = <20000000>; + }; + }; + + pmc@0,7000e400 { + nvidia,invert-interrupt; + nvidia,suspend-mode = <1>; + nvidia,cpu-pwr-good-time = <500>; + nvidia,cpu-pwr-off-time = <300>; + nvidia,core-pwr-good-time = <641 3845>; + nvidia,core-pwr-off-time = <61036>; + nvidia,core-power-req-active-high; + nvidia,sys-clock-req-active-high; + }; + + /* SD card */ + sdhci@0,700b0400 { + status = "okay"; + cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; + power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; + wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_HIGH>; + bus-width = <4>; + vqmmc-supply = <&vddio_sdmmc3>; + }; + + /* eMMC */ + sdhci@0,700b0600 { + status = "okay"; + bus-width = <8>; + }; + + ahub@0,70300000 { + i2s@0,70301100 { + status = "okay"; + }; + }; + + /* mini-PCIe USB */ + usb@0,7d004000 { + status = "okay"; + }; + + usb-phy@0,7d004000 { + status = "okay"; + }; + + /* USB A connector */ + usb@0,7d008000 { + status = "okay"; + }; + + usb-phy@0,7d008000 { + status = "okay"; + vbus-supply = <&vdd_usb3_vbus>; + }; + + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + clk32k_in: clock@0 { + compatible = "fixed-clock"; + reg = <0>; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; + linux,code = <KEY_POWER>; + debounce-interval = <10>; + gpio-key,wakeup; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + vdd_mux: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "+VDD_MUX"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_5v0_sys: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "+5V_SYS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd_mux>; + }; + + vdd_3v3_sys: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "+3.3V_SYS"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd_mux>; + }; + + vdd_3v3_run: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "+3.3V_RUN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_sys>; + }; + + vdd_3v3_hdmi: regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + regulator-name = "+3.3V_AVDD_HDMI_AP_GATED"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vdd_3v3_run>; + }; + + vdd_usb1_vbus: regulator@7 { + compatible = "regulator-fixed"; + reg = <7>; + regulator-name = "+USB0_VBUS_SW"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; + enable-active-high; + gpio-open-drain; + vin-supply = <&vdd_5v0_sys>; + }; + + vdd_usb3_vbus: regulator@8 { + compatible = "regulator-fixed"; + reg = <8>; + regulator-name = "+5V_USB_HS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>; + enable-active-high; + gpio-open-drain; + vin-supply = <&vdd_5v0_sys>; + }; + + vdd_3v3_lp0: regulator@10 { + compatible = "regulator-fixed"; + reg = <10>; + regulator-name = "+3.3V_LP0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_sys>; + }; + + vdd_hdmi_pll: regulator@11 { + compatible = "regulator-fixed"; + reg = <11>; + regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>; + vin-supply = <&vdd_1v05_run>; + }; + + vdd_5v0_hdmi: regulator@12 { + compatible = "regulator-fixed"; + reg = <12>; + regulator-name = "+5V_HDMI_CON"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_sys>; + }; + }; + + sound { + compatible = "nvidia,tegra-audio-rt5640-jetson-tk1", + "nvidia,tegra-audio-rt5640"; + nvidia,model = "NVIDIA Tegra Jetson TK1"; + + nvidia,audio-routing = + "Headphones", "HPOR", + "Headphones", "HPOL", + "Mic Jack", "MICBIAS1", + "IN2P", "Mic Jack"; + + nvidia,i2s-controller = <&tegra_i2s1>; + nvidia,audio-codec = <&rt5639>; + + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_LOW>; + + clocks = <&tegra_car TEGRA124_CLK_PLL_A>, + <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA124_CLK_EXTERN1>; + clock-names = "pll_a", "pll_a_out0", "mclk"; + }; +}; diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts index c17283c04598..f0bb84244025 100644 --- a/arch/arm/boot/dts/tegra124-venice2.dts +++ b/arch/arm/boot/dts/tegra124-venice2.dts @@ -17,6 +17,18 @@ }; host1x@0,50000000 { + hdmi@0,54280000 { + status = "okay"; + + vdd-supply = <&vdd_3v3_hdmi>; + pll-supply = <&vdd_hdmi_pll>; + hdmi-supply = <&vdd_5v0_hdmi>; + + nvidia,ddc-i2c-bus = <&hdmi_ddc>; + nvidia,hpd-gpio = + <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; + }; + sor@0,54540000 { status = "okay"; @@ -601,7 +613,7 @@ clock-frequency = <100000>; }; - i2c@0,7000c700 { + hdmi_ddc: i2c@0,7000c700 { status = "okay"; clock-frequency = <100000>; }; @@ -700,7 +712,7 @@ regulator-boot-on; }; - sd4 { + vdd_1v05_run: sd4 { regulator-name = "+1.05V_RUN"; regulator-min-microvolt = <1050000>; regulator-max-microvolt = <1050000>; @@ -931,9 +943,10 @@ sdhci@0,700b0400 { cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; + wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; status = "okay"; bus-width = <4>; - vmmc-supply = <&vddio_sdmmc3>; + vqmmc-supply = <&vddio_sdmmc3>; }; sdhci@0,700b0600 { @@ -1060,6 +1073,8 @@ regulator-name = "+3.3V_RUN"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; enable-active-high; vin-supply = <&vdd_3v3_sys>; @@ -1145,6 +1160,27 @@ enable-active-high; vin-supply = <&vdd_3v3_sys>; }; + + vdd_hdmi_pll: regulator@11 { + compatible = "regulator-fixed"; + reg = <11>; + regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>; + vin-supply = <&vdd_1v05_run>; + }; + + vdd_5v0_hdmi: regulator@12 { + compatible = "regulator-fixed"; + reg = <12>; + regulator-name = "+5V_HDMI_CON"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_sys>; + }; }; sound { diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index 6d540a025148..6e6bc4e8185c 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -51,6 +51,18 @@ nvidia,head = <1>; }; + hdmi@0,54280000 { + compatible = "nvidia,tegra124-hdmi"; + reg = <0x0 0x54280000 0x0 0x00040000>; + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA124_CLK_HDMI>, + <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>; + clock-names = "hdmi", "parent"; + resets = <&tegra_car 51>; + reset-names = "hdmi"; + status = "disabled"; + }; + sor@0,54540000 { compatible = "nvidia,tegra124-sor"; reg = <0x0 0x54540000 0x0 0x00040000>; diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts index 3fb1f50f6d46..f45aad688d9b 100644 --- a/arch/arm/boot/dts/tegra20-harmony.dts +++ b/arch/arm/boot/dts/tegra20-harmony.dts @@ -28,6 +28,7 @@ hdmi@54280000 { status = "okay"; + hdmi-supply = <&vdd_5v0_hdmi>; vdd-supply = <&hdmi_vdd_reg>; pll-supply = <&hdmi_pll_reg>; @@ -724,6 +725,17 @@ gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>; enable-active-high; }; + + vdd_5v0_hdmi: regulator@6 { + compatible = "regulator-fixed"; + reg = <6>; + regulator-name = "VDDIO_HDMI"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(T, 2) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_reg>; + }; }; sound { diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts index e93fe45b7803..3189791a9289 100644 --- a/arch/arm/boot/dts/tegra30-beaver.dts +++ b/arch/arm/boot/dts/tegra30-beaver.dts @@ -40,6 +40,7 @@ hdmi@54280000 { status = "okay"; + hdmi-supply = <&vdd_5v0_hdmi>; vdd-supply = <&sys_3v3_reg>; pll-supply = <&vio_reg>; @@ -478,6 +479,17 @@ gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>; vin-supply = <&sys_3v3_reg>; }; + + vdd_5v0_hdmi: regulator@8 { + compatible = "regulator-fixed"; + reg = <8>; + regulator-name = "+VDD_5V_HDMI"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&sys_3v3_reg>; + }; }; sound { diff --git a/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts b/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts new file mode 100644 index 000000000000..7793abd5bef1 --- /dev/null +++ b/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts @@ -0,0 +1,205 @@ +/dts-v1/; + +#include "tegra30-colibri.dtsi" + +/ { + model = "Toradex Colibri T30 on Colibri Evaluation Board"; + compatible = "toradex,colibri_t30-eval-v3", "toradex,colibri_t30", "nvidia,tegra30"; + + aliases { + rtc0 = "/i2c@7000c000/rtc@68"; + rtc1 = "/i2c@7000d000/tps65911@2d"; + rtc2 = "/rtc@7000e000"; + }; + + host1x@50000000 { + dc@54200000 { + rgb { + status = "okay"; + nvidia,panel = <&panel>; + }; + }; + hdmi@54280000 { + status = "okay"; + }; + }; + + serial@70006000 { + status = "okay"; + }; + + serial@70006040 { + compatible = "nvidia,tegra30-hsuart"; + status = "okay"; + }; + + serial@70006300 { + compatible = "nvidia,tegra30-hsuart"; + status = "okay"; + }; + + pwm@7000a000 { + status = "okay"; + }; + + /* + * GEN1_I2C: I2C_SDA/SCL on SODIMM pin 194/196 (e.g. RTC on carrier + * board) + */ + i2c@7000c000 { + status = "okay"; + clock-frequency = <100000>; + + /* M41T0M6 real time clock on carrier board */ + rtc@68 { + compatible = "stm,m41t00"; + reg = <0x68>; + }; + }; + + /* DDC_CLOCK/DATA on X3 pin 15/16 (e.g. display EDID) */ + hdmiddc: i2c@7000c700 { + status = "okay"; + }; + + /* SPI1: Colibri SSP */ + spi@7000d400 { + status = "okay"; + spi-max-frequency = <25000000>; + can0: can@0 { + compatible = "microchip,mcp2515"; + reg = <0>; + clocks = <&clk16m>; + interrupt-parent = <&gpio>; + interrupts = <TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>; + spi-max-frequency = <10000000>; + }; + spidev0: spi@1 { + compatible = "spidev"; + reg = <1>; + spi-max-frequency = <25000000>; + }; + }; + + sdhci@78000200 { + status = "okay"; + bus-width = <4>; + cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>; + no-1-8-v; + }; + + /* EHCI instance 0: USB1_DP/N -> USBC_P/N */ + usb@7d000000 { + status = "okay"; + }; + + usb-phy@7d000000 { + status = "okay"; + dr_mode = "otg"; + vbus-supply = <&usbc_vbus_reg>; + }; + + /* EHCI instance 2: USB3_DP/N -> USBH_P/N */ + usb@7d008000 { + status = "okay"; + }; + + usb-phy@7d008000 { + status = "okay"; + vbus-supply = <&usbh_vbus_reg>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + + /* PWM<A> */ + pwms = <&pwm 0 5000000>; + brightness-levels = <255 128 64 32 16 8 4 0>; + default-brightness-level = <6>; + /* BL_ON */ + enable-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; + }; + + clocks { + clk16m: clk@1 { + compatible = "fixed-clock"; + reg=<1>; + #clock-cells = <0>; + clock-frequency = <16000000>; + clock-output-names = "clk16m"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>; + linux,code = <KEY_POWER>; + debounce-interval = <10>; + gpio-key,wakeup; + }; + }; + + panel: panel { + /* + * edt,et057090dhu: EDT 5.7" LCD TFT + * edt,et070080dh6: EDT 7.0" LCD TFT + */ + compatible = "edt,et057090dhu", "simple-panel"; + + backlight = <&backlight>; + }; + + pwmleds { + compatible = "pwm-leds"; + + pwmb { + label = "PWM<B>"; + pwms = <&pwm 1 19600>; + max-brightness = <255>; + }; + pwmc { + label = "PWM<C>"; + pwms = <&pwm 2 19600>; + max-brightness = <255>; + }; + pwmd { + label = "PWM<D>"; + pwms = <&pwm 3 19600>; + max-brightness = <255>; + }; + }; + + regulators { + sys_5v0_reg: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + usbc_vbus_reg: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "usbc_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&sys_5v0_reg>; + }; + + /* USBH_PEN */ + usbh_vbus_reg: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "usbh_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; + vin-supply = <&sys_5v0_reg>; + }; + }; +}; diff --git a/arch/arm/boot/dts/tegra30-colibri.dtsi b/arch/arm/boot/dts/tegra30-colibri.dtsi new file mode 100644 index 000000000000..bf16f8e65627 --- /dev/null +++ b/arch/arm/boot/dts/tegra30-colibri.dtsi @@ -0,0 +1,377 @@ +#include <dt-bindings/input/input.h> +#include "tegra30.dtsi" + +/* + * Toradex Colibri T30 Device Tree + * Compatible for Revisions 1.1B/1.1C/1.1D + */ +/ { + model = "Toradex Colibri T30"; + compatible = "toradex,colibri_t30", "nvidia,tegra30"; + + memory { + reg = <0x80000000 0x40000000>; + }; + + host1x@50000000 { + hdmi@54280000 { + vdd-supply = <&sys_3v3_reg>; + pll-supply = <&vio_reg>; + + nvidia,hpd-gpio = + <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; + nvidia,ddc-i2c-bus = <&hdmiddc>; + }; + }; + + pinmux@70000868 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + /* Colibri BL_ON */ + pv2 { + nvidia,pins = "pv2"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + + /* Colibri Backlight PWM<A> */ + sdmmc3_dat3_pb4 { + nvidia,pins = "sdmmc3_dat3_pb4"; + nvidia,function = "pwm0"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + + /* Colibri CAN_INT */ + kb_row8_ps0 { + nvidia,pins = "kb_row8_ps0"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* + * Colibri L_BIAS, LCD_M1 is muxed with LCD_DE + * todays display need DE, disable LCD_M1 + */ + lcd_m1_pw1 { + nvidia,pins = "lcd_m1_pw1"; + nvidia,function = "rsvd3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* Thermal alert, need to be disabled */ + lcd_dc1_pd2 { + nvidia,pins = "lcd_dc1_pd2"; + nvidia,function = "rsvd3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* Colibri MMC */ + kb_row10_ps2 { + nvidia,pins = "kb_row10_ps2"; + nvidia,function = "sdmmc2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + kb_row11_ps3 { + nvidia,pins = "kb_row11_ps3", + "kb_row12_ps4", + "kb_row13_ps5", + "kb_row14_ps6", + "kb_row15_ps7"; + nvidia,function = "sdmmc2"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + + /* Colibri SSP */ + ulpi_clk_py0 { + nvidia,pins = "ulpi_clk_py0", + "ulpi_dir_py1", + "ulpi_nxt_py2", + "ulpi_stp_py3"; + nvidia,function = "spi1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + sdmmc3_dat6_pd3 { + nvidia,pins = "sdmmc3_dat6_pd3", + "sdmmc3_dat7_pd4"; + nvidia,function = "spdif"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + }; + + /* Colibri UART_A */ + ulpi_data0 { + nvidia,pins = "ulpi_data0_po1", + "ulpi_data1_po2", + "ulpi_data2_po3", + "ulpi_data3_po4", + "ulpi_data4_po5", + "ulpi_data5_po6", + "ulpi_data6_po7", + "ulpi_data7_po0"; + nvidia,function = "uarta"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + + /* Colibri UART_B */ + gmi_a16_pj7 { + nvidia,pins = "gmi_a16_pj7", + "gmi_a17_pb0", + "gmi_a18_pb1", + "gmi_a19_pk7"; + nvidia,function = "uartd"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + + /* Colibri UART_C */ + uart2_rxd { + nvidia,pins = "uart2_rxd_pc3", + "uart2_txd_pc2"; + nvidia,function = "uartb"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + + /* eMMC */ + sdmmc4_clk_pcc4 { + nvidia,pins = "sdmmc4_clk_pcc4", + "sdmmc4_rst_n_pcc3"; + nvidia,function = "sdmmc4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + sdmmc4_dat0_paa0 { + nvidia,pins = "sdmmc4_dat0_paa0", + "sdmmc4_dat1_paa1", + "sdmmc4_dat2_paa2", + "sdmmc4_dat3_paa3", + "sdmmc4_dat4_paa4", + "sdmmc4_dat5_paa5", + "sdmmc4_dat6_paa6", + "sdmmc4_dat7_paa7"; + nvidia,function = "sdmmc4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + }; + }; + + hdmiddc: i2c@7000c700 { + clock-frequency = <100000>; + }; + + /* + * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and + * touch screen controller + */ + i2c@7000d000 { + status = "okay"; + clock-frequency = <100000>; + + pmic: tps65911@2d { + compatible = "ti,tps65911"; + reg = <0x2d>; + + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <2>; + interrupt-controller; + + ti,system-power-controller; + + #gpio-cells = <2>; + gpio-controller; + + vcc1-supply = <&sys_3v3_reg>; + vcc2-supply = <&sys_3v3_reg>; + vcc3-supply = <&vio_reg>; + vcc4-supply = <&sys_3v3_reg>; + vcc5-supply = <&sys_3v3_reg>; + vcc6-supply = <&vio_reg>; + vcc7-supply = <&sys_5v0_reg>; + vccio-supply = <&sys_3v3_reg>; + + regulators { + /* SW1: +V1.35_VDDIO_DDR */ + vdd1_reg: vdd1 { + regulator-name = "vddio_ddr_1v35"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + }; + + /* SW2: unused */ + + /* SW CTRL: +V1.0_VDD_CPU */ + vddctrl_reg: vddctrl { + regulator-name = "vdd_cpu,vdd_sys"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + regulator-always-on; + }; + + /* SWIO: +V1.8 */ + vio_reg: vio { + regulator-name = "vdd_1v8_gen"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + /* LDO1: unused */ + + /* + * EN_+V3.3 switching via FET: + * +V3.3_AUDIO_AVDD_S, +V3.3 and +V1.8_VDD_LAN + * see also v3_3 fixed supply + */ + ldo2_reg: ldo2 { + regulator-name = "en_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + /* LDO3: unused */ + + /* +V1.2_VDD_RTC */ + ldo4_reg: ldo4 { + regulator-name = "vdd_rtc"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + /* + * +V2.8_AVDD_VDAC: + * only required for analog RGB + */ + ldo5_reg: ldo5 { + regulator-name = "avdd_vdac"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + /* + * +V1.05_AVDD_PLLE: avdd_plle should be 1.05V + * but LDO6 can't set voltage in 50mV + * granularity + */ + ldo6_reg: ldo6 { + regulator-name = "avdd_plle"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + }; + + /* +V1.2_AVDD_PLL */ + ldo7_reg: ldo7 { + regulator-name = "avdd_pll"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + /* +V1.0_VDD_DDR_HS */ + ldo8_reg: ldo8 { + regulator-name = "vdd_ddr_hs"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + }; + }; + + /* + * LM95245 temperature sensor + * Note: OVERT_N directly connected to PMIC PWRDN + */ + temp-sensor@4c { + compatible = "national,lm95245"; + reg = <0x4c>; + }; + + /* SW: +V1.2_VDD_CORE */ + tps62362@60 { + compatible = "ti,tps62362"; + reg = <0x60>; + + regulator-name = "tps62362-vout"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1400000>; + regulator-boot-on; + regulator-always-on; + ti,vsel0-state-low; + /* VSEL1: EN_CORE_DVFS_N low for DVFS */ + ti,vsel1-state-low; + }; + }; + + pmc@7000e400 { + nvidia,invert-interrupt; + nvidia,suspend-mode = <1>; + nvidia,cpu-pwr-good-time = <5000>; + nvidia,cpu-pwr-off-time = <5000>; + nvidia,core-pwr-good-time = <3845 3845>; + nvidia,core-pwr-off-time = <0>; + nvidia,core-power-req-active-high; + nvidia,sys-clock-req-active-high; + }; + + emmc: sdhci@78000600 { + status = "okay"; + bus-width = <8>; + non-removable; + }; + + /* EHCI instance 1: USB2_DP/N -> AX88772B */ + usb@7d004000 { + status = "okay"; + }; + + usb-phy@7d004000 { + status = "okay"; + nvidia,is-wired = <1>; + }; + + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + clk32k_in: clk@0 { + compatible = "fixed-clock"; + reg=<0>; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + sys_3v3_reg: regulator@100 { + compatible = "regulator-fixed"; + reg = <100>; + regulator-name = "3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; +}; diff --git a/arch/arm/boot/dts/twl4030.dtsi b/arch/arm/boot/dts/twl4030.dtsi index 86cfc7d15ca7..36ae9160b558 100644 --- a/arch/arm/boot/dts/twl4030.dtsi +++ b/arch/arm/boot/dts/twl4030.dtsi @@ -152,4 +152,10 @@ keypad,num-rows = <8>; keypad,num-columns = <8>; }; + + twl_madc: madc { + compatible = "ti,twl4030-madc"; + interrupts = <3>; + #io-channel-cells = <1>; + }; }; diff --git a/arch/arm/boot/dts/twl4030_omap3.dtsi b/arch/arm/boot/dts/twl4030_omap3.dtsi index c353ef0a6ac7..3537ae5b2146 100644 --- a/arch/arm/boot/dts/twl4030_omap3.dtsi +++ b/arch/arm/boot/dts/twl4030_omap3.dtsi @@ -8,7 +8,7 @@ &twl { pinctrl-names = "default"; - pinctrl-0 = <&twl4030_pins>; + pinctrl-0 = <&twl4030_pins &twl4030_vpins>; }; &omap3_pmx_core { @@ -23,3 +23,20 @@ >; }; }; + +/* + * If your board is not using the I2C4 pins with twl4030, then don't include + * this file. For proper idle mode signaling with sys_clkreq and sys_off_mode + * pins we need to configure I2C4, or else use the legacy sys_nvmode1 and + * sys_nvmode2 signaling. + */ +&omap3_pmx_wkup { + twl4030_vpins: pinmux_twl4030_vpins { + pinctrl-single,pins = < + OMAP3_WKUP_IOPAD(0x2a00, PIN_INPUT | MUX_MODE0) /* i2c4_scl.i2c4_scl */ + OMAP3_WKUP_IOPAD(0x2a02, PIN_INPUT | MUX_MODE0) /* i2c4_sda.i2c4_sda */ + OMAP3_WKUP_IOPAD(0x2a06, PIN_OUTPUT | MUX_MODE0) /* sys_clkreq.sys_clkreq */ + OMAP3_WKUP_IOPAD(0x2a18, PIN_OUTPUT | MUX_MODE0) /* sys_off_mode.sys_off_mode */ + >; + }; +}; diff --git a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi index ac870fb3fa0d..756c986995a3 100644 --- a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi +++ b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi @@ -74,8 +74,24 @@ v2m_sysreg: sysreg@010000 { compatible = "arm,vexpress-sysreg"; reg = <0x010000 0x1000>; - gpio-controller; - #gpio-cells = <2>; + + v2m_led_gpios: sys_led@08 { + compatible = "arm,vexpress-sysreg,sys_led"; + gpio-controller; + #gpio-cells = <2>; + }; + + v2m_mmc_gpios: sys_mci@48 { + compatible = "arm,vexpress-sysreg,sys_mci"; + gpio-controller; + #gpio-cells = <2>; + }; + + v2m_flash_gpios: sys_flash@4c { + compatible = "arm,vexpress-sysreg,sys_flash"; + gpio-controller; + #gpio-cells = <2>; + }; }; v2m_sysctl: sysctl@020000 { @@ -113,8 +129,8 @@ compatible = "arm,pl180", "arm,primecell"; reg = <0x050000 0x1000>; interrupts = <9 10>; - cd-gpios = <&v2m_sysreg 0 0>; - wp-gpios = <&v2m_sysreg 1 0>; + cd-gpios = <&v2m_mmc_gpios 0 0>; + wp-gpios = <&v2m_mmc_gpios 1 0>; max-frequency = <12000000>; vmmc-supply = <&v2m_fixed_3v3>; clocks = <&v2m_clk24mhz>, <&smbclk>; @@ -265,6 +281,58 @@ clock-output-names = "v2m:refclk32khz"; }; + leds { + compatible = "gpio-leds"; + + user@1 { + label = "v2m:green:user1"; + gpios = <&v2m_led_gpios 0 0>; + linux,default-trigger = "heartbeat"; + }; + + user@2 { + label = "v2m:green:user2"; + gpios = <&v2m_led_gpios 1 0>; + linux,default-trigger = "mmc0"; + }; + + user@3 { + label = "v2m:green:user3"; + gpios = <&v2m_led_gpios 2 0>; + linux,default-trigger = "cpu0"; + }; + + user@4 { + label = "v2m:green:user4"; + gpios = <&v2m_led_gpios 3 0>; + linux,default-trigger = "cpu1"; + }; + + user@5 { + label = "v2m:green:user5"; + gpios = <&v2m_led_gpios 4 0>; + linux,default-trigger = "cpu2"; + }; + + user@6 { + label = "v2m:green:user6"; + gpios = <&v2m_led_gpios 5 0>; + linux,default-trigger = "cpu3"; + }; + + user@7 { + label = "v2m:green:user7"; + gpios = <&v2m_led_gpios 6 0>; + linux,default-trigger = "cpu4"; + }; + + user@8 { + label = "v2m:green:user8"; + gpios = <&v2m_led_gpios 7 0>; + linux,default-trigger = "cpu5"; + }; + }; + mcc { compatible = "arm,vexpress,config-bus"; arm,vexpress,config-bridge = <&v2m_sysreg>; diff --git a/arch/arm/boot/dts/vexpress-v2m.dtsi b/arch/arm/boot/dts/vexpress-v2m.dtsi index f1420368355b..ba856d604fb7 100644 --- a/arch/arm/boot/dts/vexpress-v2m.dtsi +++ b/arch/arm/boot/dts/vexpress-v2m.dtsi @@ -73,8 +73,24 @@ v2m_sysreg: sysreg@00000 { compatible = "arm,vexpress-sysreg"; reg = <0x00000 0x1000>; - gpio-controller; - #gpio-cells = <2>; + + v2m_led_gpios: sys_led@08 { + compatible = "arm,vexpress-sysreg,sys_led"; + gpio-controller; + #gpio-cells = <2>; + }; + + v2m_mmc_gpios: sys_mci@48 { + compatible = "arm,vexpress-sysreg,sys_mci"; + gpio-controller; + #gpio-cells = <2>; + }; + + v2m_flash_gpios: sys_flash@4c { + compatible = "arm,vexpress-sysreg,sys_flash"; + gpio-controller; + #gpio-cells = <2>; + }; }; v2m_sysctl: sysctl@01000 { @@ -112,8 +128,8 @@ compatible = "arm,pl180", "arm,primecell"; reg = <0x05000 0x1000>; interrupts = <9 10>; - cd-gpios = <&v2m_sysreg 0 0>; - wp-gpios = <&v2m_sysreg 1 0>; + cd-gpios = <&v2m_mmc_gpios 0 0>; + wp-gpios = <&v2m_mmc_gpios 1 0>; max-frequency = <12000000>; vmmc-supply = <&v2m_fixed_3v3>; clocks = <&v2m_clk24mhz>, <&smbclk>; @@ -264,6 +280,58 @@ clock-output-names = "v2m:refclk32khz"; }; + leds { + compatible = "gpio-leds"; + + user@1 { + label = "v2m:green:user1"; + gpios = <&v2m_led_gpios 0 0>; + linux,default-trigger = "heartbeat"; + }; + + user@2 { + label = "v2m:green:user2"; + gpios = <&v2m_led_gpios 1 0>; + linux,default-trigger = "mmc0"; + }; + + user@3 { + label = "v2m:green:user3"; + gpios = <&v2m_led_gpios 2 0>; + linux,default-trigger = "cpu0"; + }; + + user@4 { + label = "v2m:green:user4"; + gpios = <&v2m_led_gpios 3 0>; + linux,default-trigger = "cpu1"; + }; + + user@5 { + label = "v2m:green:user5"; + gpios = <&v2m_led_gpios 4 0>; + linux,default-trigger = "cpu2"; + }; + + user@6 { + label = "v2m:green:user6"; + gpios = <&v2m_led_gpios 5 0>; + linux,default-trigger = "cpu3"; + }; + + user@7 { + label = "v2m:green:user7"; + gpios = <&v2m_led_gpios 6 0>; + linux,default-trigger = "cpu4"; + }; + + user@8 { + label = "v2m:green:user8"; + gpios = <&v2m_led_gpios 7 0>; + linux,default-trigger = "cpu5"; + }; + }; + mcc { compatible = "arm,vexpress,config-bus"; arm,vexpress,config-bridge = <&v2m_sysreg>; diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts index 15f98cbcb75a..a25c262326dc 100644 --- a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts +++ b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts @@ -312,6 +312,7 @@ arm,vexpress-sysreg,func = <12 0>; label = "A15 Pcore"; }; + power@1 { /* Total power for the three A7 cores */ compatible = "arm,vexpress-power"; @@ -322,14 +323,14 @@ energy@0 { /* Total energy for the two A15 cores */ compatible = "arm,vexpress-energy"; - arm,vexpress-sysreg,func = <13 0>; + arm,vexpress-sysreg,func = <13 0>, <13 1>; label = "A15 Jcore"; }; energy@2 { /* Total energy for the three A7 cores */ compatible = "arm,vexpress-energy"; - arm,vexpress-sysreg,func = <13 2>; + arm,vexpress-sysreg,func = <13 2>, <13 3>; label = "A7 Jcore"; }; }; diff --git a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts index c544a5504591..d2709b73316b 100644 --- a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts +++ b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts @@ -88,6 +88,14 @@ interrupts = <1 13 0x304>; }; + timer@2c000200 { + compatible = "arm,cortex-a5-global-timer", + "arm,cortex-a9-global-timer"; + reg = <0x2c000200 0x20>; + interrupts = <1 11 0x304>; + clocks = <&oscclk0>; + }; + watchdog@2c000620 { compatible = "arm,cortex-a5-twd-wdt"; reg = <0x2c000620 0x20>; @@ -120,7 +128,7 @@ compatible = "arm,vexpress,config-bus"; arm,vexpress,config-bridge = <&v2m_sysreg>; - osc@0 { + oscclk0: osc@0 { /* CPU and internal AXI reference clock */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 0>; diff --git a/arch/arm/boot/dts/vf610-colibri.dts b/arch/arm/boot/dts/vf610-colibri.dts new file mode 100644 index 000000000000..aecc7dbc65e8 --- /dev/null +++ b/arch/arm/boot/dts/vf610-colibri.dts @@ -0,0 +1,123 @@ +/* + * Copyright 2014 Toradex AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +/dts-v1/; +#include "vf610.dtsi" + +/ { + model = "Toradex Colibri VF61 COM"; + compatible = "toradex,vf610-colibri", "fsl,vf610"; + + chosen { + bootargs = "console=ttyLP0,115200"; + }; + + memory { + reg = <0x80000000 0x10000000>; + }; + + clocks { + enet_ext { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + }; + }; + +}; + +&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1>; + bus-width = <4>; + status = "okay"; +}; + +&fec1 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + status = "okay"; +}; + +&L2 { + arm,data-latency = <2 1 2>; + arm,tag-latency = <3 2 3>; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&iomuxc { + vf610-colibri { + pinctrl_esdhc1: esdhc1grp { + fsl,fsl,pins = < + VF610_PAD_PTA24__ESDHC1_CLK 0x31ef + VF610_PAD_PTA25__ESDHC1_CMD 0x31ef + VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef + VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef + VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef + VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef + VF610_PAD_PTB20__GPIO_42 0x219d + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2 + VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 + VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 + VF610_PAD_PTC12__ENET_RMII_RXD1 0x30d1 + VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 + VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1 + VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 + VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2 + VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2 + >; + }; + + pinctrl_uart0: uart0grp { + fsl,pins = < + VF610_PAD_PTB10__UART0_TX 0x21a2 + VF610_PAD_PTB11__UART0_RX 0x21a1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + VF610_PAD_PTB4__UART1_TX 0x21a2 + VF610_PAD_PTB5__UART1_RX 0x21a1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + VF610_PAD_PTD0__UART2_TX 0x21a2 + VF610_PAD_PTD1__UART2_RX 0x21a1 + VF610_PAD_PTD2__UART2_RTS 0x21a2 + VF610_PAD_PTD3__UART2_CTS 0x21a1 + >; + }; + }; +}; diff --git a/arch/arm/boot/dts/vf610-twr.dts b/arch/arm/boot/dts/vf610-twr.dts index ded361075aab..11d733406c7e 100644 --- a/arch/arm/boot/dts/vf610-twr.dts +++ b/arch/arm/boot/dts/vf610-twr.dts @@ -113,6 +113,13 @@ }; }; +&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1>; + bus-width = <4>; + status = "okay"; +}; + &fec0 { phy-mode = "rmii"; pinctrl-names = "default"; @@ -160,6 +167,18 @@ >; }; + pinctrl_esdhc1: esdhc1grp { + fsl,fsl,pins = < + VF610_PAD_PTA24__ESDHC1_CLK 0x31ef + VF610_PAD_PTA25__ESDHC1_CMD 0x31ef + VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef + VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef + VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef + VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef + VF610_PAD_PTA7__GPIO_134 0x219d + >; + }; + pinctrl_fec0: fec0grp { fsl,pins = < VF610_PAD_PTA6__RMII_CLKIN 0x30d1 @@ -196,6 +215,17 @@ >; }; + pinctrl_pwm0: pwm0grp { + fsl,pins = < + VF610_PAD_PTB0__FTM0_CH0 0x1582 + VF610_PAD_PTB1__FTM0_CH1 0x1582 + VF610_PAD_PTB2__FTM0_CH2 0x1582 + VF610_PAD_PTB3__FTM0_CH3 0x1582 + VF610_PAD_PTB6__FTM0_CH6 0x1582 + VF610_PAD_PTB7__FTM0_CH7 0x1582 + >; + }; + pinctrl_sai2: sai2grp { fsl,pins = < VF610_PAD_PTA16__SAI2_TX_BCLK 0x02ed @@ -217,6 +247,12 @@ }; }; +&pwm0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0>; + status = "okay"; +}; + &sai2 { #sound-dai-cells = <0>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/vf610.dtsi b/arch/arm/boot/dts/vf610.dtsi index b8ce0aa7b157..6cc314e7b8fb 100644 --- a/arch/arm/boot/dts/vf610.dtsi +++ b/arch/arm/boot/dts/vf610.dtsi @@ -183,6 +183,19 @@ clock-names = "pit"; }; + pwm0: pwm@40038000 { + compatible = "fsl,vf610-ftm-pwm"; + #pwm-cells = <3>; + reg = <0x40038000 0x1000>; + clock-names = "ftm_sys", "ftm_ext", + "ftm_fix", "ftm_cnt_clk_en"; + clocks = <&clks VF610_CLK_FTM0>, + <&clks VF610_CLK_FTM0_EXT_SEL>, + <&clks VF610_CLK_FTM0_FIX_SEL>, + <&clks VF610_CLK_FTM0_EXT_FIX_EN>; + status = "disabled"; + }; + adc0: adc@4003b000 { compatible = "fsl,vf610-adc"; reg = <0x4003b000 0x1000>; @@ -347,6 +360,30 @@ status = "disabled"; }; + esdhc1: esdhc@400b2000 { + compatible = "fsl,imx53-esdhc"; + reg = <0x400b2000 0x4000>; + interrupts = <0 28 0x04>; + clocks = <&clks VF610_CLK_IPG_BUS>, + <&clks VF610_CLK_PLATFORM_BUS>, + <&clks VF610_CLK_ESDHC1>; + clock-names = "ipg", "ahb", "per"; + status = "disabled"; + }; + + ftm: ftm@400b8000 { + compatible = "fsl,ftm-timer"; + reg = <0x400b8000 0x1000 0x400b9000 0x1000>; + interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "ftm-evt", "ftm-src", + "ftm-evt-counter-en", "ftm-src-counter-en"; + clocks = <&clks VF610_CLK_FTM2>, + <&clks VF610_CLK_FTM3>, + <&clks VF610_CLK_FTM2_EXT_FIX_EN>, + <&clks VF610_CLK_FTM3_EXT_FIX_EN>; + status = "disabled"; + }; + fec0: ethernet@400d0000 { compatible = "fsl,mvf600-fec"; reg = <0x400d0000 0x1000>; diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi index c1176abc34d9..760bbc463c5b 100644 --- a/arch/arm/boot/dts/zynq-7000.dtsi +++ b/arch/arm/boot/dts/zynq-7000.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (C) 2011 Xilinx + * Copyright (C) 2011 - 2014 Xilinx * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and @@ -25,6 +25,7 @@ reg = <0>; clocks = <&clkc 3>; clock-latency = <1000>; + cpu0-supply = <®ulator_vccpint>; operating-points = < /* kHz uV */ 666667 1000000 @@ -48,6 +49,15 @@ reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >; }; + regulator_vccpint: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "VCCPINT"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + }; + amba { compatible = "simple-bus"; #address-cells = <1>; @@ -55,7 +65,7 @@ interrupt-parent = <&intc>; ranges; - i2c0: zynq-i2c@e0004000 { + i2c0: i2c@e0004000 { compatible = "cdns,i2c-r1p10"; status = "disabled"; clocks = <&clkc 38>; @@ -66,7 +76,7 @@ #size-cells = <0>; }; - i2c1: zynq-i2c@e0005000 { + i2c1: i2c@e0005000 { compatible = "cdns,i2c-r1p10"; status = "disabled"; clocks = <&clkc 39>; @@ -80,7 +90,6 @@ intc: interrupt-controller@f8f01000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; - #address-cells = <1>; interrupt-controller; reg = <0xF8F01000 0x1000>, <0xF8F00100 0x100>; @@ -95,7 +104,7 @@ cache-level = <2>; }; - uart0: uart@e0000000 { + uart0: serial@e0000000 { compatible = "xlnx,xuartps"; status = "disabled"; clocks = <&clkc 23>, <&clkc 40>; @@ -104,7 +113,7 @@ interrupts = <0 27 4>; }; - uart1: uart@e0001000 { + uart1: serial@e0001000 { compatible = "xlnx,xuartps"; status = "disabled"; clocks = <&clkc 24>, <&clkc 41>; @@ -131,7 +140,7 @@ clock-names = "pclk", "hclk", "tx_clk"; }; - sdhci0: ps7-sdhci@e0100000 { + sdhci0: sdhci@e0100000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; clock-names = "clk_xin", "clk_ahb"; @@ -141,7 +150,7 @@ reg = <0xe0100000 0x1000>; } ; - sdhci1: ps7-sdhci@e0101000 { + sdhci1: sdhci@e0101000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; clock-names = "clk_xin", "clk_ahb"; @@ -177,6 +186,11 @@ }; }; + devcfg: devcfg@f8007000 { + compatible = "xlnx,zynq-devcfg-1.0"; + reg = <0xf8007000 0x100>; + } ; + global_timer: timer@f8f00200 { compatible = "arm,cortex-a9-global-timer"; reg = <0xf8f00200 0x20>; @@ -185,26 +199,27 @@ clocks = <&clkc 4>; }; - ttc0: ttc0@f8001000 { + ttc0: timer@f8001000 { interrupt-parent = <&intc>; - interrupts = < 0 10 4 0 11 4 0 12 4 >; + interrupts = <0 10 4>, <0 11 4>, <0 12 4>; compatible = "cdns,ttc"; clocks = <&clkc 6>; reg = <0xF8001000 0x1000>; }; - ttc1: ttc1@f8002000 { + ttc1: timer@f8002000 { interrupt-parent = <&intc>; - interrupts = < 0 37 4 0 38 4 0 39 4 >; + interrupts = <0 37 4>, <0 38 4>, <0 39 4>; compatible = "cdns,ttc"; clocks = <&clkc 6>; reg = <0xF8002000 0x1000>; }; - scutimer: scutimer@f8f00600 { + + scutimer: timer@f8f00600 { interrupt-parent = <&intc>; - interrupts = < 1 13 0x301 >; + interrupts = <1 13 0x301>; compatible = "arm,cortex-a9-twd-timer"; - reg = < 0xf8f00600 0x20 >; + reg = <0xf8f00600 0x20>; clocks = <&clkc 4>; } ; }; |