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| author | Maxime Ripard <maxime.ripard@free-electrons.com> | 2014-07-03 14:01:29 +0400 |
|---|---|---|
| committer | Maxime Ripard <maxime.ripard@free-electrons.com> | 2014-07-15 16:52:12 +0400 |
| commit | 1e165a7dc2f07054736a6a16bdc2fa024f3aa2d4 (patch) | |
| tree | 6e074e8dd757aa9c5226ec6a94db0c8245fe6dc9 /arch/arm/boot | |
| parent | 7e948346000cfc300f39f1c14335b2ef364257ef (diff) | |
| download | linux-1e165a7dc2f07054736a6a16bdc2fa024f3aa2d4.tar.xz | |
ARM: at91/dt: Declare a second ram controller when relevant
The G45 and 9263 SoCs has two identical ram controller, that are defined as a
single node, with two reg cells.
The proper way to support such a case is to have two separate DT nodes.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Diffstat (limited to 'arch/arm/boot')
| -rw-r--r-- | arch/arm/boot/dts/at91sam9263.dtsi | 10 | ||||
| -rw-r--r-- | arch/arm/boot/dts/at91sam9g45.dtsi | 8 |
2 files changed, 13 insertions, 5 deletions
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi index fece8665fb63..e8ecb03772ce 100644 --- a/arch/arm/boot/dts/at91sam9263.dtsi +++ b/arch/arm/boot/dts/at91sam9263.dtsi @@ -71,10 +71,14 @@ reg = <0xfffffc00 0x100>; }; - ramc: ramc@ffffe200 { + ramc0: ramc@ffffe200 { compatible = "atmel,at91sam9260-sdramc"; - reg = <0xffffe200 0x200 - 0xffffe800 0x200>; + reg = <0xffffe200 0x200>; + }; + + ramc1: ramc@ffffe800 { + compatible = "atmel,at91sam9260-sdramc"; + reg = <0xffffe800 0x200>; }; pit: timer@fffffd30 { diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi index ace6bf197b70..6f648b85b725 100644 --- a/arch/arm/boot/dts/at91sam9g45.dtsi +++ b/arch/arm/boot/dts/at91sam9g45.dtsi @@ -75,8 +75,12 @@ ramc0: ramc@ffffe400 { compatible = "atmel,at91sam9g45-ddramc"; - reg = <0xffffe400 0x200 - 0xffffe600 0x200>; + reg = <0xffffe400 0x200>; + }; + + ramc1: ramc@ffffe600 { + compatible = "atmel,at91sam9g45-ddramc"; + reg = <0xffffe600 0x200>; }; pmc: pmc@fffffc00 { |