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authorTony Prisk <linux@prisktech.co.nz>2013-04-23 06:23:26 +0400
committerTony Prisk <linux@prisktech.co.nz>2013-05-12 12:31:13 +0400
commit55954f8522cf108e8c894130b2656516b9ae6991 (patch)
treeab834b44f2e7b1da0b5ab40f4e96d430f0c8151c /arch/arm/boot/dts/vt8500.dtsi
parent4606c48051db62db14756e1085fe0f8821a0e116 (diff)
downloadlinux-55954f8522cf108e8c894130b2656516b9ae6991.tar.xz
dts: vt8500: Update serial nodes and disable by default in SoC files
Missing aliases for uarts on vt8500, wm8505, wm8650 added. Nodes incorrectly labelled uart@.., changed to serial@... on all SoCs. Set each uarts default status = "disabled" as they generally don't exist. For each board file, we only need to enable uart0 as no other uarts are physically present on any of these boards. Signed-off-by: Tony Prisk <linux@prisktech.co.nz>
Diffstat (limited to 'arch/arm/boot/dts/vt8500.dtsi')
-rw-r--r--arch/arm/boot/dts/vt8500.dtsi19
1 files changed, 15 insertions, 4 deletions
diff --git a/arch/arm/boot/dts/vt8500.dtsi b/arch/arm/boot/dts/vt8500.dtsi
index a0b490d51519..51d0e912c8f5 100644
--- a/arch/arm/boot/dts/vt8500.dtsi
+++ b/arch/arm/boot/dts/vt8500.dtsi
@@ -21,6 +21,13 @@
};
};
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ serial3 = &uart3;
+ };
+
soc {
#address-cells = <1>;
#size-cells = <1>;
@@ -121,32 +128,36 @@
reg = <0xd8050400 0x100>;
};
- uart@d8200000 {
+ uart0: serial@d8200000 {
compatible = "via,vt8500-uart";
reg = <0xd8200000 0x1040>;
interrupts = <32>;
clocks = <&clkuart0>;
+ status = "disabled";
};
- uart@d82b0000 {
+ uart1: serial@d82b0000 {
compatible = "via,vt8500-uart";
reg = <0xd82b0000 0x1040>;
interrupts = <33>;
clocks = <&clkuart1>;
+ status = "disabled";
};
- uart@d8210000 {
+ uart2: serial@d8210000 {
compatible = "via,vt8500-uart";
reg = <0xd8210000 0x1040>;
interrupts = <47>;
clocks = <&clkuart2>;
+ status = "disabled";
};
- uart@d82c0000 {
+ uart3: serial@d82c0000 {
compatible = "via,vt8500-uart";
reg = <0xd82c0000 0x1040>;
interrupts = <50>;
clocks = <&clkuart3>;
+ status = "disabled";
};
rtc@d8100000 {