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authorKunihiko Hayashi <hayashi.kunihiko@socionext.com>2018-07-26 10:09:59 +0300
committerMasahiro Yamada <yamada.masahiro@socionext.com>2018-08-28 17:17:55 +0300
commit92fa4f4cc2cdf70a7db650c09fd6ee5598ebe52b (patch)
tree63ae0ca3499b91b8e539dc7d8a95fdea5aa812ee /arch/arm/boot/dts/uniphier-pro5.dtsi
parentdc0a2098cc2a673b9315d1ac3f577fa53dd5ea74 (diff)
downloadlinux-92fa4f4cc2cdf70a7db650c09fd6ee5598ebe52b.tar.xz
ARM: dts: uniphier: add SPI node for UniPhier 32bit SoCs
Add nodes of SPI controller for LD4, Pro4, sLD8, Pro5 and PXs2. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Diffstat (limited to 'arch/arm/boot/dts/uniphier-pro5.dtsi')
-rw-r--r--arch/arm/boot/dts/uniphier-pro5.dtsi22
1 files changed, 22 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/uniphier-pro5.dtsi b/arch/arm/boot/dts/uniphier-pro5.dtsi
index 40a84f2c0b81..e5f9faeba377 100644
--- a/arch/arm/boot/dts/uniphier-pro5.dtsi
+++ b/arch/arm/boot/dts/uniphier-pro5.dtsi
@@ -156,6 +156,28 @@
cache-level = <3>;
};
+ spi0: spi@54006000 {
+ compatible = "socionext,uniphier-scssi";
+ status = "disabled";
+ reg = <0x54006000 0x100>;
+ interrupts = <0 39 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi0>;
+ clocks = <&peri_clk 11>;
+ resets = <&peri_rst 11>;
+ };
+
+ spi1: spi@54006100 {
+ compatible = "socionext,uniphier-scssi";
+ status = "disabled";
+ reg = <0x54006100 0x100>;
+ interrupts = <0 216 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi1>;
+ clocks = <&peri_clk 11>;
+ resets = <&peri_rst 11>;
+ };
+
serial0: serial@54006800 {
compatible = "socionext,uniphier-uart";
status = "disabled";