diff options
| author | Joseph Lo <josephl@nvidia.com> | 2012-10-29 14:25:45 +0400 |
|---|---|---|
| committer | Stephen Warren <swarren@nvidia.com> | 2012-11-05 22:36:23 +0400 |
| commit | 5ab134ad09988ca8225e759a052df7a1bbd26145 (patch) | |
| tree | 11e1eb36b10a018663e4d147f76196e63840bf21 /arch/arm/boot/dts/tegra20.dtsi | |
| parent | d534b5d4a530d2d1597c3ffb9e896a3499da6172 (diff) | |
| download | linux-5ab134ad09988ca8225e759a052df7a1bbd26145.tar.xz | |
ARM: tegra: dt: add L2 cache controller
Add L2 cache controller binding into DT for Tegra.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'arch/arm/boot/dts/tegra20.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/tegra20.dtsi | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index f3a09d0d45bc..f40cfbaa7c7e 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -4,6 +4,15 @@ compatible = "nvidia,tegra20"; interrupt-parent = <&intc>; + cache-controller@50043000 { + compatible = "arm,pl310-cache"; + reg = <0x50043000 0x1000>; + arm,data-latency = <5 5 2>; + arm,tag-latency = <4 4 2>; + cache-unified; + cache-level = <2>; + }; + intc: interrupt-controller { compatible = "arm,cortex-a9-gic"; reg = <0x50041000 0x1000 |