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authorJoseph Lo <josephl@nvidia.com>2013-10-08 11:47:40 +0400
committerStephen Warren <swarren@nvidia.com>2013-12-17 01:09:17 +0400
commit3b86baf296eb2791eeeacd2ed07f7d2789784d24 (patch)
tree6aa1c25344527a9b0d3519c48fdadf31141c8e02 /arch/arm/boot/dts/tegra124.dtsi
parent578990537aa553a3194420e63d467fcb12d42ba4 (diff)
downloadlinux-3b86baf296eb2791eeeacd2ed07f7d2789784d24.tar.xz
ARM: tegra: add clock properties for devices of Tegra124
This patch adds clock properties for devices in the DT for basic support of Tegra124 SoC. Signed-off-by: Joseph Lo <josephl@nvidia.com> [swarren, added missing unit address to "clock" node] Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'arch/arm/boot/dts/tegra124.dtsi')
-rw-r--r--arch/arm/boot/dts/tegra124.dtsi16
1 files changed, 16 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi
index b7413004ee77..936579b806d4 100644
--- a/arch/arm/boot/dts/tegra124.dtsi
+++ b/arch/arm/boot/dts/tegra124.dtsi
@@ -1,3 +1,4 @@
+#include <dt-bindings/clock/tegra124-car.h>
#include <dt-bindings/gpio/tegra-gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -28,6 +29,13 @@
<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA124_CLK_TIMER>;
+ };
+
+ tegra_car: clock@60006000 {
+ compatible = "nvidia,tegra124-car";
+ reg = <0x60006000 0x1000>;
+ #clock-cells = <1>;
};
gpio: gpio@6000d000 {
@@ -60,6 +68,7 @@
reg = <0x70006000 0x40>;
reg-shift = <2>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA124_CLK_UARTA>;
status = "disabled";
};
@@ -68,6 +77,7 @@
reg = <0x70006040 0x40>;
reg-shift = <2>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA124_CLK_UARTB>;
status = "disabled";
};
@@ -76,6 +86,7 @@
reg = <0x70006200 0x40>;
reg-shift = <2>;
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA124_CLK_UARTC>;
status = "disabled";
};
@@ -84,6 +95,7 @@
reg = <0x70006300 0x40>;
reg-shift = <2>;
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA124_CLK_UARTD>;
status = "disabled";
};
@@ -92,6 +104,7 @@
reg = <0x70006400 0x40>;
reg-shift = <2>;
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA124_CLK_UARTE>;
status = "disabled";
};
@@ -99,11 +112,14 @@
compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc";
reg = <0x7000e000 0x100>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA124_CLK_RTC>;
};
pmc@7000e400 {
compatible = "nvidia,tegra124-pmc";
reg = <0x7000e400 0x400>;
+ clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>;
+ clock-names = "pclk", "clk32k_in";
};
cpus {