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| author | Jesse Taube <mr.bossman075@gmail.com> | 2022-03-17 19:23:42 +0300 |
|---|---|---|
| committer | Jernej Skrabec <jernej.skrabec@gmail.com> | 2022-04-06 23:26:21 +0300 |
| commit | 1aba2af585fc594f08e2a90e37d7f943b6d68730 (patch) | |
| tree | 2a0d09d6056c44ace35541378c9a6e61d29b3fac /arch/arm/boot/dts/suniv-f1c100s.dtsi | |
| parent | fb2dcdd7c44652add88ac518c67b208e5133a7a9 (diff) | |
| download | linux-1aba2af585fc594f08e2a90e37d7f943b6d68730.tar.xz | |
ARM: dts: suniv: F1C100: add clock and reset macros
Include clock and reset macros and replace magic numbers.
Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20220317162349.739636-6-andre.przywara@arm.com
Diffstat (limited to 'arch/arm/boot/dts/suniv-f1c100s.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/suniv-f1c100s.dtsi | 17 |
1 files changed, 10 insertions, 7 deletions
diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi index def830101448..922efd5e9457 100644 --- a/arch/arm/boot/dts/suniv-f1c100s.dtsi +++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi @@ -4,6 +4,9 @@ * Copyright 2018 Mesih Kilinc <mesihkilinc@gmail.com> */ +#include <dt-bindings/clock/suniv-ccu-f1c100s.h> +#include <dt-bindings/reset/suniv-ccu-f1c100s.h> + / { #address-cells = <1>; #size-cells = <1>; @@ -82,7 +85,7 @@ compatible = "allwinner,suniv-f1c100s-pinctrl"; reg = <0x01c20800 0x400>; interrupts = <38>, <39>, <40>; - clocks = <&ccu 37>, <&osc24M>, <&osc32k>; + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>; clock-names = "apb", "hosc", "losc"; gpio-controller; interrupt-controller; @@ -116,8 +119,8 @@ interrupts = <1>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&ccu 38>; - resets = <&ccu 24>; + clocks = <&ccu CLK_BUS_UART0>; + resets = <&ccu RST_BUS_UART0>; status = "disabled"; }; @@ -127,8 +130,8 @@ interrupts = <2>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&ccu 39>; - resets = <&ccu 25>; + clocks = <&ccu CLK_BUS_UART1>; + resets = <&ccu RST_BUS_UART1>; status = "disabled"; }; @@ -138,8 +141,8 @@ interrupts = <3>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&ccu 40>; - resets = <&ccu 26>; + clocks = <&ccu CLK_BUS_UART2>; + resets = <&ccu RST_BUS_UART2>; status = "disabled"; }; }; |