diff options
| author | Evgeny Boger <boger@wirenboard.com> | 2021-11-22 13:46:16 +0300 |
|---|---|---|
| committer | Marc Kleine-Budde <mkl@pengutronix.de> | 2021-12-08 12:12:59 +0300 |
| commit | 671f852c1bee9bd7138a5c4ad2c88d379cd0a6cb (patch) | |
| tree | 67153070cd8f67348f769724dbd696d4845d193a /arch/arm/boot/dts/sun8i-r40.dtsi | |
| parent | 2c2fd0e68d9e1832d7661f434ee7ddd77bf1b985 (diff) | |
| download | linux-671f852c1bee9bd7138a5c4ad2c88d379cd0a6cb.tar.xz | |
ARM: dts: sun8i: r40: add node for CAN controller
Allwinner R40 (also known as A40i, T3, V40) has a CAN controller. The
controller is the same as in earlier A10 and A20 SoCs, but needs reset
line to be deasserted before use.
This patch adds a CAN node and the corresponding pinctrl descriptions.
Link: https://lore.kernel.org/all/20211122104616.537156-4-boger@wirenboard.com
Signed-off-by: Evgeny Boger <boger@wirenboard.com>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Diffstat (limited to 'arch/arm/boot/dts/sun8i-r40.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/sun8i-r40.dtsi | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi index 1d87fc0c24ee..c99c92f008a0 100644 --- a/arch/arm/boot/dts/sun8i-r40.dtsi +++ b/arch/arm/boot/dts/sun8i-r40.dtsi @@ -511,6 +511,16 @@ #interrupt-cells = <3>; #gpio-cells = <3>; + can_ph_pins: can-ph-pins { + pins = "PH20", "PH21"; + function = "can"; + }; + + can_pa_pins: can-pa-pins { + pins = "PA16", "PA17"; + function = "can"; + }; + clk_out_a_pin: clk-out-a-pin { pins = "PI12"; function = "clk_out_a"; @@ -926,6 +936,15 @@ #size-cells = <0>; }; + can0: can@1c2bc00 { + compatible = "allwinner,sun8i-r40-can"; + reg = <0x01c2bc00 0x400>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_CAN>; + resets = <&ccu RST_BUS_CAN>; + status = "disabled"; + }; + i2c4: i2c@1c2c000 { compatible = "allwinner,sun6i-a31-i2c"; reg = <0x01c2c000 0x400>; |