diff options
| author | Erwan Le Ray <erwan.leray@st.com> | 2020-05-28 10:40:02 +0300 |
|---|---|---|
| committer | Alexandre Torgue <alexandre.torgue@st.com> | 2020-06-15 13:37:31 +0300 |
| commit | f6b43d89d3b5a31bf4251a26c61e92bf659e74c5 (patch) | |
| tree | c8aa2da0c46a792c3fc571fb61c36dc996d40870 /arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | |
| parent | a5f8a58c6a2da588192392caea16d6988eb94d72 (diff) | |
| download | linux-f6b43d89d3b5a31bf4251a26c61e92bf659e74c5.tar.xz | |
ARM: dts: stm32: fix uart nodes ordering in stm32mp15-pinctrl
Fix usart and uart nodes ordering. Several usart nodes didn't respect
expecting ordering.
Fixes: 077e0638fc83 ("ARM: dts: stm32: Add alternate pinmux for USART2 pins on stm32mp15")
Signed-off-by: Erwan Le Ray <erwan.leray@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Diffstat (limited to 'arch/arm/boot/dts/stm32mp15-pinctrl.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 122 |
1 files changed, 61 insertions, 61 deletions
diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi index 7cf535dc05f5..5ff1323236e1 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -1574,67 +1574,6 @@ }; }; - usart2_pins_a: usart2-0 { - pins1 { - pinmux = <STM32_PINMUX('F', 5, AF7)>, /* USART2_TX */ - <STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = <STM32_PINMUX('D', 6, AF7)>, /* USART2_RX */ - <STM32_PINMUX('D', 3, AF7)>; /* USART2_CTS_NSS */ - bias-disable; - }; - }; - - usart2_sleep_pins_a: usart2-sleep-0 { - pins { - pinmux = <STM32_PINMUX('F', 5, ANALOG)>, /* USART2_TX */ - <STM32_PINMUX('D', 4, ANALOG)>, /* USART2_RTS */ - <STM32_PINMUX('D', 6, ANALOG)>, /* USART2_RX */ - <STM32_PINMUX('D', 3, ANALOG)>; /* USART2_CTS_NSS */ - }; - }; - - usart2_pins_b: usart2-1 { - pins1 { - pinmux = <STM32_PINMUX('F', 5, AF7)>, /* USART2_TX */ - <STM32_PINMUX('A', 1, AF7)>; /* USART2_RTS */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = <STM32_PINMUX('F', 4, AF7)>, /* USART2_RX */ - <STM32_PINMUX('E', 15, AF7)>; /* USART2_CTS_NSS */ - bias-disable; - }; - }; - - usart2_sleep_pins_b: usart2-sleep-1 { - pins { - pinmux = <STM32_PINMUX('F', 5, ANALOG)>, /* USART2_TX */ - <STM32_PINMUX('A', 1, ANALOG)>, /* USART2_RTS */ - <STM32_PINMUX('F', 4, ANALOG)>, /* USART2_RX */ - <STM32_PINMUX('E', 15, ANALOG)>; /* USART2_CTS_NSS */ - }; - }; - - usart3_pins_a: usart3-0 { - pins1 { - pinmux = <STM32_PINMUX('B', 10, AF7)>; /* USART3_TX */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */ - bias-disable; - }; - }; - uart4_pins_a: uart4-0 { pins1 { pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */ @@ -1732,6 +1671,67 @@ }; }; + usart2_pins_a: usart2-0 { + pins1 { + pinmux = <STM32_PINMUX('F', 5, AF7)>, /* USART2_TX */ + <STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('D', 6, AF7)>, /* USART2_RX */ + <STM32_PINMUX('D', 3, AF7)>; /* USART2_CTS_NSS */ + bias-disable; + }; + }; + + usart2_sleep_pins_a: usart2-sleep-0 { + pins { + pinmux = <STM32_PINMUX('F', 5, ANALOG)>, /* USART2_TX */ + <STM32_PINMUX('D', 4, ANALOG)>, /* USART2_RTS */ + <STM32_PINMUX('D', 6, ANALOG)>, /* USART2_RX */ + <STM32_PINMUX('D', 3, ANALOG)>; /* USART2_CTS_NSS */ + }; + }; + + usart2_pins_b: usart2-1 { + pins1 { + pinmux = <STM32_PINMUX('F', 5, AF7)>, /* USART2_TX */ + <STM32_PINMUX('A', 1, AF7)>; /* USART2_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('F', 4, AF7)>, /* USART2_RX */ + <STM32_PINMUX('E', 15, AF7)>; /* USART2_CTS_NSS */ + bias-disable; + }; + }; + + usart2_sleep_pins_b: usart2-sleep-1 { + pins { + pinmux = <STM32_PINMUX('F', 5, ANALOG)>, /* USART2_TX */ + <STM32_PINMUX('A', 1, ANALOG)>, /* USART2_RTS */ + <STM32_PINMUX('F', 4, ANALOG)>, /* USART2_RX */ + <STM32_PINMUX('E', 15, ANALOG)>; /* USART2_CTS_NSS */ + }; + }; + + usart3_pins_a: usart3-0 { + pins1 { + pinmux = <STM32_PINMUX('B', 10, AF7)>; /* USART3_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */ + bias-disable; + }; + }; + usbotg_hs_pins_a: usbotg-hs-0 { pins { pinmux = <STM32_PINMUX('A', 10, ANALOG)>; /* OTG_ID */ |