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| author | Peter Griffin <peter.griffin@linaro.org> | 2015-03-31 10:35:00 +0300 |
|---|---|---|
| committer | Maxime Coquelin <maxime.coquelin@st.com> | 2015-04-30 16:49:26 +0300 |
| commit | b3d37f92a79a329c392712da5e71fdd6c0258c3a (patch) | |
| tree | 66ad707cc7e211fd6f5c819f4e0338f0b30d7e85 /arch/arm/boot/dts/stih407-family.dtsi | |
| parent | d90accb913a7a72172ec6b82f8b8766d9c9bf8bf (diff) | |
| download | linux-b3d37f92a79a329c392712da5e71fdd6c0258c3a.tar.xz | |
ARM: DT: STi: STiH407: Add sata DT nodes.
Now that the miphy28lp is upstream, we can add the sata dt nodes
for stih407 family silicon. This has been tested on b2120 board
J4 (sata0 channel). These nodes are disabled by default as a
special mini pci-e to sata daughter board is required which
isn't shipped with the board.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Acked-by: Lee Jones <lee.jones@linaro.org>
Acked-by: Maxime Coquelin <maxime.coquelin@st.com>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
Diffstat (limited to 'arch/arm/boot/dts/stih407-family.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/stih407-family.dtsi | 45 |
1 files changed, 45 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/stih407-family.dtsi b/arch/arm/boot/dts/stih407-family.dtsi index cdee4a7799b4..85159b823867 100644 --- a/arch/arm/boot/dts/stih407-family.dtsi +++ b/arch/arm/boot/dts/stih407-family.dtsi @@ -8,6 +8,7 @@ */ #include "stih407-pinctrl.dtsi" #include <dt-bindings/mfd/st-lpc.h> +#include <dt-bindings/phy/phy.h> #include <dt-bindings/reset-controller/stih407-resets.h> / { #address-cells = <1>; @@ -471,5 +472,49 @@ clocks = <&clk_s_d3_flexgen CLK_LPC_1>; st,lpc-mode = <ST_LPC_MODE_RTC>; }; + + sata0: sata@9b20000 { + compatible = "st,ahci"; + reg = <0x9b20000 0x1000>; + + interrupts = <GIC_SPI 159 IRQ_TYPE_NONE>; + interrupt-names = "hostc"; + + phys = <&phy_port0 PHY_TYPE_SATA>; + phy-names = "ahci_phy"; + + resets = <&powerdown STIH407_SATA0_POWERDOWN>, + <&softreset STIH407_SATA0_SOFTRESET>, + <&softreset STIH407_SATA0_PWR_SOFTRESET>; + reset-names = "pwr-dwn", "sw-rst", "pwr-rst"; + + clock-names = "ahci_clk"; + clocks = <&clk_s_c0_flexgen CLK_ICN_REG>; + + status = "disabled"; + }; + + sata1: sata@9b28000 { + compatible = "st,ahci"; + reg = <0x9b28000 0x1000>; + + interrupts = <GIC_SPI 170 IRQ_TYPE_NONE>; + interrupt-names = "hostc"; + + phys = <&phy_port1 PHY_TYPE_SATA>; + phy-names = "ahci_phy"; + + resets = <&powerdown STIH407_SATA1_POWERDOWN>, + <&softreset STIH407_SATA1_SOFTRESET>, + <&softreset STIH407_SATA1_PWR_SOFTRESET>; + reset-names = "pwr-dwn", + "sw-rst", + "pwr-rst"; + + clock-names = "ahci_clk"; + clocks = <&clk_s_c0_flexgen CLK_ICN_REG>; + + status = "disabled"; + }; }; }; |