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author | Maxime Coquelin <maxime.coquelin@st.com> | 2014-02-27 16:27:27 +0400 |
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committer | Maxime Coquelin <maxime.coquelin@st.com> | 2014-05-21 16:20:27 +0400 |
commit | f563a5718da590ac3fa4d7500f6f5271628ec1e1 (patch) | |
tree | e75209f7ee29a2e40ac4dd91768e786248c44d01 /arch/arm/boot/dts/stih407-clock.dtsi | |
parent | 59b26c8092eac8c5c2c3ae6926e139a7bb7eb067 (diff) | |
download | linux-f563a5718da590ac3fa4d7500f6f5271628ec1e1.tar.xz |
ARM: dts: Add STiH407 SoC support
The STiH407 is advanced multi-HD AVC processor with 3D graphics acceleration
and 1.5-GHz ARM Cortex-A9 SMP CPU.
Acked-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
Acked-by: Lee Jones <lee.jones@linaro.org>
Acked-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
Diffstat (limited to 'arch/arm/boot/dts/stih407-clock.dtsi')
-rw-r--r-- | arch/arm/boot/dts/stih407-clock.dtsi | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/stih407-clock.dtsi b/arch/arm/boot/dts/stih407-clock.dtsi new file mode 100644 index 000000000000..800f46f009f3 --- /dev/null +++ b/arch/arm/boot/dts/stih407-clock.dtsi @@ -0,0 +1,39 @@ +/* + * Copyright (C) 2014 STMicroelectronics R&D Limited + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/ { + clocks { + /* + * Fixed 30MHz oscillator inputs to SoC + */ + clk_sysin: clk-sysin { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <30000000>; + }; + + /* + * ARM Peripheral clock for timers + */ + arm_periph_clk: arm-periph-clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <600000000>; + }; + + /* + * Bootloader initialized system infrastructure clock for + * serial devices. + */ + clk_ext2f_a9: clockgen-c0@13 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <200000000>; + clock-output-names = "clk-s-icn-reg-0"; + }; + }; +}; |