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| author | Dinh Nguyen <dinguyen@kernel.org> | 2018-09-10 17:12:08 +0300 |
|---|---|---|
| committer | Dinh Nguyen <dinguyen@kernel.org> | 2018-09-17 18:11:28 +0300 |
| commit | 20373e0cb8f7d540ae082a8026f5ae7c27cc6cb3 (patch) | |
| tree | 525331e96d92f85e0165157e6a18952e16d49ef8 /arch/arm/boot/dts/socfpga_arria10.dtsi | |
| parent | cbbc488ed85061a765cf370c3e41f383c1e0add6 (diff) | |
| download | linux-20373e0cb8f7d540ae082a8026f5ae7c27cc6cb3.tar.xz | |
ARM: dts: socfpga: add timer resets for SoCFPGA platform
Add the resets property for all the timers on the Cyclone5/Arria5/Arria10
platforms.
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Diffstat (limited to 'arch/arm/boot/dts/socfpga_arria10.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/socfpga_arria10.dtsi | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index 266c67878a15..4e0c26423d84 100644 --- a/arch/arm/boot/dts/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi @@ -786,6 +786,8 @@ reg = <0xffc02700 0x100>; clocks = <&l4_sp_clk>; clock-names = "timer"; + resets = <&rst SPTIMER0_RESET>; + reset-names = "timer"; }; timer1: timer1@ffc02800 { @@ -794,6 +796,8 @@ reg = <0xffc02800 0x100>; clocks = <&l4_sp_clk>; clock-names = "timer"; + resets = <&rst SPTIMER1_RESET>; + reset-names = "timer"; }; timer2: timer2@ffd00000 { @@ -802,6 +806,8 @@ reg = <0xffd00000 0x100>; clocks = <&l4_sys_free_clk>; clock-names = "timer"; + resets = <&rst L4SYSTIMER0_RESET>; + reset-names = "timer"; }; timer3: timer3@ffd00100 { @@ -810,6 +816,8 @@ reg = <0xffd01000 0x100>; clocks = <&l4_sys_free_clk>; clock-names = "timer"; + resets = <&rst L4SYSTIMER1_RESET>; + reset-names = "timer"; }; uart0: serial0@ffc02000 { |