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authorThor Thayer <tthayer@opensource.altera.com>2016-05-25 19:29:43 +0300
committerDinh Nguyen <dinguyen@opensource.altera.com>2016-06-03 19:03:07 +0300
commit4586e4ea7eddb123322e25b63369fad35976d9e6 (patch)
treeafc8aeadbe989bf0f0ffe52c5c25d70ba0de7fb6 /arch/arm/boot/dts/socfpga_arria10.dtsi
parenta034a8d9e50fda30e0532a0f965bbe70bf8a7bd5 (diff)
downloadlinux-4586e4ea7eddb123322e25b63369fad35976d9e6.tar.xz
ARM: dts: Move Arria10 SDRAM as child of ECC Manager
Changes to support ECC Manager as SDRAM IRQ parent by 1) updating IRQ property values to correct child IRQs 2) moving node under ECC Manager. Signed-off-by: Thor Thayer <tthayer@opensource.altera.com> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Diffstat (limited to 'arch/arm/boot/dts/socfpga_arria10.dtsi')
-rw-r--r--arch/arm/boot/dts/socfpga_arria10.dtsi13
1 files changed, 7 insertions, 6 deletions
diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi
index a2f82bb5d249..21f6c3ce2c52 100644
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -572,12 +572,6 @@
reg = <0xffcfb100 0x80>;
};
- sdramedac {
- compatible = "altr,sdram-edac-a10";
- altr,sdr-syscon = <&sdr>;
- interrupts = <0 2 4>, <0 0 4>;
- };
-
L2: l2-cache@fffff000 {
compatible = "arm,pl310-cache";
reg = <0xfffff000 0x1000>;
@@ -614,6 +608,13 @@
#interrupt-cells = <2>;
ranges;
+ sdramedac {
+ compatible = "altr,sdram-edac-a10";
+ altr,sdr-syscon = <&sdr>;
+ interrupts = <17 IRQ_TYPE_LEVEL_HIGH>,
+ <49 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
l2-ecc@ffd06010 {
compatible = "altr,socfpga-a10-l2-ecc";
reg = <0xffd06010 0x4>;