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authorBoris BREZILLON <boris.brezillon@free-electrons.com>2014-07-10 23:59:53 +0400
committerNicolas Ferre <nicolas.ferre@atmel.com>2014-09-01 21:29:03 +0400
commit71e8a328cb4893cdae88ab7653ede1b3d2605ad8 (patch)
tree7be1833edba1df64b20a344d01853b7264dbbe3e /arch/arm/boot/dts/sama5d3xcm.dtsi
parent2fbda374a2add291bce8036c5084f955bbef7a94 (diff)
downloadlinux-71e8a328cb4893cdae88ab7653ede1b3d2605ad8.tar.xz
ARM: at91/dt: describe rgmii ethernet phy connected to sama5d3xek boards
Add ethernet-phy nodes and specify phy interrupt (connected to pin PB25) and board specific timing configs. Atmel has two different HW designs for its CPU modules: the first one (produced by Embest) is connecting PHYAD[0-2] pins to pull up resistors and the other one (produced by Ronetix) is connecting PHYAD0 to a pull up resistor and PHYAD[1-2] to pull down resistors. As a result, Ronetix design will have its PHY available at address 0x1 and Embest design at 0x7. By defining both phys we're letting the phy core detect the one actually available on the MDIO bus. Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com> Tested-by: Bo Shen <voice.shen@atmel.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Diffstat (limited to 'arch/arm/boot/dts/sama5d3xcm.dtsi')
-rw-r--r--arch/arm/boot/dts/sama5d3xcm.dtsi30
1 files changed, 30 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/sama5d3xcm.dtsi b/arch/arm/boot/dts/sama5d3xcm.dtsi
index f7d8583eef82..962dc28dc37b 100644
--- a/arch/arm/boot/dts/sama5d3xcm.dtsi
+++ b/arch/arm/boot/dts/sama5d3xcm.dtsi
@@ -36,6 +36,36 @@
macb0: ethernet@f0028000 {
phy-mode = "rgmii";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethernet-phy@1 {
+ reg = <0x1>;
+ interrupt-parent = <&pioB>;
+ interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
+ txen-skew-ps = <800>;
+ txc-skew-ps = <3000>;
+ rxdv-skew-ps = <400>;
+ rxc-skew-ps = <3000>;
+ rxd0-skew-ps = <400>;
+ rxd1-skew-ps = <400>;
+ rxd2-skew-ps = <400>;
+ rxd3-skew-ps = <400>;
+ };
+
+ ethernet-phy@7 {
+ reg = <0x7>;
+ interrupt-parent = <&pioB>;
+ interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
+ txen-skew-ps = <800>;
+ txc-skew-ps = <3000>;
+ rxdv-skew-ps = <400>;
+ rxc-skew-ps = <3000>;
+ rxd0-skew-ps = <400>;
+ rxd1-skew-ps = <400>;
+ rxd2-skew-ps = <400>;
+ rxd3-skew-ps = <400>;
+ };
};
pmc: pmc@fffffc00 {