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authorDouglas Anderson <dianders@chromium.org>2019-04-01 20:17:23 +0300
committerHeiko Stuebner <heiko@sntech.de>2019-07-22 02:03:55 +0300
commit95671ec23696d7351b47d159159c6bdcb64fafe4 (patch)
treec828b61060365630aefe5bb394a29ba90b3587b0 /arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi
parent5f9e832c137075045d15cd6899ab0505cfb2ca4b (diff)
downloadlinux-95671ec23696d7351b47d159159c6bdcb64fafe4.tar.xz
ARM: dts: rockchip: Specify rk3288-veyron-chromebook's display timings
Let's document the display timings that most veyron chromebooks (like jaq, jerry, mighty, speedy) have been using out in the field. This uses the standard blankings but a slightly slower clock rate, thus getting a refresh rate 58.3 Hz. NOTE: this won't really do anything except cause DRM to properly report the refresh rate since vop_crtc_mode_fixup() was rounding the pixel clock to 74.25 MHz anyway. Apparently the adjusted rate isn't exposed to userspace so it's important that the rate we're trying to achieve is mostly right. For the downstream kernel change related to this see See https://crrev.com/c/324558. NOTE: minnie uses a different panel will be fixed up in a future patch, so for now we'll just delete the panel timings there. Signed-off-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi')
-rw-r--r--arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi14
1 files changed, 14 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi
index 1cadb522fd0d..6a28ce345ba0 100644
--- a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi
+++ b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi
@@ -91,6 +91,20 @@
power-supply = <&vcc33_lcd>;
backlight = <&backlight>;
+ panel-timing {
+ clock-frequency = <74250000>;
+ hactive = <1366>;
+ hfront-porch = <136>;
+ hback-porch = <60>;
+ hsync-len = <30>;
+ hsync-active = <0>;
+ vactive = <768>;
+ vfront-porch = <8>;
+ vback-porch = <12>;
+ vsync-len = <12>;
+ vsync-active = <0>;
+ };
+
ports {
panel_in: port {
panel_in_edp: endpoint {