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| author | Biju Das <biju.das.jz@bp.renesas.com> | 2022-08-30 19:45:17 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-09-09 13:17:13 +0300 |
| commit | 8419e21affa77048a3b5ab27968d2b729cdf9289 (patch) | |
| tree | 53139a49c26b1887b0f46ad9a03269a584194975 /arch/arm/boot/dts/r9a06g032.dtsi | |
| parent | e357955558e2f958f1efece874f4b5ad4526d042 (diff) | |
| download | linux-8419e21affa77048a3b5ab27968d2b729cdf9289.tar.xz | |
ARM: dts: r9a06g032: Add CAN{0,1} nodes
Add CAN{0,1} nodes to R9A06G032 (RZ/N1) SoC DTSI.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220830164518.1381632-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'arch/arm/boot/dts/r9a06g032.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/r9a06g032.dtsi | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi index 5b97fa85474f..563024c9a4ae 100644 --- a/arch/arm/boot/dts/r9a06g032.dtsi +++ b/arch/arm/boot/dts/r9a06g032.dtsi @@ -423,6 +423,26 @@ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; }; + + can0: can@52104000 { + compatible = "renesas,r9a06g032-sja1000","renesas,rzn1-sja1000"; + reg = <0x52104000 0x800>; + reg-io-width = <4>; + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sysctrl R9A06G032_HCLK_CAN0>; + power-domains = <&sysctrl>; + status = "disabled"; + }; + + can1: can@52105000 { + compatible = "renesas,r9a06g032-sja1000", "renesas,rzn1-sja1000"; + reg = <0x52105000 0x800>; + reg-io-width = <4>; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sysctrl R9A06G032_HCLK_CAN1>; + power-domains = <&sysctrl>; + status = "disabled"; + }; }; timer { |