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authorGeert Uytterhoeven <geert+renesas@glider.be>2017-03-06 19:58:08 +0300
committerSimon Horman <horms+renesas@verge.net.au>2017-03-10 12:20:13 +0300
commitc2f2e266acb39f86bda1461874568ced7eaa6752 (patch)
tree1fbbb6cc47c27365fa161f57946ce584f059031c /arch/arm/boot/dts/r8a7791.dtsi
parent9e58523624fc063ce43ad3ef2bf6d603bda50a5e (diff)
downloadlinux-c2f2e266acb39f86bda1461874568ced7eaa6752.tar.xz
ARM: dts: r8a7791: Add INTC-SYS clock to device tree
Link the ARM GIC to the INTC-SYS module clock, and add it to the "always on" PM Domain, so it can be power managed using that clock. Note that currently the GIC-400 driver doesn't support module clocks nor Runtime PM, so this must be handled as a critical clock. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm/boot/dts/r8a7791.dtsi')
-rw-r--r--arch/arm/boot/dts/r8a7791.dtsi9
1 files changed, 6 insertions, 3 deletions
diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index 7cad65a28f25..525377df16ee 100644
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -117,6 +117,9 @@
<0 0xf1004000 0 0x2000>,
<0 0xf1006000 0 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+ clocks = <&mstp4_clks R8A7791_CLK_INTC_SYS>;
+ clock-names = "clk";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
};
gpio0: gpio@e6050000 {
@@ -1365,10 +1368,10 @@
mstp4_clks: mstp4_clks@e6150140 {
compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
- clocks = <&cp_clk>;
+ clocks = <&cp_clk>, <&zs_clk>;
#clock-cells = <1>;
- clock-indices = <R8A7791_CLK_IRQC>;
- clock-output-names = "irqc";
+ clock-indices = <R8A7791_CLK_IRQC R8A7791_CLK_INTC_SYS>;
+ clock-output-names = "irqc", "intc-sys";
};
mstp5_clks: mstp5_clks@e6150144 {
compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";