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authorKonrad Dybcio <konrad.dybcio@somainline.org>2022-04-15 14:56:13 +0300
committerBjorn Andersson <bjorn.andersson@linaro.org>2022-04-20 02:22:15 +0300
commitb905c34ae7db6b564589f02fa7eac7afaa0294e9 (patch)
tree7d6e7b88212b6e1b1f79182a03091c80843c558b /arch/arm/boot/dts/qcom-msm8974.dtsi
parenteba5e62045b2848042435ae0503d7c2354edf2af (diff)
downloadlinux-b905c34ae7db6b564589f02fa7eac7afaa0294e9.tar.xz
ARM: dts: qcom-msm8974*: Fix UART naming
It's either uart10, or blsp2_uart4, not blsp2_uart10, as there aren't 10 UARTs on BLSP2. Fix the naming to align with what's done in arm64/qcom. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220415115633.575010-4-konrad.dybcio@somainline.org
Diffstat (limited to 'arch/arm/boot/dts/qcom-msm8974.dtsi')
-rw-r--r--arch/arm/boot/dts/qcom-msm8974.dtsi6
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi
index 4c773b63e59a..ccd2593dc8c4 100644
--- a/arch/arm/boot/dts/qcom-msm8974.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
@@ -713,7 +713,7 @@
status = "disabled";
};
- blsp2_uart7: serial@f995d000 {
+ blsp2_uart1: serial@f995d000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0xf995d000 0x1000>;
interrupts = <GIC_SPI 113 IRQ_TYPE_NONE>;
@@ -722,7 +722,7 @@
status = "disabled";
};
- blsp2_uart8: serial@f995e000 {
+ blsp2_uart2: serial@f995e000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0xf995e000 0x1000>;
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
@@ -731,7 +731,7 @@
status = "disabled";
};
- blsp2_uart10: serial@f9960000 {
+ blsp2_uart4: serial@f9960000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0xf9960000 0x1000>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;