diff options
| author | Tony Lindgren <tony@atomide.com> | 2018-07-06 12:55:34 +0300 |
|---|---|---|
| committer | Tony Lindgren <tony@atomide.com> | 2018-07-21 08:20:47 +0300 |
| commit | 4bce678624227b5f5e020a3ff05205d40f6677c0 (patch) | |
| tree | 9560869fe423dade2a2c732e59a9585b99f88439 /arch/arm/boot/dts/omap4.dtsi | |
| parent | 8f42cb7f64c7ffcb2168305ea6e9724cd82562ef (diff) | |
| download | linux-4bce678624227b5f5e020a3ff05205d40f6677c0.tar.xz | |
ARM: dts: omap4: Probe watchdog 3 with ti-sysc
Before updating wdt2 to probe with ti-sysc we want to have wdt3
probed with ti-sysc to avoid having them unnecessarily swap order.
With ti-sysc, we probe child devices at module_init time while
and until l4 abe interconnect is converted to use ti-sysc, wdt3
will probe earlier with legacy platform data.
Cc: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/boot/dts/omap4.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/omap4.dtsi | 31 |
1 files changed, 26 insertions, 5 deletions
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index e554b6e039f3..bbc347755c7b 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -787,12 +787,33 @@ ti,hwmods = "wd_timer2"; }; - wdt3: wdt@40130000 { - compatible = "ti,omap4-wdt", "ti,omap3-wdt"; - reg = <0x40130000 0x80>, /* MPU private access */ - <0x49030000 0x80>; /* L3 Interconnect */ - interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + target-module@40130000 { + compatible = "ti,sysc-omap2", "ti,sysc"; ti,hwmods = "wd_timer3"; + reg = <0x40130000 0x4>, + <0x40130010 0x4>, + <0x40130014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_EMUFREE | + SYSC_OMAP2_SOFTRESET)>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>, + <SYSC_IDLE_SMART_WKUP>; + ti,syss-mask = <1>; + /* Domains (V, P, C): abe, abe_pwrdm, abe_clkdm */ + clocks = <&abe_clkctrl OMAP4_WD_TIMER3_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x40130000 0x1000>, /* MPU private access */ + <0x49030000 0x49030000 0x0080>; /* L3 Interconnect */ + + wdt3: wdt@0 { + compatible = "ti,omap4-wdt", "ti,omap3-wdt"; + reg = <0x0 0x80>; + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; + }; }; mcpdm: mcpdm@40132000 { |