Merge tag 'amlogic-dt-2' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into next/dt

Merge "Amlogic 32-bit DT changes for v4.13 (round 2)" from Kevin Hilman:

- greatly expands DT clock support for meson8b

* tag 'amlogic-dt-2' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic: (22 commits)
  ARM: dts: meson: use the real ethernet clock on Meson8 and Meson8b
  ARM: dts: meson8b: add the SCU device node
  ARM: dts: meson: add USB support on Meson8 and Meson8b
  ARM: dts: meson: add the hardware random number generator
  ARM: dts: meson8: add reserved memory zones
  ARM: dts: meson: add the SAR ADC
  ARM: dts: meson8: add the pins for the SDIO controller
  ARM: dts: meson8: add the PWM_E and PWM_F pins
  ARM: dts: meson: use GIC_SPI and IRQ_TYPE_EDGE_RISING macros
  ARM: dts: meson: use C preprocessor friendly include syntax
  ARM: dts: meson8: fix the IR receiver pins
  clk: meson8b: export the ethernet gate clock
  clk: meson8b: export the USB clocks
  clk: meson8b: export the gate clock for the HW random number generator
  clk: meson8b: export the SDIO clock
  clk: meson8b: export the SAR ADC clocks
  clk: meson-gxbb: un-export the CPU clock
  clk: meson-gxbb: expose UART clocks
  clk: meson-gxbb: expose SPICC gate
  clk: meson-gxbb: expose spdif master clock
  ...

1 files changed, 116 insertions, 8 deletions

diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
index 9b0b3ddbb17e..cada35828931 100644
--- a/arch/arm/boot/dts/meson8.dtsi
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -45,7 +45,7 @@
 
 #include <dt-bindings/clock/meson8b-clkc.h>
 #include <dt-bindings/gpio/meson8-gpio.h>
-/include/ "meson.dtsi"
+#include "meson.dtsi"
 
 / {
 	model = "Amlogic Meson8 SoC";
@@ -83,6 +83,38 @@
 			reg = <0x203>;
 		};
 	};
+
+	reserved-memory {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		/* 2 MiB reserved for Hardware ROM Firmware? */
+		hwrom@0 {
+			reg = <0x0 0x200000>;
+			no-map;
+		};
+
+		/*
+		 * 1 MiB reserved for the "ARM Power Firmware": this is ARM
+		 * code which is responsible for system suspend. It loads a
+		 * piece of ARC code ("arc_power" in the vendor u-boot tree)
+		 * into SRAM, executes that and shuts down the (last) ARM core.
+		 * The arc_power firmware then checks various wakeup sources
+		 * (IR remote receiver, HDMI CEC, WIFI and Bluetooth wakeup or
+		 * simply the power key) and re-starts the ARM core once it
+		 * detects a wakeup request.
+		 */
+		power-firmware@4f00000 {
+			reg = <0x4f00000 0x100000>;
+			no-map;
+		};
+	};
+
+	scu@c4300000 {
+		compatible = "arm,cortex-a9-scu";
+		reg = <0xc4300000 0x100>;
+	};
 }; /* end of / */
 
 &aobus {
@@ -116,6 +148,20 @@
 				function = "i2c_mst_ao";
 			};
 		};
+
+		ir_recv_pins: remote {
+			mux {
+				groups = "remote_input";
+				function = "remote";
+			};
+		};
+
+		pwm_f_ao_pins: pwm-f-ao {
+			mux {
+				groups = "pwm_f_ao";
+				function = "pwm_f_ao";
+			};
+		};
 	};
 };
 
@@ -144,17 +190,34 @@
 			gpio-ranges = <&pinctrl_cbus 0 0 120>;
 		};
 
-		spi_nor_pins: nor {
+		sd_a_pins: sd-a {
 			mux {
-				groups = "nor_d", "nor_q", "nor_c", "nor_cs";
-				function = "nor";
+				groups = "sd_d0_a", "sd_d1_a", "sd_d2_a",
+					"sd_d3_a", "sd_clk_a", "sd_cmd_a";
+				function = "sd_a";
 			};
 		};
 
-		ir_recv_pins: remote {
+		sd_b_pins: sd-b {
 			mux {
-				groups = "remote_input";
-				function = "remote";
+				groups = "sd_d0_b", "sd_d1_b", "sd_d2_b",
+					"sd_d3_b", "sd_clk_b", "sd_cmd_b";
+				function = "sd_b";
+			};
+		};
+
+		sd_c_pins: sd-c {
+			mux {
+				groups = "sd_d0_c", "sd_d1_c", "sd_d2_c",
+					"sd_d3_c", "sd_clk_c", "sd_cmd_c";
+				function = "sd_c";
+			};
+		};
+
+		spi_nor_pins: nor {
+			mux {
+				groups = "nor_d", "nor_q", "nor_c", "nor_cs";
+				function = "nor";
 			};
 		};
 
@@ -168,14 +231,27 @@
 				function = "ethernet";
 			};
 		};
+
+		pwm_e_pins: pwm-e {
+			mux {
+				groups = "pwm_e";
+				function = "pwm_e";
+			};
+		};
 	};
 };
 
 &ethmac {
-	clocks = <&clkc CLKID_CLK81>;
+	clocks = <&clkc CLKID_ETH>;
 	clock-names = "stmmaceth";
 };
 
+&hwrng {
+	compatible = "amlogic,meson8-rng", "amlogic,meson-rng";
+	clocks = <&clkc CLKID_RNG0>;
+	clock-names = "core";
+};
+
 &i2c_AO {
 	clocks = <&clkc CLKID_CLK81>;
 };
@@ -194,6 +270,14 @@
 	arm,filter-ranges = <0x100000 0xc0000000>;
 };
 
+&saradc {
+	compatible = "amlogic,meson8-saradc", "amlogic,meson-saradc";
+	clocks = <&clkc CLKID_XTAL>,
+		<&clkc CLKID_SAR_ADC>,
+		<&clkc CLKID_SANA>;
+	clock-names = "clkin", "core", "sana";
+};
+
 &spifc {
 	clocks = <&clkc CLKID_CLK81>;
 };
@@ -213,3 +297,27 @@
 &uart_C {
 	clocks = <&clkc CLKID_CLK81>;
 };
+
+&usb0 {
+	compatible = "amlogic,meson8-usb", "snps,dwc2";
+	clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
+	clock-names = "otg";
+};
+
+&usb1 {
+	compatible = "amlogic,meson8-usb", "snps,dwc2";
+	clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
+	clock-names = "otg";
+};
+
+&usb0_phy {
+	compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy";
+	clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
+	clock-names = "usb_general", "usb";
+};
+
+&usb1_phy {
+	compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy";
+	clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
+	clock-names = "usb_general", "usb";
+};