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| author | Vladimir Zapolskiy <vz@mleia.com> | 2015-11-20 04:05:05 +0300 |
|---|---|---|
| committer | Vladimir Zapolskiy <vz@mleia.com> | 2016-02-11 04:06:05 +0300 |
| commit | fe86131f9e447b606c40a90124b44a21a40ce54a (patch) | |
| tree | 77d818a5fde716d43f53972c40b59d5265e737c8 /arch/arm/boot/dts/lpc32xx.dtsi | |
| parent | ef5f885ec93b1e6d51a0ef3f4f98d2015b7cab6f (diff) | |
| download | linux-fe86131f9e447b606c40a90124b44a21a40ce54a.tar.xz | |
arm: dts: lpc32xx: add clock controller device node
NXP LPC32xx SoC has a clocking and power control unit (CPC) as a part
of system control block (SCB). CPC is supplied by two external
oscillators and it manages core and most of peripheral clocks, the
change adds SCB and CPC descriptions to shared LPC32xx dtsi file.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Diffstat (limited to 'arch/arm/boot/dts/lpc32xx.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/lpc32xx.dtsi | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi index a9f2d9ac203f..65023c1ff796 100644 --- a/arch/arm/boot/dts/lpc32xx.dtsi +++ b/arch/arm/boot/dts/lpc32xx.dtsi @@ -247,6 +247,23 @@ compatible = "simple-bus"; ranges = <0x20000000 0x20000000 0x30000000>; + /* System Control Block */ + scb { + compatible = "simple-bus"; + ranges = <0x0 0x040004000 0x00001000>; + #address-cells = <1>; + #size-cells = <1>; + + clk: clock-controller@0 { + compatible = "nxp,lpc3220-clk"; + reg = <0x00 0x114>; + #clock-cells = <1>; + + clocks = <&xtal_32k>, <&xtal>; + clock-names = "xtal_32k", "xtal"; + }; + }; + /* * MIC Interrupt controller includes: * MIC @40008000 |