Merge tag 'imx-dt-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/dt

i.MX arm32 device tree changes for 5.4:
 - New board support: ZII i.MX7 RMU2, Kontron i.MX6UL N6310, and
   PHYTEC phyBOARD-Segin based on i.MX6ULL.
 - A series from Andrey Smirnov to update vf610-zii boards on I2C
   pinmux, switch watchdog, GPIO expander IRQ.
 - Move GIC node into soc node for i.MX6 SoCs.
 - Add OV5645 camera support for imx6qdl-wandboard board.
 - Drop unneeded snvs_pwrkey node for imx7d-zii-rpu2 and imx7-colibri.
 - Use simple-mfd instead of simple-bus for i.MX6 ANATOP.
 - Move the native-mode property inside the display-timings node for
   various i.MX25 and i.MX27 boards.
 - Add EDMA devices for i.MX7ULP SoC.
 - A series from Stefan Riedmueller to update imx6ul-phytec-segin board
   on various devices.
 - Use OF graph to describe the display for opos6uldev board.
 - Misc random updates on i.MX7/6 boards.

* tag 'imx-dt-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (53 commits)
  ARM: dts: vf610-zii-scu4-aib: Configure IRQ line for GPIO expander
  ARM: dts: imx6ul-kontron-n6310: Add Kontron i.MX6UL N6310 SoM and boards
  ARM: dts: vf610-zii-cfu1: Slow I2C0 down to 100 kHz
  ARM: dts: pbab01: correct rtc vendor
  ARM: vf610-zii-cfu1: Add node for switch watchdog
  ARM: dts: imx6: drop gpmi-nand address and size cells
  ARM: dts: imx6: replace simple-bus by simple-mfd for anatop
  ARM: dts: imx6qdl-colibri: add phy to fec
  ARM: dts: imx7-colibri: add recovery for I2C for iMX7
  ARM: dts: imx7-colibri: Add sleep pinctrl to ethernet
  ARM: dts: imx7-colibri: prepare module device tree for FlexCAN
  ARM: dts: imx7-colibri: disable HS400
  ARM: dts: imx7-colibri: make sure module supplies are always on
  ARM: dts: imx7d: cl-som-imx7: add compatible for phy
  ARM: dts: imx7d: cl-som-imx7: make ethernet work again
  ARM: dts: imx6ul: Add csi node
  ARM: dts: imx25: mbimxsd25: native-mode is part of display-timings
  ARM: dts: apf27dev: native-mode is part of display-timings
  ARM: dts: edb7211: native-mode is part of display-timings
  ARM: dts: imx27-phytec-phycore-rdk: native-mode is part of display-timings
  ...

Link: https://lore.kernel.org/r/20190825153237.28829-5-shawnguo@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

1 files changed, 32 insertions, 4 deletions

diff --git a/arch/arm/boot/dts/imx7ulp.dtsi b/arch/arm/boot/dts/imx7ulp.dtsi
index 56907bb4b329..6859a3a83750 100644
--- a/arch/arm/boot/dts/imx7ulp.dtsi
+++ b/arch/arm/boot/dts/imx7ulp.dtsi
@@ -101,6 +101,34 @@
 		reg = <0x40000000 0x800000>;
 		ranges;
 
+		edma1: dma-controller@40080000 {
+			#dma-cells = <2>;
+			compatible = "fsl,imx7ulp-edma";
+			reg = <0x40080000 0x2000>,
+				<0x40210000 0x1000>;
+			dma-channels = <32>;
+			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "dma", "dmamux0";
+			clocks = <&pcc2 IMX7ULP_CLK_DMA1>,
+				 <&pcc2 IMX7ULP_CLK_DMA_MUX1>;
+		};
+
 		crypto: crypto@40240000 {
 			compatible = "fsl,sec-v4.0";
 			#address-cells = <1>;
@@ -201,12 +229,12 @@
 			clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
 				 <&scg1 IMX7ULP_CLK_NIC1_DIV>,
 				 <&pcc2 IMX7ULP_CLK_USDHC0>;
-			clock-names ="ipg", "ahb", "per";
+			clock-names = "ipg", "ahb", "per";
 			assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC0>;
 			assigned-clock-parents = <&scg1 IMX7ULP_CLK_NIC1_DIV>;
 			bus-width = <4>;
 			fsl,tuning-start-tap = <20>;
-			fsl,tuning-step= <2>;
+			fsl,tuning-step = <2>;
 			status = "disabled";
 		};
 
@@ -217,12 +245,12 @@
 			clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
 				 <&scg1 IMX7ULP_CLK_NIC1_DIV>,
 				 <&pcc2 IMX7ULP_CLK_USDHC1>;
-			clock-names ="ipg", "ahb", "per";
+			clock-names = "ipg", "ahb", "per";
 			assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC1>;
 			assigned-clock-parents = <&scg1 IMX7ULP_CLK_NIC1_DIV>;
 			bus-width = <4>;
 			fsl,tuning-start-tap = <20>;
-			fsl,tuning-step= <2>;
+			fsl,tuning-step = <2>;
 			status = "disabled";
 		};