diff options
| author | Anson Huang <anson.huang@nxp.com> | 2018-12-07 13:03:39 +0300 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2019-01-10 09:55:57 +0300 |
| commit | 13c033bc630a2df51931d16ea5fb81710ad2e0b2 (patch) | |
| tree | fee4e2bc4e437a9925cd8fe4f3162a621b5f123f /arch/arm/boot/dts/imx7ulp.dtsi | |
| parent | bfeffd155283772bbe78c6a05dec7c0128ee500c (diff) | |
| download | linux-13c033bc630a2df51931d16ea5fb81710ad2e0b2.tar.xz | |
ARM: dts: imx7ulp: add HSRUN mode clocks
i.MX7ULP can switch CPU between RUN mode and HSRUN mode
by programming SMC1 register, different clock sources
will be used for CPU in different modes, so SMC1 can be
abstracted as a clock controller for CPU clock switch,
this patch adds support for it.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm/boot/dts/imx7ulp.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/imx7ulp.dtsi | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/imx7ulp.dtsi b/arch/arm/boot/dts/imx7ulp.dtsi index 931b2754b099..b86daf73bb89 100644 --- a/arch/arm/boot/dts/imx7ulp.dtsi +++ b/arch/arm/boot/dts/imx7ulp.dtsi @@ -199,9 +199,13 @@ assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>; }; - smc1: smc1@40410000 { + smc1: clock-controller@40410000 { compatible = "fsl,imx7ulp-smc1"; reg = <0x40410000 0x1000>; + #clock-cells = <1>; + clocks = <&scg1 IMX7ULP_CLK_CORE_DIV>, + <&scg1 IMX7ULP_CLK_HSRUN_CORE_DIV>; + clock-names = "divcore", "hsrun_divcore"; }; pcc3: clock-controller@40b30000 { |