diff options
| author | Fabio Estevam <festevam@gmail.com> | 2018-12-03 20:40:19 +0300 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2018-12-10 05:03:04 +0300 |
| commit | 0c29339d53bf7cf3b96847081ad7f64e835de4d4 (patch) | |
| tree | bc13d5cd7a3752feb26b0a5df1f6b37ae930aee0 /arch/arm/boot/dts/imx6ul.dtsi | |
| parent | f46af111c6948a842708d68d16564666ea2d1c68 (diff) | |
| download | linux-0c29339d53bf7cf3b96847081ad7f64e835de4d4.tar.xz | |
ARM: dts: imx6ul: Correct mask for GIC PPI interrupts
The GIC_CPU_MASK_SIMPLE() macro should take as its argument the actual
number of CPU cores the interrupt controller is wired to.
i.MX6UL contains a single Cortex-A7, hence the second interrupt specifier
cell for Private Peripheral Interrupts should use "GIC_CPU_MASK_SIMPLE(1)".
Tested on a imx6ul-evk.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm/boot/dts/imx6ul.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/imx6ul.dtsi | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi index 99c366303d73..0efc85f1bb95 100644 --- a/arch/arm/boot/dts/imx6ul.dtsi +++ b/arch/arm/boot/dts/imx6ul.dtsi @@ -94,7 +94,7 @@ intc: interrupt-controller@a01000 { compatible = "arm,gic-400", "arm,cortex-a7-gic"; - interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; #interrupt-cells = <3>; interrupt-controller; interrupt-parent = <&intc>; @@ -106,10 +106,10 @@ timer { compatible = "arm,armv7-timer"; - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; interrupt-parent = <&intc>; status = "disabled"; }; |