diff options
| author | Dmitry Lavnikevich <d.lavnikevich@sam-solutions.com> | 2014-11-04 16:05:47 +0300 |
|---|---|---|
| committer | Shawn Guo <shawn.guo@linaro.org> | 2014-11-23 10:08:11 +0300 |
| commit | d76fab80ef32a7421feb7b71b6e2fdddf3a036fd (patch) | |
| tree | 6cbb2bd8b47eb2feaff365cc01b1e10c94826560 /arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi | |
| parent | e1bf86ace4d2ac915e130699aefe6e9d9bc7164d (diff) | |
| download | linux-d76fab80ef32a7421feb7b71b6e2fdddf3a036fd.tar.xz | |
ARM: dts: pbab01: move i2c pins and frequency configuration into pfla02
Since pins and frequency are specific to module (pfla02), not base board
(pbab02), it is better to be initialized in corresponding dts file.
This patch fixes i2c2, i2c3 pin configuration which caused messages:
imx6q-pinctrl 20e0000.iomuxc: no groups defined in /soc/aips-bus@02000000/iomuxc@020e0000/i2c2grp
imx6q-pinctrl 20e0000.iomuxc: no groups defined in /soc/aips-bus@02000000/iomuxc@020e0000/i2c3grp
imx6q-pinctrl 20e0000.iomuxc: unable to find group for node i2c2grp
imx6q-pinctrl 20e0000.iomuxc: unable to find group for node i2c3grp
Signed-off-by: Dmitry Lavnikevich <d.lavnikevich@sam-solutions.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Diffstat (limited to 'arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi index 0e50bb0a6b94..aa2275671d2c 100644 --- a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi +++ b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi @@ -162,6 +162,18 @@ }; }; +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clock-frequency = <100000>; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + clock-frequency = <100000>; +}; + &iomuxc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hog>; @@ -235,6 +247,20 @@ >; }; + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 + >; + }; + pinctrl_uart3: uart3grp { fsl,pins = < MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 |