Merge tag 'imx-dt-4.19' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt

i.MX device tree update for 4.19:
 - Add device tree support for i.MX6SLL SoC.
 - New board support: ConnectCore 6UL System-On-Module and SBC Express;
   ZII SCU2 Mezz, SCU3 ESB, SSMB SPU3 and CFU1 board; i.MX6SLL EVK
   board; Engicam i.CoreM6 1.5 Quad/Dual MIPI; LogicPD MX31Lite board;
   i.MX53 HSC/DDC boards from K+P.
 - Remove fake regulator bus container node and enable USB OTG support
   for i.MX6 wandboard and riotboard.
 - Populate RAVE SP EEPROM, backlight, power button and watchdog devices
   for ZII boards.
 - Add cooling-cells for cpufreq cooling device, and add OPP properties
   for all CPUs.
 - A series from Anson Huang to enable LCD panel and backlight support
   for imx6sll-evk board.
 - Make pfuze100 sw4 regulator always-on for for a few Freescale/NXP
   development boards, because the regulator is critical there and
   cannot be turned off.
 - Add more device support for i.MX5: AIPSTZ, SAHARA Crypto, M4IF,
   Tigerp, PMU, CodaHx4 VPU.
 - Enable PMU secure-reg-access for imx51-babbage, imx51-zii-rdu1 and
   imx53-ppd board.
 - Switch more device tree license to use SPDX identifier.
 - Switch to use OF graph to describe the display for imx7d-nitrogen7.
 - Add chosen/stdout-path for more boards, so that earlycon can be
   enabled more easily on kernel cmdline.
 - Convert GPC to new device tree bindings and add Vivante gpu nodes
   for i.MX6SL SoC.
 - Add more device support for imx6dl-mamoj board: parallel display,
   WiFi and USB.
 - A series from Stefan Agner to update i.MX6 apalis/colibri boards on
   various aspects: SD/MMC card detection, regulators, etc.

* tag 'imx-dt-4.19' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (96 commits)
  ARM: dts: imx7d: remove "operating-points" property for cpu1
  ARM: dts: vf610-zii-ssmb-spu3: Fix W=1 level warnings
  ARM: dts: vf610: Add ZII CFU1 board
  ARM: dts: imx6dl-mamoj: Add usb host and device support
  ARM: dts: imx6dl-mamoj: Add Wifi support
  ARM: dts: imx6dl-mamoj: Add parallel display support
  ARM: dts: vf610: Add ZII SSMB SPU3 board
  ARM: dts: imx6ul-pico-hobbit: Do not hardcode the memory size
  ARM: dts: imx6sl-evk: make pfuze100 sw4 always on
  ARM: dts: imx6sll-evk: make pfuze100 sw4 always on
  ARM: dts: imx6sx-sdb-reva: make pfuze100 sw4 always on
  ARM: dts: imx6qdl-sabresd: make pfuze100 sw4 always on
  ARM: dts: imx6sl-evk: add missing GPIO iomux setting
  ARM: dts: imx51-zii-scu3-esb: Fix RAVE SP watchdog compatible string
  ARM: dts: imx51-zii-scu3-esb: Add switch IRQ line pinumx config
  ARM: dts: imx6sx-nitrogen6sx: remove obsolete display configuration
  ARM: dts: imx7d-nitrogen7: use OF graph to describe the display
  ARM: dts: imx: Switch Boundary Devices boards to SPDX identifier
  ARM: dts: imx6sl: Add vivante gpu nodes
  ARM: dts: imx6sll-evk: enable SEIKO 43WVF1G lcdif panel
  ...

Signed-off-by: Olof Johansson <olof@lixom.net>

1 files changed, 85 insertions, 3 deletions

diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 77f8f030dd07..0193ee6fe964 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -38,6 +38,7 @@
 				396000	1175000
 			>;
 			clock-latency = <61036>; /* two CLK32 periods */
+			#cooling-cells = <2>;
 			clocks = <&clks IMX6QDL_CLK_ARM>,
 				 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
 				 <&clks IMX6QDL_CLK_STEP>,
@@ -50,25 +51,106 @@
 			soc-supply = <&reg_soc>;
 		};
 
-		cpu@1 {
+		cpu1: cpu@1 {
 			compatible = "arm,cortex-a9";
 			device_type = "cpu";
 			reg = <1>;
 			next-level-cache = <&L2>;
+			operating-points = <
+				/* kHz    uV */
+				1200000 1275000
+				996000  1250000
+				852000  1250000
+				792000  1175000
+				396000  975000
+			>;
+			fsl,soc-operating-points = <
+				/* ARM kHz  SOC-PU uV */
+				1200000 1275000
+				996000	1250000
+				852000	1250000
+				792000	1175000
+				396000	1175000
+			>;
+			clock-latency = <61036>; /* two CLK32 periods */
+			clocks = <&clks IMX6QDL_CLK_ARM>,
+				 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
+				 <&clks IMX6QDL_CLK_STEP>,
+				 <&clks IMX6QDL_CLK_PLL1_SW>,
+				 <&clks IMX6QDL_CLK_PLL1_SYS>;
+			clock-names = "arm", "pll2_pfd2_396m", "step",
+				      "pll1_sw", "pll1_sys";
+			arm-supply = <&reg_arm>;
+			pu-supply = <&reg_pu>;
+			soc-supply = <&reg_soc>;
 		};
 
-		cpu@2 {
+		cpu2: cpu@2 {
 			compatible = "arm,cortex-a9";
 			device_type = "cpu";
 			reg = <2>;
 			next-level-cache = <&L2>;
+			operating-points = <
+				/* kHz    uV */
+				1200000 1275000
+				996000  1250000
+				852000  1250000
+				792000  1175000
+				396000  975000
+			>;
+			fsl,soc-operating-points = <
+				/* ARM kHz  SOC-PU uV */
+				1200000 1275000
+				996000	1250000
+				852000	1250000
+				792000	1175000
+				396000	1175000
+			>;
+			clock-latency = <61036>; /* two CLK32 periods */
+			clocks = <&clks IMX6QDL_CLK_ARM>,
+				 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
+				 <&clks IMX6QDL_CLK_STEP>,
+				 <&clks IMX6QDL_CLK_PLL1_SW>,
+				 <&clks IMX6QDL_CLK_PLL1_SYS>;
+			clock-names = "arm", "pll2_pfd2_396m", "step",
+				      "pll1_sw", "pll1_sys";
+			arm-supply = <&reg_arm>;
+			pu-supply = <&reg_pu>;
+			soc-supply = <&reg_soc>;
 		};
 
-		cpu@3 {
+		cpu3: cpu@3 {
 			compatible = "arm,cortex-a9";
 			device_type = "cpu";
 			reg = <3>;
 			next-level-cache = <&L2>;
+			operating-points = <
+				/* kHz    uV */
+				1200000 1275000
+				996000  1250000
+				852000  1250000
+				792000  1175000
+				396000  975000
+			>;
+			fsl,soc-operating-points = <
+				/* ARM kHz  SOC-PU uV */
+				1200000 1275000
+				996000	1250000
+				852000	1250000
+				792000	1175000
+				396000	1175000
+			>;
+			clock-latency = <61036>; /* two CLK32 periods */
+			clocks = <&clks IMX6QDL_CLK_ARM>,
+				 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
+				 <&clks IMX6QDL_CLK_STEP>,
+				 <&clks IMX6QDL_CLK_PLL1_SW>,
+				 <&clks IMX6QDL_CLK_PLL1_SYS>;
+			clock-names = "arm", "pll2_pfd2_396m", "step",
+				      "pll1_sw", "pll1_sys";
+			arm-supply = <&reg_arm>;
+			pu-supply = <&reg_pu>;
+			soc-supply = <&reg_soc>;
 		};
 	};