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| author | Daniel Schultz <d.schultz@phytec.de> | 2018-03-05 15:45:11 +0300 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2018-04-16 15:13:04 +0300 |
| commit | c887f5b0210c5c7d30e2da47c37798eb6f37f563 (patch) | |
| tree | 6a46ca2cf7980f49387ca334b6dce30f5b6d4409 /arch/arm/boot/dts/bcm4709-netgear-r7000.dts | |
| parent | 5f501b42f35678615bef3f00dfb277eff1c58dfb (diff) | |
| download | linux-c887f5b0210c5c7d30e2da47c37798eb6f37f563.tar.xz | |
ARM: dts: rockchip: Add dp83867 CLK_OUT muxing on rk3288-phycore-som
The CLK_O_SEL default is synchronous to XI input clock, which is 25 MHz.
Set CLK_O_SEL to channel A transmit clock so we have 125 MHz on CLK_OUT.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'arch/arm/boot/dts/bcm4709-netgear-r7000.dts')
0 files changed, 0 insertions, 0 deletions