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| author | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2018-09-01 16:04:57 +0300 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2018-09-26 17:50:38 +0300 |
| commit | e0cffa9a1b64099f537887712ba3802f92429675 (patch) | |
| tree | 11a0b1aef873a965d1d0f919a65ce5944bae4c8b /arch/arm/boot/dts/at91sam9263ek.dts | |
| parent | a052d2b67f00dfc6181d7dea6ff911bc7175f52a (diff) | |
| download | linux-e0cffa9a1b64099f537887712ba3802f92429675.tar.xz | |
ARM: tegra: apalis-tk1: reorder cpu dfll clock properties
Reorder CPU DFLL clock properties.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'arch/arm/boot/dts/at91sam9263ek.dts')
0 files changed, 0 insertions, 0 deletions