diff options
| author | Joachim Eastwood <manabian@gmail.com> | 2012-12-04 22:10:59 +0400 |
|---|---|---|
| committer | Nicolas Ferre <nicolas.ferre@atmel.com> | 2013-02-07 19:40:09 +0400 |
| commit | ce3b2630fd4737a3f9aa9119d40647a9ac7baa38 (patch) | |
| tree | 540a75f680dccc68f8165f4044a808a58fe070a7 /arch/arm/boot/dts/at91rm9200.dtsi | |
| parent | 883a07f69cc7c6f40e5e57677f268267781d5b01 (diff) | |
| download | linux-ce3b2630fd4737a3f9aa9119d40647a9ac7baa38.tar.xz | |
ARM: at91: add EMAC bindings to RM9200 DT
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Diffstat (limited to 'arch/arm/boot/dts/at91rm9200.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/at91rm9200.dtsi | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi index 6ff27bba6296..b0268a5f4b4e 100644 --- a/arch/arm/boot/dts/at91rm9200.dtsi +++ b/arch/arm/boot/dts/at91rm9200.dtsi @@ -127,6 +127,16 @@ status = "disable"; }; + macb0: ethernet@fffbc000 { + compatible = "cdns,at91rm9200-emac", "cdns,emac"; + reg = <0xfffbc000 0x4000>; + interrupts = <24 4 3>; + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_macb_rmii>; + status = "disabled"; + }; + pinctrl@fffff400 { #address-cells = <1>; #size-cells = <1>; @@ -246,6 +256,34 @@ }; }; + macb { + pinctrl_macb_rmii: macb_rmii-0 { + atmel,pins = + <0 7 0x1 0x0 /* PA7 periph A */ + 0 8 0x1 0x0 /* PA8 periph A */ + 0 9 0x1 0x0 /* PA9 periph A */ + 0 10 0x1 0x0 /* PA10 periph A */ + 0 11 0x1 0x0 /* PA11 periph A */ + 0 12 0x1 0x0 /* PA12 periph A */ + 0 13 0x1 0x0 /* PA13 periph A */ + 0 14 0x1 0x0 /* PA14 periph A */ + 0 15 0x1 0x0 /* PA15 periph A */ + 0 16 0x1 0x0>; /* PA16 periph A */ + }; + + pinctrl_macb_rmii_mii: macb_rmii_mii-0 { + atmel,pins = + <1 12 0x2 0x0 /* PB12 periph B */ + 1 13 0x2 0x0 /* PB13 periph B */ + 1 14 0x2 0x0 /* PB14 periph B */ + 1 15 0x2 0x0 /* PB15 periph B */ + 1 16 0x2 0x0 /* PB16 periph B */ + 1 17 0x2 0x0 /* PB17 periph B */ + 1 18 0x2 0x0 /* PB18 periph B */ + 1 19 0x2 0x0>; /* PB19 periph B */ + }; + }; + mmc0 { pinctrl_mmc0_clk: mmc0_clk-0 { atmel,pins = |