diff options
| author | Wenyou Yang <wenyou.yang@atmel.com> | 2017-04-24 04:12:17 +0300 |
|---|---|---|
| committer | Alexandre Belloni <alexandre.belloni@free-electrons.com> | 2017-05-15 12:42:09 +0300 |
| commit | bc6d5d7666b73cbd8d6ed6ee3aece84903fffe0b (patch) | |
| tree | 3c887fa7b3616028a600d318477d49c1dfa6e9ff /arch/arm/boot/dts/at91-sama5d2_xplained.dts | |
| parent | 43c3a448b3570654876eb5a111e94356dcbde37e (diff) | |
| download | linux-bc6d5d7666b73cbd8d6ed6ee3aece84903fffe0b.tar.xz | |
ARM: dts: at91: sama5d2: add m_can nodes
Add nodes to support the Controller Area Network(M_CAN) on SAMA5D2.
The version of M_CAN IP core is 3.1.0 (CREL = 0x31040730).
As said in SAMA5D2 datasheet, the CAN clock is recommended to use
frequencies of 20, 40 or 80 MHz. To achieve these frequencies,
PMC GCLK3 must select the UPLLCK(480 MHz) as source clock and
divide by 24, 12, or 6. So, the "assigned-clock-rates" property
has three options: 20000000, 40000000, and 80000000.
The "assigned-clock-parents" property should be referred to utmi
fixedly.
The MSBs [bits 31:16] of the CAN Message RAM for CAN0 and CAN1 are
default configured in 0x00200000. To avoid conflict with SRAM map
for PM, change them to 0x00210000 in the AT91Bootstrap via setting
the CAN Memories Address-based Register(SFR_CAN) of SFR.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Tested-by: Quentin Schulz <quentin.schulz@free-electrons.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Diffstat (limited to 'arch/arm/boot/dts/at91-sama5d2_xplained.dts')
| -rw-r--r-- | arch/arm/boot/dts/at91-sama5d2_xplained.dts | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/at91-sama5d2_xplained.dts b/arch/arm/boot/dts/at91-sama5d2_xplained.dts index 0bef9e0b89c6..37de94fc9b5a 100644 --- a/arch/arm/boot/dts/at91-sama5d2_xplained.dts +++ b/arch/arm/boot/dts/at91-sama5d2_xplained.dts @@ -258,6 +258,12 @@ status = "okay"; }; + can0: can@f8054000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can0_default>; + status = "okay"; + }; + uart3: serial@fc008000 { atmel,use-dma-rx; atmel,use-dma-tx; @@ -322,6 +328,18 @@ bias-disable; }; + pinctrl_can0_default: can0_default { + pinmux = <PIN_PC10__CANTX0>, + <PIN_PC11__CANRX0>; + bias-disable; + }; + + pinctrl_can1_default: can1_default { + pinmux = <PIN_PC26__CANTX1>, + <PIN_PC27__CANRX1>; + bias-disable; + }; + pinctrl_charger_chglev: charger_chglev { pinmux = <PIN_PA12__GPIO>; bias-disable; @@ -469,6 +487,12 @@ }; }; + + can1: can@fc050000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1_default>; + status = "okay"; + }; }; }; |